Performance and manufacturability trade-offs of pattern minimization for sub-22nm technology nodes

Vyacheslav V. Rovner; Tejas Jhaveri; Daniel Morris; Andrzej Strojwas; Larry Pileggi

doi:10.1117/12.879514

4 April 2011 Performance and manufacturability trade-offs of pattern minimization for sub-22nm technology nodes

Vyacheslav V. Rovner, Tejas Jhaveri, Daniel Morris, Andrzej Strojwas, Larry Pileggi

Proceedings Volume 7974, Design for Manufacturability through Design-Process Integration V; 79740I (2011) https://doi.org/10.1117/12.879514
Event: SPIE Advanced Lithography, 2011, San Jose, California, United States

Abstract

The traditional design rule paradigm of defining the illegal areas of the design space has been deteriorating at the advanced technology nodes. Radical design space restrictions, advocated by the regular design fabrics methodology, provide an opportunity to reshape the design/manufacturing interface by constraining the layout to a set of allowable patterns. As such, this would allow for guaranteed convergence of the source mask optimization techniques (SMO) and complete validation of the legal design space during technology development and ramp. However, the number of the unique patterns generated by the layout adhering to even the simplistic gridded design rules prohibits this approach. Nevertheless, we have found that just 10% of the unique geometric patterns are sufficient to represent 90% of all layout pattern instances. Furthermore, the overall number of layout patterns on Active, Contact, and Metal-1 design layers can be reduced through modification of existing layout shapes in the final layout database and insertion of non-essential layout features. Unlike the 'dummy fill' used for chemical mechanical polishing (CMP), the newly added shapes must resemble the patterning of the functional design features and be inserted in close proximity to them. In this paper, we evaluate the digital circuit performance impact of the additional layout parasitics introduced by these 'dummy' features. In particular, we have found that a significant pattern count reduction can be achieved with minimal performance penalty. These results have been used at PDF Solutions to enable a correct by construction layout style, such as the templates and connectors-based layout methodology presented in the companion paper.

Citation Download Citation

Vyacheslav V. Rovner, Tejas Jhaveri, Daniel Morris, Andrzej Strojwas, and Larry Pileggi "Performance and manufacturability trade-offs of pattern minimization for sub-22nm technology nodes", Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 79740I (4 April 2011); https://doi.org/10.1117/12.879514

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available