Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14 nm node

Kaushik Vaidyanathan; Siew Hoon Ng; Daniel Morris; Neal Lafferty; Lars Liebmann; Mitchell Bender; Wenbin Huang; Kafai Lai; Larry Pileggi; Andrzej Strojwas

doi:10.1117/12.916104

14 March 2012 Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14 nm node

Kaushik Vaidyanathan, Siew Hoon Ng, Daniel Morris, Neal Lafferty, Lars Liebmann, Mitchell Bender, Wenbin Huang, Kafai Lai, Larry Pileggi, Andrzej Strojwas

Author Affiliations +

Proceedings Volume 8327, Design for Manufacturability through Design-Process Integration VI; 83270K (2012) https://doi.org/10.1117/12.916104
Event: SPIE Advanced Lithography, 2012, San Jose, California, United States

Abstract

The 14 nm node is seeing the dominant use of three-dimensional FinFET architectures, local interconnects, multiple patterning processes and restricted design rules. With the adoption of these new process technologies and design styles, it becomes necessary to rethink the standard cell library design methodologies that proved successful in the past. In this paper, we compare the design efficiency and manufacturability of standard cell libraries that use either unidirectional or bidirectional Metal 1. In contrast to previous nodes, a 14 nm 9-track unidirectional standard cell layout results in up to 20% lower energy-delay-area product as compared to the 9-track bidirectional standard cell layout. Manufacturability assessment shows that the unidirectional standard cell layouts save one exposure on Metal 1, reduces process variability by 10% and layout construct count by 2-3X. As a result, the unidirectional standard cell layout could serve as a key enabler for affordable scaling.

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Kaushik Vaidyanathan, Siew Hoon Ng, Daniel Morris, Neal Lafferty, Lars Liebmann, Mitchell Bender, Wenbin Huang, Kafai Lai, Larry Pileggi, and Andrzej Strojwas "Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14 nm node", Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270K (14 March 2012); https://doi.org/10.1117/12.916104

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