Given a circuit pattern to print, how can we determine the optimal lithography approach? If traditional lithography provides sufficient process latitude, there is little reason to use resolution enhancement techniques (RETs). Otherwise we need to pick the appropriate enhancement technique or combination of techniques. An effective procedure for choosing suitable techniques comprises:
1. include applicable approaches based on physical principles,
2. select promising techniques by simulation,
3. determine actual process latitude by experimentation.
This three-step methodology is demonstrated via a 1-Gb dynamic random access memory (DRAM) example.
7.1 Critical levels
The DRAM under consideration is a trench capacitor design. Since the storage cell is of prime importance, we examine only printing of the DRAM cell layout. Logic circuitries such as column and row decoders peripheral to the cell array are not examined. Shown in Fig. 7.1, the four critical lithography levels are storage, isolation, word line, and bit line contact. The storage level [Fig. 7.1 (a)] defines capacitor trenches which hold the charges.