Multiple-Exposure-Patterning-Enhanced Digital Logic Design

doi:10.1117/3.2217861.ch2

Book: Design Technology Co-Optimization in the Era of Sub-Resolution IC Scaling

Author(s): Lars W. Liebmann, Lawrence Pileggi, Kaushik Vaidyanathan

Published: 2016

https://doi.org/10.1117/3.2217861.ch2

Author Affiliations +

Abstract

To provide a very rudimentary level of design insight as part of the overall DTCO discussion, this section reviews the primary elements of a digital standard-cell design flow. Of course, a complete system-on-chip (SoC) design contains many more design elements in addition to auto-routed digital logic blocks: memory blocks, analog circuits, I/O designs, and e-fuses, to name a few. Each undergoes DTCO negotiations in a very similar fashion to the elements of the digital-logic-design flow and will be discussed in more detail in Section 3.6.1.