This PDF file contains the front matter associated with SPIE Proceedings Volume 10451, including the Title Page, Copyright information, Table of Contents, and Conference Committee listing.

The virtuous cycle of integrated-circuit (IC) technology advancement has resulted in the proliferation of information and communication technology with revolutionary economic and social impact. Advancements in lithography have been critical to sustaining Moore’s law over the past 50+ years. As the minimum feature size of an IC has been scaled down well below the wavelength of light used in the photolithographic process, however, the semiconductor industry has faced a growing challenge of continuing to increase the density of transistors at ever lower cost per transistor. This paper discusses a cost-effective method for defining sublithographic features that can help to extend the era of Moore’s Law.

Captive and merchant mask makers participated in an anonymous survey in the summer of 2017 to capture the profile of the mask industry for the period of July 2016 through June 2017. A mask industry survey has been conducted for the 15th time in the past 16 years. Sematech ran the mask industry survey for 13 years through 2013. In 2015, the eBeam Initiative invested in reviving a subset of the survey called the Mask Maker Survey. The eBeam Initiative’s third Mask Maker Survey in 2017 covers a number of questions related to the profile of the mask industry, from overall number of masks to pattern generation type. The survey addresses questions about data preparation, writing and delivery times. Mask yields and returns are captured along with a new question on the usage of mask process correction (MPC) by ground rules. The eBeam Initiative also conducts an annual Perceptions Survey of mask industry luminaries.

To achieve the ultimate resolution and process control from an optical (193i 1.35NA) scanner system, it is desirable to be able to exploit both source and mask degrees of freedom to create the imaging conditions for any given set of patterns that comprise a photomask. For the source it has been possible to create an illumination system that allows for almost no restrictions in the location and intensity of source points in the illumination plane [1]. For the mask, it has been harder to approach the ideal continuous phase and transmission mask that theoretically would have the best imaging performance. Mask blanks and processing requirements have limited us to binary (1 and 0 amplitude, or 1 and -0.25 amplitude (6% attenuated PSM)) or Alternating PSM (1, 0 and -1 amplitude) solutions. Furthermore, mask writing (and OPC algorithms) have limited us to Manhattan layouts for full chip logic solutions. Recent developments in the areas of mask design and newly developed Multi-Beam Mask Writers (MBMW) have removed the mask limitation to Manhattan geometries [2]. In this paper we consider some of the manufacturing challenges for these curvilinear masks.

Mask Data Preparation (MDP) fracture takes IC layout data and decomposes (“fractures”) complex polygons into rectilinear and trapezoidal primitives suitable for mask writers. For rectilinear polygons, the total number of decomposed figures from a given polygon is bounded mathematically in terms of the polygon’s reflex vertex count. Such geometric-based decomposition algorithms can be further optimized by considering parameters associated with VSB mask writers. This paper describes our efforts to reduce mask write time while maintaining CD quality by further optimizing the underlying algorithms. The optimization results are statistically analyzed with variation of shot size and sliver size. In addition, a case study is conducted to explore how sliver size specification impacts both shot count and fracturing quality.

Throughout this report, we demonstrate the benefits of lithography simulation for the fabrication of the photonic devices using a rigorous verification flow. In our case, we report the application rigorous lithography simulation to predict the fabrication imperfections of silicon photonic devices during the lithography process. Resist calibration has been performed, with both FEM CD and resist profile simulation results matching well with the wafer results for the design rule patterns. SEM overlay proves that the simulation contours agree with the wafer images for the design rule test patterns.

NuFlare has several VSB mask writers which read in patterns in the VSB12 format. Each type of machine has restrictions over the input VSB12 chips they can read; mainly the file-size of input files. MDP software tools — which are used to convert the customers layout designs into VSB12 format files — can generate VSB12 chips for a given VSB12 machine model. However, the generated VSB12 chip might not be compatible for printing in other VSB12 machine models other than the one specified. This is very inconvenient for some mask manufacturers, as it hinders the flexibility of their processes. They might require to write a previously generated VSB12 chip in a different machine model than the originally specified one. This paper presents a tool that can convert VSB12 jobdeck files to be compatible with a different VSB12 machine model than originally intended. It generates the new VSB12 jobdeck in a time considerably shorter than refracturing it with a MDP tool and comparable to just file copying it.

With both 193i multiple patterning and EUV technologies, the constraints on the mask manufacturability are becoming increasingly stringent. The necessity for understanding curvilinear shapes implicitly in design (for ILT and EUV) or OPC correction (corner-rounding effects) along with new multi-beam mask writing systems mean the mask manufacturers are at an inflection point: whether the mask shapes are described as curvilinear targets or complex rectilinear targets, the actual mask shapes after exposure are curvilinear and must be accounted for correctly for wafer lithography. We present a GPU-accelerated intrinsically curvilinear mask data preparation system, compatible with both VSB and multi-beam systems, that is capable of full-ship simultaneous shape and dose correction using arbitrary (non-Gaussian) kernels for model shape and dose effects.

Curvilinear mask shapes have become one of the resolution enhancement technology options in optical lithography. While this technology has been demonstrated already at the 65 nm node [1], it becomes a more important option beyond the 14 nm node. One of the limiting factors for deploying curvilinear mask shapes for sub-14nm nodes is the need for mask process corrections (MPC). A solution for Curvilinear MPC (CLMPC) is demonstrated and discussed in this paper along with various options for the mask data preparation flows for VSB mask writers and raster based Multi-Beam mask writers. Mask Rule Check (MRC) is identified as a critical step in this data preparation flow for curvilinear shapes, and it is demonstrated that model-based MRC is a viable solution for curvilinear mask shapes.

Machine learning is a powerful computer science technique that can derive knowledge from big data and make predictions/decisions. Since nanometer integrated circuits (IC) and manufacturing have extremely high complexity and gigantic data, there is great opportunity to apply and adapt various machine learning techniques in IC physical design and verification. This paper will first give an introduction to machine learning, and then discuss several applications, including mask/wafer hotspot detection, and machine learning-based optical proximity correction (OPC) and sub-resolution assist feature (SRAF) insertion. We will further discuss some challenges and research directions.

Practical machine learning (ML) techniques are being deployed, at an accelerated pace, in an expanding set of application domains. The newsworthy examples in games strategy, image recognition, automated translation and autonomous driving are only the tip of the iceberg of a massive revolution in industrial manufacturing. Semiconductor IC design and manufacturing are also starting to see a number of ML applications, albeit of limited scope. In this work we present both a novel computational tool for ML of physical design layout styles (constructs, patterns) and also a general technical framework for the implementation of ML solutions across the design to mask to silicon chain. ML applications derive their mathematical foundations from Computational Learning Theory, which establishes “learning” as a computational process. The quantitative characterization of the learnability space and its associated Vapnik-Chervonenkis, (VC) dimension, is therefore a pre-requisite of any meaningful ML application. Various types of geometric constructs in the 3D Euclidian space of physical design layouts provide an ideal learnability domain. Specifically, the entire set of generalized Design Rules, silicon retargeting, Optical proximity Correction (OPC), post-OPC verification (ORC) and mask manufacturing constraints (MRC) can be demonstrated to be in a learnable set. This means that, given a suitable feature extraction model, classifiers systems can be built to perform data analytics and optimization, with a quantifiably higher performance (in terms of speed and scale) than any of the currently used engineering-based heuristics. Additionally layout styles, particularly the ones generated by Place-and-Route (P&R) tools and even manual layout for custom blocks are amenable to automated learning (and subsequent parametric-space optimization). Two complete examples in the Design to Mask flow, for advanced technology node applications will be used to validate the ML methodological framework and to illustrate extendibility to other areas, such as process and fab flow optimization. References [1] “A Theory of the Learnable”, L. Valiant – Communications of the ACM, 27 (1984) [2] “On the Learnability of Boolean Formulae”, M. Kearns et al. - ACM Symposium on Theory of computing (1987) [3] “Classifying learnable geometric concepts with the Vapnik-Chervonenkis dimension”, Blumer, et al. - ACM Symposium on Theory of computing (1986) [4] Optimization of complex high-dimensional layout configurations for IC physical designs using graph search, data analytics, and machine learning, V. Dai, et al. - Proc. SPIE 10148, DPTCO XI, (April 2)

Machine learning based hot spot detection is an emerging area in verification of mask and layout design. In machine learning, feature extraction methods suitable for application domains are as important as learning and inference algorithm itself for detection accuracy. In this paper, several feature extraction methods were proposed and implemented, and compared using a standard bench mark dataset. Preferable characteristics for the good feature extraction will be discussed. Comparison studies indicated that combination of a good feature extraction method and a standard machine learning algorithm often gave excellent results compared with previously reported results.

Sub-Resolution Assist Features (SRAF) are widely used for Process Window (PW) enhancement in computational lithography. Rule-Based SRAF (RB-SRAF) methods work well with simple designs and regular repeated patterns, but require a long development cycle involving Litho, OPC, and design-technology co-optimization (DTCO) engineers. Furthermore, RB-SRAF is heuristics-based and there is no guarantee that SRAF placement is optimal for complex patterns. In contrast, the Model-Based SRAF (MB-SRAF) technique to construct SRAFs using the guidance map is sufficient to provide the required process window for the 32nm node and below. It provides an improved lithography margin for full chip and removes the challenge of developing manually complex rules to assist 2D structures. The machine learning assisted SRAF placement technique developed on the ASML Brion Tachyon platform allows us to push the limits of MB-SRAF even further. A Deep Convolutional Neural Network (DCNN) is trained using a Continuous Transmission Mask (CTM) that is fully optimized by the Tachyon inverse lithography engine. The neural network generated SRAF guidance map is then used to assist full-chip SRAF placement. This is different from the current full-chip MB-SRAF approach which utilizes a guidance map of mask sensitivity to improve the contrast of optical image at the edge of lithography target patterns. We expect that machine learning assisted SRAF placement can achieve a superior process window compared to the MB-SRAF method, with a full-chip affordable runtime significantly faster than inverse lithography. We will describe the current status of machine learning assisted SRAF technique and demonstrate its application on the full chip mask synthesis and how it can extend the computational lithography roadmap.

Lithographical patterning on the surface of a fine pipe with a thin wall is required for fabricating three-dimensional micro-parts. For this reason, a new exposure system was developed for printing patterns on a cylindrical pipe. In the exposure system, the pipe was rotated 360° synchronous to a linear scan of a reticle. Stent-like resist patterns with a mean width of 185 μm were printed on a surface of stainless-steel pipe 2 mm in diameter. Next, the patterned pipe was chemically etched and stent-like meshed pipes with a mean mesh width of 110 μm were fabricated.

Nanoimprint lithography (NIL) is one of the highest potential candidates for next generation lithography in semiconductors. NIL is very useful technology for pattern fabrication in high resolution compared to conventional optical lithography. NIL technology makes use of replication from quartz templates. The cross-sectional profile of the template is directly transferred to the resist profile on a wafer. Accordingly, the management of the cross-sectional profile on the template pattern is much more important than on each photomask. In our previous report, we had studied the performance of measuring cross-sectional profiles using grazing-incidence small-angle X-ray scattering (GISAXS). GISAXS has made it possible to analyze the repeated nanostructure patterns with a 2D X-ray scattering pattern. After various researches, we found the application is very effective in the method of cross-sectional profiling of sub-20 nm half-pitch lines-and-spaces (LS) patterns. In this report, we investigated the capabilities of measuring cross-sectional profiles for hole patterns using GISAXS. Since the pattern density of hole patterns is much lower than that of LS patterns, the intensity of X-ray scattering in hole measurements is much lower. We optimized some measurement conditions to build the hole measurement system. Finally, the results suggested that 3D profile measurement of hole pattern using GISAXS has sufficient performance to manage the cross-sectional profile of template. The measurement system using GISAXS for measuring 3D profiles establishes the cross-sectional profile management essential for the production of high quality quartz hole templates.

Currently, we are supplying defect-free EUV mask for device development. This was one of the biggest challenges in the implementation of EUV lithography for high volume manufacturing (HVM). It became possible to hide all multi-layer defects by using defect avoidance technique through improvement of blank mask defectivity and development of actinic blank inspection tool. In addition, EUV pellicle is also considered as a requisite to guarantee predictable yield. Both development of mask shop tools and preparation of EUV scanner for pellicle are going well. However, still membrane needs to be much improved in terms of transmittance and robustness for HVM. At the conference, EUV mask readiness for HVM will be discussed including blank defect improvement, preparation of actinic tools and pellicle development.

Actinic review of potential defect sites and verification of their repair is a key step in producing defect free masks. The AIMS^TM systems are the industry proven standard for this task and the AIMSTM EUV has been developed to provide this functionality for EUV masks. Thereby it closes an important gap in the EUV mask infrastructure for volume production. In this paper, we show the readiness of the AIMS^TM EUV for defect review and verification, and discuss the use of actinic aerial image metrology beyond this core application. In particular, we show measurements on mask 3D effects and the contribution of photon stochastics on wafer local CDU.

It is generally said that conventional deep ultraviolet inspection tools have difficulty meeting the defect requirement for extreme ultraviolet masks of hp 1X nm. In previous studies, it has been shown that the newly developed optics and systems using deep ultraviolet, named Super Inspection Resolution Improvement method for UnreSolved pattern (SIRIUS), has high sensitivity for nanoimprint lithography templates with unresolved patterns which are the same scale as the wafer. In this paper, the capability of SIRIUS for the extreme ultraviolet mask of hp 1X nm lines and spaces pattern has been studied by evaluating the signal to noise ratio of inspection images and capture rates with 5 runs to the target defects which cause over 10% printed wafer critical dimension errors calculated by simulation. It was demonstrated that the signal to noise ratio was increased and the all target defects became detectable with the throughput of 120 min per 100 × 100 mm² . Additionally, the printability of natural defects detected with SIRIUS was analyzed. It was confirmed that SIRIUS was able to detect natural defects under 10% of wafer critical dimension. In conclusion, we confirm that SIRIUS can be available for the extreme ultraviolet mask inspection of hp 1X nm lines and spaces pattern.

As the Extreme Ultraviolet (EUV) lithography ecosystem is being actively mapped out to enable sub-7nm design rule devices, there is an immediate and imperative need to identify the EUV reticle (mask) inspection methodologies [1]. The introduction of additional particle sources due to the vacuum system and potential growth of haze defects or other film or particle depositions on the reticle, in combination with pellicle uncertainty pose unique inspection challenges when compared to 193i reticles. EUV reticles are typically inspected with optical reticle-inspection tools. However, if there is a pellicle on the EUV mask which is non-transmissive to the optical wavelengths used in the reticle inspection tools, then there is a need for alternative inspection methodologies based on inspection of printed wafers. In addition, due to the potential new defect mechanisms associated with the EUV reticles, fabs are looking for additional methods to re-qualify reticles in production using printed wafer inspections. The printed wafer inspection methodology is referred to as “Reticle Print Verification” or “Reticle Print Check.” This paper discusses these alternative inspection methodologies that are being developed in collaboration with imec using an advanced broadband plasma (BBP) patterned wafer optical inspection (KLA-Tencor 3905) and e-beam review systems (KLA-Tencor eDR7280).

The current industry plan is for EUV Lithography (EUVL) to enter High Volume Manufacturing (HVM) in the 2019/20 timeframe for the 1X nm half-pitch (HP) node (logic and memory). Reticle quality and reticle defects continue to be a top industry risk. The primary reticle defect quality requirement continues to be “no reticle defects causing 10% or larger CD errors on wafer (CDE)”. In 2013, KLA-Tencor reported on inspection of EUV reticles using a 193nm wavelength inspection system1. The report included both die-to-database (db) and die-to-die (dd) inspection modes. Results showed the capability to detect a wide variety of programmed and native reticle defects judged to be critical. We have developed extensions to the 193nm wavelength (193) inspection system for the typical 2019/20 HVM EUV reticle defect requirements. These improvements include innovations in: defect enhancement methods, database modeling, defect detection, and throughput. In this paper, we report on the latest data and results of this work, focusing on EUV reticle dieto- database inspection. Inspection results are shown using typical next generation EUV programmed defect test reticles and typical full field product-like EUV reticles, all from industry sources. Results show significant defect detection improvements versus the prior generation inspection system. We also report the test results of a high throughput die-todatabase inspection mode that could be used for the typical mask shop outgoing inspection of EUV reticles where particles are the primary defect to be detected and there is no pellicle (or the pellicle transmits 193nm wavelength²).

EUV pellicles are needed to support EUV lithography in high volume manufacturing. We demonstrate progress in cap layer design for increased EUV transmission and infrared emission of the Polysilicon-film. In our research lab we obtained EUV transmission of 90% and good emissivity for a fully capped pSi film. We also discuss results on next generation EUV pellicle films. These include metal-silicides and graphite. Next-gen film performance is compared to the current generation pSi film. These films are expected to be stable at higher operating temperature than pSi. Metal-silicides have the advantage of sharing a similar process flow as that of pSi, while graphite shows ultimate high temperature performance at the expense of a more complicated manufacturing flow. Capping layers are needed here as well and capping strategies are discussed for these film generations.

Development of a pellicle membrane to protect the reticle from particles for EUV source powers beyond 250 W is a subject of intensive research and is in great demand to support high volume manufacturing with EUV lithography. Identifying a membrane with high EUV transmission, mechanical integrity, thermal stability and chemical resistance within the scanner environment is extremely challenging; yet these properties are required to realize next-generation EUV pellicle solutions. This paper proposes free-standing carbon nanotube (CNT) film as an alternative next generation core pellicle material. Most of the desired pellicle characteristics can be achieved by tuning the properties of freestanding CNT films. We demonstrate that free-standing CNT films possess very high EUV transmission (up to 99%) and good transmission uniformity (0.4% half range), mechanical stability (maximum deflection ~0.08 mm at 2 Pa), thermal stability (no change under greater than 500 W equivalent EUV exposure in vacuum without hydrogen radicals) and scalability to a full pellicle size. Other important CNT membrane properties are presented and are favourable for the pellicle application: low EUV scattering, low EUV reflectivity and high transmission under DUV. The ability of the CNT film to stop particles is analysed. The only known failure of the CNT membrane is instability to hydrogen radical/ion environment within the current reticle chamber of the scanner. If changing that environment to limit hydrogen radicals near the pellicle surface is not an option, there is a need to coat the CNT structures for protection. The challenges and considerations for coating the free-standing CNT membranes are discussed.

In the existing DUV pellicle, haze generation risk on mask surface during DUV exposure exists due to the reaction of out gas in an exposure atmosphere. It is well known fact that outgas is generated not only from pellicle in itself but also by stray light being irradiated adhesive parts. As for EUV pellicle, problems of the exposure defect such as haze generation and reflectance reduction of mask will be anticipated because EUV has higher photon energy compared with DUV and diffusion of the outgas is promoted in high vacuum condition. In this study, similar to the pelliclized EUV mask structure was constructed by using the full-size EUV pellicle frame stacked on a base plate which has similar component of the EUV mask surface, and dummy plate placed on the membrane side of the frame. Contamination growth behavior was examined by irradiating the EUV light to the base plate inside pellicle via EUV transparent membrane on dummy plate. Adhesion of the contamination on base plate was observed in EUV irradiation area in the case of the pellicle sample using commercially available adhesive as the mask adhesive. So, general commercially available adhesives will not be suitable for mask adhesive of pellicle. We found that generation of the contamination was not observed for pellicle sample with coated adhesive materials as the mask adhesive, which has both outgas suppressing and EUV light screening function. Coated adhesives for mask adhesive of pellicle, which keep the adhesive properties, will be suitable for fixing method to suppress the contamination growth during EUV exposure.

Pellicles are an important part of the IC-manufacturing supply chain, keeping particles away from the imaging plane of the photomask to preserve wafer yield. EUV lithography poses new challenges on the pellicle membrane because the radiation must pass twice due to the reflective mask. Additionally, there are no transparent materials for EUV so the EUV pellicle must be extremely thin to keep the transmission high. Present continuous-membrane pellicle solutions will not be sufficient for source powers greater than 250 W that are anticipated for HVM EUV lithography. A possible approach to maintain strength and high transmittance is to use nano-structured materials. We report here on the EUV optical characterization of a variety of alternative membrane materials. The fine structure of etched holes or membranes made of carbon nano-tubes introduces interesting optical effects. We, therefore, not only address specular reflectance or transmittance by the optical characterization but also investigate off-specular diffuse scatter. We compare the respective optical properties of homogeneous reference membranes with etched membranes and carbon nano-tubes. Particularly the latter show a very high EUV transmittance of more than 95 % and are therefore considered being a highly promising candidate for alternative EUV pellicles.

Pellicles that satisfy transmission, emission, thermal, and mechanical requirements are highly desired for EUV high volume manufacturing. We present here the capability of integrating pellicles in the full flow of rigorous EUV lithography simulations. This platform allows us to investigate new coherence effects in EUV lithography when pellicle is used. Critical dimension uniformity and throughput loss due to pellicle defects and add-on particles are also analyzed. Our study provides theoretical insights into pellicle development and facilitates pellicle insertion in EUV lithography.

The detection of problematic low-fidelity lithographic design patterns in the physical verification phase is considered to be one of the greatest challenges and important techniques nowadays in the manufacturing process. There are lots of contributions to detect the lithographic hotspots, which mostly rely on using machine learning (ML) and/or pattern matching (PM) approaches. The fuzzy PM was presented due to the limitations in ML approach, where inappropriate layout feature representation impacts the number of false alarms, and the PM approach, which lacks prediction or identifying two similar patterns. However, the tricky step in fuzzy PM techniques is to define a similarity measurement between two patterns. This paper proposes a new feature representation for fuzzy matching for lithography hotspot detection. The technique enhances the modified-transitive-closure-graph (MTCG) by adding specific do-not-care (DC) regions to filter out unwanted polygons. This technique is capable of reaching 88% success rates, by 10% increase in success rates compared to the conventional MTCG, with no impact on total run-time. Building on the uniqueness of MTCGs for any tiled pattern, a new similaritydetection technique is also introduced that detects hotspots of similar shapes with acceptable defined tolerance. The proposed technique, besides MTCG, is able to reach 97.044% success rate with only 1.0287% increase in total run-time.

Sub-Resolution Assist Features (SRAF) are a widely used Resolution Enhancement Technique (RET) used in Optical Lithography. They are used to enhance the printability of the main features. Model Based SRAF (MBSRAF) are now the state of art method for placing SRAF, where numerical simulation is used to predict the optimal SRAF size and location. When a slight change in the environment occurs, very small numerical differences may result, and in some cases for very complex structures, the numerical technique may drive to a different solution, resulting in SRAF solution inconsistency. In addition following the initial placement by MB-SRAF, SRAF Print Avoidance (SPA) models are utilized to modify the SRAF size and placement, to prevent the SRAF printing. This step may change the SRAF solution and consequently cause inconsistency. In this work, a case of SRAF inconsistency is shown and an alternative solution will be presented.

With several foundries/IDMs committed to using EUV to manufacture devices at the 7 nm and 5 nm nodes, the success of EUVL will depend critically on the ability of manufacturers to meet extremely tight edge placement error (EPE) budgets. EPE is affected by many factors and it becomes important to identify and address all systematic sources of edge placement error. One major source of this error, which hasn’t been given a lot of attention, continues to be the magnitude and variation of aberrations across the exposure field and between different scanners. EUV scanners are known to have significantly higher level of aberrations than DUV scanners due to the substantial drop in wavelength requiring tighter specifications on lens roughness, as well as a move to reflective optics producing double pass impact of surface roughness.

While the EPE from variation in aberrations across the exposure field is correctable in OPC software, there are no known ways to address tool-to-tool aberration variation. Given that foundries are expected to have multiple EUV tools for high volume manufacturing, the degree of tool-matching between different machines is expected to play a critical role to the success of EUV. This work seeks to further the study by quantifying the simulated edge placement error on realistic 7 nm / 5 nm node designs resulting from a fleet consisting of multiple EUV tools, under the assumption of single OPC model / mask for multiple tools and whether such assumptions are valid. Given the importance of tool-to-tool aberration matching in EUVL, this study investigates the amount of variation in tool-to-tool aberration that can be tolerated before foundries must consider tool dedicated OPC mask sets. This study statistically analyzes different metrics such as EPEs, image shifts and worst case excursions to understand which single tool in the fleet should be best used in model calibration to generate the OPC mask shapes. In addition, an effort to rank relative quality of the verification solutions is investigated, to be used to tool allocation.

A new technology transforms mask inspection images through focus into 3D lithography images in resist. This enables early detection and ranking of hotspots, and distinguishes mask-induced and process-induced hotspots. The results can be used in several ways including: 1) feed back to OPC teams to improve process window; 2) feed forward to the litho team for scanner adjustment; and, 3) feed forward to wafer inspection in the form of care areas to reduce time to result for wafer-based process window discovery.

Mask writers have evolved significantly in the last decade, and many modern ones include some level of process error correction. However, the feature sizes were shrinking at even faster rate, so the ratio of error to feature size has grown to a level that can no longer be ignored. Even “ideal” process will still produce some rounded contours on the mask. This paper discusses potential applications for the mask contour approximation, such as manufacturing rule check, inspection, metrology and mask error correction. We also discuss and compare possible approaches to generate the mask contours.

CDSEM metrology is a powerful tool to obtain silicon data. However, as our technology nodes advance shrink to 14nm and below, the CD measurement data from CDSEM can hardly provide sufficient information for OPC verification (OPCV) and the related silicon verification. On the other hand, the abundant information from CDSEM images has not been fully utilized to assist our data analysis. In this context, contour extraction emerges as the best method to obtain extensive information from CDSEM images, especially for 2D structures. This paper demonstrates that contour extraction bridges the gap between the needs of 2D characterization and the limited capability of CDSEM measurement. The extracted contour enables automatic identification of litho-hotspots using OPCV tools, especially for non-CD related hotspots. Statistical silicon data extraction and analysis on complex geometries is viable with extracted contours. The silicon data can then be feedback to the evolution of non-CD OPCV checks, where simple CD measurement is inadequate. Effective CD can also be calculated from the obtained 2D information, with which Bossung curves can be built and provide complementary information.

To address the increasing requirements of the semiconductor industry for accurate measurement of small features, Critical Dimensions (CD) Grazing-Incidence Small-Angle X-ray Scattering (GISAXS) is being considered. GISAXS offers fast, surface sensitive measurements from which relevant structural parameters can be reconstructed. However, an essential limitation for the practical application is the large measurement spot size resulting from the shallow incidence angle. Here we show that despite a large spot size, GISAXS measurements of small targets are possible if the targets are designed such that the scattering from the targets is separable from the scattering of other structures in the measurement spot. For grating targets, in particular rotation of the targets in the sample plane such that the grating lines are not parallel to the predominant direction of the surroundings allows reliable measurement of the target scattering irrespective of the X-ray beam size. We discuss the effect of X-ray source, rotation angle, target size and grating pitch on the minimum measurement times and number of measurable grating diffraction orders and conclude that a single 50 μm × 50 μm area grating target can be measured with high-end laboratory sources in tens of seconds if it is rotated by at least 0.2°. For smaller targets, significantly longer measurement times and larger rotations are necessary.

After the introduction of multi-patterning techniques like multiple Litho-Etch (LEⁿ ) steps and/or Spacer Assisted Double/Quadruple Patterning (SADP/SAQP), the amount of masks required to produce a semiconductor device has increased significantly. The main reason was that a functional layer could no longer be exposed in one single litho step due to the elevated pitch requirements. Consequently, the required pattern had to be split-up and divided over multiple masks. One can imagine that this has put a huge constraint on the mask-to-mask on-product overlay requirements and control. It was already shown before that for the LE² use-case the mask-to-mask contribution is the second largest contributor (after the scanner) to the overall on-product overlay. In order to keep the on-product overlay within specification over time, the number of on-wafer overlay metrology steps inside the fab increased even more. Since more masks are used per layer, multiple combinations are now possible to measure and control both the intra-layer as well as the inter-layer overlay. As a consequence, the increasing number of metrology steps has resulted in a negative impact on the overall wafer/lot cycle time in the fab. It would be beneficial to fully characterize the mask-to-mask overlay off-line and apply computational overlay techniques to compute the on-wafer overlay. This enables smart metrology sampling to address and reduce the overall wafer/lot cycle time inside the fab. In this work, we performed a correlation study between off-line mask-to-mask registration metrology and on-wafer measurements. The off-line overlay measurements were performed on a PROVE® tool while the exposures and scanner readouts were executed on an ASML TWINSCAN™. Two ASML qualification (BaseLiner) masks were used for this purpose. Extensive off-line registration measurements were performed on both reticles including the reticle alignment marks as well as the image field metrology features (gratings). We show an excellent correlation between the measurements on the PROVE® tool and the on-wafer results reaching R² < 0.96 with an accuracy of 0.58-nm. The accuracy is determined by the reticle alignment accuracy on the scanner and the quality of the masks. We have identified the underlying contributors to the error budget to enable a further improvement of the correlation between the mask-tomask and the on-wafer overlay. Since the results of this first investigation were so promising, the effect of a pellicle mounted on one of the masks was studied as well. The off-line mask-to-mask registration metrology was repeated and the resulting computational overlay has been compared with the on-wafer results.

A critical challenge in optical critical dimension metrology, that requires high measurement sensitivity as well as high throughput, is the dimensional measurements of features sized below the optical resolution limit. This paper investigates the relationships among dimensional sensitivity and key illumination beam conditions (e.g., angular illumination, partial coherence) for photomask feature characterization. Scatterfield images at the edge areas of multiple line structures on a Molybdenum Silicide (MoSi) photomask are analyzed to establish sensitivity to dimensional changes. Actinic scatterfield imaging experiments for these features are performed using the NIST 193 nm Scatterfield Microscope, designed to enable engineered illumination beams at the target. Illumination configurations that improve sensitivity are identified from imaging edges of multiple line targets having linewidths and spaces of about 1/3 wavelength.

The ongoing trend to smaller structures and an increasing number of high MEEF patterns in mask design makes defect disposition and repair verification more critical than ever. For AIMS™ as the standard method for defect disposition and repair verification, the requirements are getting tighter. Additionally, the efforts required for defect analysis are steadily increasing. As a result, mask manufacturers are forced to continually find methods to increase productivity and optimize the cost of defect disposition.

Smart solutions for automated defect treatment together with a high degree of tool integration play an increasing role in this challenge. With AIMS™ AutoAnalysis, which provides fully automated analysis capability of AIMS™ aerial images, ZEISS addresses this challenge. Due to direct connection and communication of AutoAnalysis with the AIMS™ system via the FAVOR® platform, the image analysis process runs in parallel to the measurement process. A high degree of automation reduces the influence of human error and provides highly reliable results.

In the following paper a study is presented demonstrating the benefits of the implementation of AutoAnalysis in the production environment at Photronics, Inc. The study was carried out by analyzing defects on pattern sets, varying from simple to very complex patterns. Furthermore, the analysis capabilities of AutoAnalysis have been compared with the capability of operators and engineers.

The performance of AutoAnalysis is presented showing significant time saving in the defect disposition process as well as an overall increase in reliability of analysis results.

Megasonic agitation continues to be used in advanced 193i and EUV photomask cleaning processes. The trend to adopt higher frequencies is driven by the need to control a tighter process window with shrinking feature sizes and a zerotolerance defect requirement. Despite continued use of megasonics, the effect of the acoustic field applied to the mask substrate remains unclear. Photomask cleaning is a dynamic process with many parameters that contribute to the particle removal efficiency and pattern damage. These include transducer type, transducer position, drive frequency, power setting, flow rate, chemistry, gas concentration, etc. To add to the complexity, when the acoustic waves from the transducer interact with a quartz mask the energy may reflect from, transmit through, or couple into the substrate. An in-situ measurement of the acoustic field, as present at the feature location, is required to correlate acoustic parameters with cleaning performance. This work introduces a photomask-shaped cavitation sensor capable of measuring the absolute pressure from the direct field, stable cavitation, and transient cavitation present at the surface. In contrast to previous work characterizing skirt-type transducers, this measurement instrument is sensitive to higher drive frequencies while withstanding concentrated pressure levels from nozzle transducers. Here, a megasonic system with dual nozzle transducers at 5 MHz and 3 MHz was evaluated. The aim of the study is to better understand the acoustic properties from different types of transducers for process development and monitoring in the quest to correlate with photomask cleaning.

The current Cr etch solutions will need to be improved to keep up with market demand for smaller features and reticle resolution while the industry awaits the maturity of EUV technology, and based on the current roadmap, there is an urgency to improve the Cr reticle pattern resolution capability today. That resolution capability comes in the form of writing smaller features on a photomask, but as the Cr-to-photoresist (PR) ratio increases beyond three to one, there is a negative impact on the integrity of the PR, resulting in costly product scrap. Thinner PR layers are required to avoid such scrap, since the Cr layer is fixed. This necessitates lower consumption of the PR during the etch process, and that translates to higher etch selectivity of Cr to PR. This manuscript covers the ideas selected to address reduction in PR loss, the experiments around a few of those ideas, and the results of those experiments. Our experimental set shows that a <25% increase in selectivity and a 40-50% reduction in over-etch can be achieved through increased ion/neutral control during the etch process. This, combined with resist pretreatments or other Cr etch modifications, could prove to be a solution in the interim, but while the initial results are promising, further investigation is needed on production nodes to realize the full impact of this achievement.

Despite recently receiving a large amount of global publicity, smart automation is yet to be fully implemented in production for many areas, including mask making for semiconductors. One specific area that can significantly benefit from smart automation is the back end of line (BEOL) in mask manufacturing where the implementation of data driven decision making and predictive analytics can completely revolutionize our current way of working. Apart from any hardware aspect, software must adapt to the current needs of connectivity which demand the ability to handle large amounts of data, have sufficient computational resources and execute tool-to-tool communication. These requirements call for flexible and expandable software applications that increase the productivity and efficiency of backend processes. Additionally, by incorporating automated systems, businesses benefit from the reduction or elimination of losses due to human error. Given the number of human interactions within each step of the standard BEOL, such as inspection, cleaning, disposition/review and repair, mask shops run a high risk of a mishap occurring. Even by extensive measures such errors can only be reduced but not completely avoided as their origin lies in the way of how humans act. The consequences can range from harmless slip-ups up to severe manufacturing impacts which finally can lead to an economic loss. These risk levels become further multiplied as both product and workflow become more complex due to the possible repetitive cycles in the repair steps. These losses can be mitigated by the use of smart automated solutions that deliver a reduction in turnaround time (TAT) and overhead. More efficient use of operator expertise and cost reductions in data handling will improve mask shops’ productivity. Another issue that intelligent automation brings is efficient tool management. In a high volume manufacturing environment it can be challenging to maintain active monitoring of tools. Consequently, idle times and bottlenecks prevent mask shops from achieving their highest potential in terms of cycle time and reliability in delivering products on time. Having the possibility to monitor the tool clusters enables efficient delegation of operations and facilitates the optimization of workflows. The proposed model in this paper investigates the effects of defectivity complexity on the TAT in a mask shop. The inclusion of intelligent application solutions effectively address human error, bottlenecks and defect complexity reducing both TAT and TAT variability. Smart automation coupled with real time monitoring and decision making solutions help control the BEOL in a predictive manner. Therefore optimization of the BEOL workflow through intelligent automation leads to a mask production with higher reliability and higher market value.

Multi-beam mask writer MBM-1000 is developed for N5. It is designed to accomplish higher throughput than a singlebeam VSB writer EBM-9500 at shot count higher than 500 G/pass, and write masks with low sensitivity resist to have better CDU and patterning resolution. Product version of blanking aperture array (BAA) for MBM-1000 is fabricated along with data transfer system to accomplish data rate of 300 Gbps. They have been integrated with writing control software based on MBF format, a tool-specific format which handles any-angle pattern and polygon patterns. Writing test without re-adjustment of beam current showed that exposure time control by BAA blanking is very stable, and linear CD drift is less than 0.1 nm for 10 hours. Complex OPC pattern and ring pattern were printed on low-sensitivity pCAR resist and showed good resolution to resolve 25 nm isolated line.

Nanoimprint lithography manufacturing utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Throughputs of 80 wph have been demonstrated, and mix and match overlay of 3.7nm 3 sigma has been achieved. The technology has already been successfully applied as a demonstration to the fabrication of advanced NAND Flash memory devices. A similar approach can also be applied however to remove topography on an existing wafer, thereby creating a planar surface on which to pattern. In this paper, a novel adaptive planarization process is presented that addresses the problems associated with planarization of varying pattern densities, even in the presence of pre-existing substrate topography. The process is called Inkjet-enabled Adaptive Planarization (IAP). The IAP process uses an inverse optimization scheme, built around a validated fluid mechanics-based forward model that takes the pre-existing substrate topography and pattern layout as inputs. It then generates an inkjet drop pattern with a material distribution that is correlated with the desired planarization film profile. This allows a contiguous film to be formed with the desired thickness variation to cater to the topography and any parasitic signatures caused by the pattern layout. In this work, it was demonstrated that planarization efficiencies of up to 99.5% could be achieved, thereby reducing an initial ~100nm wafer topography down to as little as 0.6nm.

Nanoimprint lithography manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of widediameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. In this paper, we review the advancements in both wafer imprinting and mask replication systems. To address high volume manufacturing concerns, an FPA-1200 NZ2C four station cluster tool is used in order to meet throughput and cost of ownership requirements (CoO). The status of the tool overlay is discussed. Application of a High Order Distortion Correction system to the existing magnification actuator has enabled correction of high order distortion terms up to K20. Because mask replication is required for nanoimprint lithography, improvements to the FPA-1100 NR2 mask replication system are reviewed. Criteria that are crucial to the success of a replication platform include both particle control and image placement (IP) accuracy. Data is presented on both of these subjects. Particle adders were studied over a nine month period. Additionally, with respect to image placement, an IP accuracy (after removing correctables) of 1.0nm in X, 1.1nm in Y has been demonstrated.

The current industry plan is for EUV Lithography (EUVL) to enter High Volume Manufacturing (HVM) in the 2019/20 timeframe at about the 16nm half-pitch node (16hp). Reticle quality and reticle defects continue to be a top industry risk. The primary reticle defect quality requirement continues to be defined as “no reticle defects causing 10% or larger CD errors on wafer”. Traditionally, mask shops and mask blank manufacturers have been using bright field confocal technology to perform mask blank qualification. However, due to more stringent defect requirements for EUV blank defects, and the difficulty in detecting and repairing any mask defects caused by a blank defect, the industry requires a new approach to detect defects to support 16 nm hp EUV manufacturing. To meet these emerging requirements, we have developed a new dark field imaging system for photomask blank inspection. This system can be used in the blank manufacturing process to inspect the quartz blank, to inspect after film deposition, and to inspect the finished blank after resist coating. In the mask shop, the same system can be used to inspect an uncoated blank prior to resist coating, or to perform incoming inspection on a finished blank, prior to writing. In this paper, we report on the initial results from this new system on a range of programmed defect blanks as well as production photomask blanks. Inspection results will be shown on a variety of substrates, both for EUV blanks as well as optical blanks.

Fine cylindrical micro-components such as stents and micro-needles are required. Here, laser-scan lithography and electrolytic etching were investigated for opening many slits on fine stainless-steel pipes with an outer diameter of 100 μm, a thickness of 20 μm and a length of 40 mm.

At first, a pipe coated with a positive resist was exposed to a beam spot of violet laser. Linearly arrayed 22 slit patterns were continuously delineated by scanning and intermittently moving the pipe in the axial direction. The same delineations of 22 slit patterns were repeated four times in every 90-degree circumferential direction. The pipe was exposed to the laser spot in lengths of 170 μm, and interval lengths of 100 μm were located between the exposed lengths. Thus, 88 slit patterns in total were delineated on 8 pipe surfaces.

Next, the pipes masked by the resist were electrolytically etched one by one. A pipe was used as an anode, and an aluminum cylinder was set as a cathode around the pipe. As the electrolyte, aqueous solution of NaNO₃ and NH₄Cl was used. Then, the resist was removed by ultrasonic cleaning in acetone. Sizes of etched 22 slits in a line were measured for each pipe using SEM (JEOL, JSM-5510). The average width and length measured at inner surfaces were 25.8 μm (σ=4.7) and 174.8 μm (σ=13.4), respectively. The width and length measured at the outer surface were 54.6 μm (σ=2.6) and 211.4 μm (σ=4.2), respectively. It was demonstrated that aimed mesh structures were successfully fabricated. Keywords: laser-scan lithography, ultra-fine pipe, slit-pattern, electrolytic etching, stent, micro-needle

Sub-Resolution Assist Feature (SRAF) printing detection is critical during SRAF model building. Currently, SRAF printing detection on silicon wafer is mainly through human judgement on CDSEM images, which is inefficient and error prone. Therefore, a robust automatic SRAF printing classification mechanism is essential to improve detection accuracy and efficiency. This paper presents a method of classifying SRAF printing based on a database-independent contour extraction algorithm. By size calculation on extracted contour SRAF feature printing classification can be made automatically. This flow has been demonstrated to be able to correctly classify SRAF printing with consistent performance thus avoid the subjectivity and inconsistency in human judgement.

The paper aims to propose a systematic methodology and the relevant strategies during data preparation to reduce catastrophic failures at 7nm or smaller technology nodes when calibrating optical proximity correction (OPC) models. The common loop and the work flow to build up an OPC empirical model is reviewed first. The strategies to discuss are focusing on the steps of data collection and data preparation. Pattern sampling selection is not a part of the discussions in this paper. The primary metrology technology to accomplish data collection for OPC model calibration is Critical Dimension (CD) Scanning Electron Microscope (SEM). Collected data set is reported as a combination of CD values at various heights of side wall of the measured features and the corresponding top-view images. A challenging mission at the data preparation step is to establish a systemtic methodology with a set of reliable filtering criteria and an algorithm that can perform the data qualification check effectively and automatically. The major concepts and terms proposed from the criteria are based on data analysis on the achievable information from CD SEM and the validity of the methodology is proven from mathematical perspective as well, which is targeted on obtaining additional insights of patterns before a standard or customized OPC model creation. The paper is summarized with conclusions.

Lithography process variation as well as etch and topography have always been a stubborn challenge for advanced technology nodes, i.e. 14nm and beyond. This variability usually results in defects aggregating around the edge of the wafer and leading to yield loss. A very tight process control is the logical resolution for such issues, nevertheless it might not be possible, or it may slow down the whole design to silicon cycle time. Another degree of difficulty is detecting these defects in ORC and concluding an OPC fix. In this paper, we show that aerial image ORC checks could provide a very useful insight to these defects ahead of time, and that they correlate well with silicon defects highlighted by CFM scan. This early detection upstream enables us to conclude a generic OPC fix for such issues and also improves the total OPC process-window enhancement and eliminates these defects on silicon.

One of the major challenges for process control is wafer to wafer and lot to lot variation, for the 14nm technology node and beyond. Most of advanced process control (APC) is based on product groups, and different product groups exhibit different amounts of parameter tuning. Because lithography pattern density varies between product groups, it is difficult or impossible to share APC threads between different product groups. This paper will introduce a new method to optimize current APC into a dynamic control. With dynamic control, product groups having different pattern density will have a similar amount of parameter tuning and all product groups could share APC feedback. This paper also shows the simulation results and predicts CD sigma with dynamic control.

Below the 28nm node the difficulty of using subresolution assist features (SrAFs) in OPC/RET schemes increases substantially with each new device node. This increase in difficulty is due to the need for tighter process window control for smaller target patterns, the increased risk of SrAF printing , and also the increased difficulty of SrAF mask manufacture and inspection. Therefore, there is a substantially increased risk of SrAFs which violate one or more manufacturability limits. In this paper, we present results of our work to evaluate methods to pre-characterize designs which are likely to become problematic for SrAF placement. We do this by evaluating different machine learning methods, inputs and functions.

Greyscale lithography is a way to fabricate 3D microstructures in the fields of micro-electro-mechanical systems (MEMS) and micro-optics. We use direct laser writing (DLW) to create a layered staircase sample for bio-microscopy use. To minimize the number of experiments necessary to determine the laser system parameters necessary to have the specified structure we used Design of Experiment (DOE) together with a 3D profiler using scanning white light interferometry (SWLI). A gray-scale mask with varying intensities was developed and used to pattern a thick positive tone photoresist. We employed a Microtech LW405 laser writer with a 405 nm GaN laser. Our results show the potential of the SWLI-DOE approach as a tool to optimize (precision, speed and structure) greyscale DLW lithography for the herein reported use. This work is a step towards replacing slow SEM and AFM devices for quality control in 3D MEMS production.

In order to reduce the fabrication time of the diffractive optical elements (DOEs), a new process is proposed by combining the laser ablation phenomenon using the laser intensity in the conventional thermochemical process. The basic mechanism of the proposed method and experimental results are also presented. We confirmed the effect of reducing the movement distance of the stage for the production of the overall lithography when we made repetitive square patterns. The time reduction rate is drastically improved when the number of patterns is increased. Various patterns including rectangular, triangular, parallelogram, and diamond shape were fabricated by using the proposed method.

In order to improve on-product-overlay, the image placement performance of a photomask can be corrected and improved through a multiphoton absorption process. This is possible with an ultra-short pulse laser focused into the glass substrate of the mask, from its backside. For optical masks, this is a well-established technology by using the RegC system from ZEISS. Applying this technology to EUV mask requires a backside transparent coating, still electrically conductive for chucking (according to SEMI SPEC). Using nanometers thick Cr and Ni, their oxide and nitride forms, in different stoichiometric forms if need be, we have developed a backside coating with the required optical transmission, sheet conductance, and mechanical durability, and demonstrated femtosecond correction through it. The proposed backside transparent coating designs can be extended to other metals, such as Ti, Ta, Mo and compounds, such as carbides and borides.

With continuous shrinking technology nodes, the error tolerances for mask CD (critical dimension) becomes tighter and tighter since mask errors are passed on downstream and might even be amplified at wafer level. Therefore, high accuracy MPC (Mask Process Correction) models are imperative. Besides the mask model, the MPC algorithm for the input layout also has a critical influence on mask quality. This paper studies and compares two methods of MPC correction: a new method, introducing a correction algorithm based on the CD-SEM box is compared to the standard method that measures EPE (edge placement error) only at the center of an edge. Under which condition the EPE measurement method for MPC correction by the CD-SEM box method should be applied is discussed and its influence on the correction accuracy of small CD patterns is demonstrated.

To deliver a defect-free photomask, is an essential step of mask manufacturing. EB (Electron-beam) repair is widely applied to deal with defects on photomasks, and has to cover etch and deposition capabilities without any pattern damage. However, mask repair is facing more challenges, with the shrinkage of minimum feature resolution for advanced technology nodes. Especially for micro defects at the edge of wafer printability specifications, differences between defect and reference may be tiny and hard to distinguish in visual or by existing methods on repair tools, so that it was difficult to start.

In this paper, a new approach named Contour-based 2D Metrology will be introduced as assistance for the repair processes of such challenging micro defects. Both CDSEM images of defect and reference are input for extracting; then contour-based patterns are overlapped for each other and compared with GDS as well, to describe quantitative differences for each micro area. Assisted with such rigorous and comprehensive data analysis, micro defects can be accurately positioned according to Aims Results and repair processes would be proceeding.