This PDF file contains the front matter associated with SPIE Proceedings Volume PMJ17, including the Title Page, Copyright information, Table of Contents, and Conference Committee listing.

The production of high-resolution flat panel displays (FPDs) for mobile phones today requires the use of high-quality large-size photomasks (LSPMs). Organic light emitting diode (OLED) displays use several transistors on each pixel for precise current control and, as such, the mask patterns for OLED displays are denser and finer than the patterns for the previous generation displays throughout the entire mask surface. It is therefore strongly demanded that mask patterns be produced with high fidelity and free of defect. To enable the production of a high quality LSPM in a short lead time, the manufacturers need a high-sensitivity high-speed mask blank inspection system that meets the requirement of advanced LSPMs. Lasertec has developed a large-size blank inspection system called LBIS, which achieves high sensitivity based on a laser-scattering technique. LBIS employs a high power laser as its inspection light source. LBIS’s delivery optics, including a scanner and F-Theta scan lens, focus the light from the source linearly on the surface of the blank. Its specially-designed optics collect the light scattered by particles and defects generated during the manufacturing process, such as scratches, on the surface and guide it to photo multiplier tubes (PMTs) with high efficiency. Multiple PMTs are used on LBIS for the stable detection of scattered light, which may be distributed at various angles due to irregular shapes of defects. LBIS captures 0.3mμ PSL at a detection rate of over 99.5% with uniform sensitivity. Its inspection time is 20 minutes for a G8 blank and 35 minutes for G10. The differential interference contrast (DIC) microscope on the inspection head of LBIS captures high-contrast review images after inspection. The images are classified automatically.

The miniaturization technology of the FPD panel have been advanced continuously, and it is said that the reducing rate is about 0.7 times for three years. Therefore, an exposure equipment of the 1.5 μm resolution was released from manufacturers in 2016. As one of some methods to realize 1.5 μm resolution, change from the broadband light to i-line single wavelength light has been selected. However, it is known that CD uniformity is become large, when a conventional pellicle is used in i-line single wavelength exposure[1]. Therefore, it is needed products suitable for i-line single wavelength exposure. In this paper, influence of the pellicle is investigated between conventional pellicle and i-line pellicle. Keywords：FPD, pellicle, i-line, resolution, CD uniformity.

Recently, due to increases in the definition of high function panels for mobile devices such as smartphones and tablets, LCD panel TFT and OLED (organic electro luminescence display) circuits are becoming increasingly denser and more miniaturized by the year. TFT and OLED circuits are composed of several layers, such as gate, semiconductor and contact hole (C / H). It is particularly difficult to obtain a stable resolution for C/H due to the decrease in the C/H process margin (EL, DOF, MEEF) as a result of increases in the density of the circuit. Moreover, C/H productivity has also markedly decreased due to an increase in the exposure dose. In response to this, attenuated phase shift mask (Att. PSM) for large size photomasks have been proposed as a means to improve the process margin in FPD. We have developed new PSM that can further improve the process margin and the productivity of C/H via the effective positioning of a high transmittance phase shift film. Using a 1.5um sized hole as the target, we confirmed the improvement effect of the optimized PSM via a software simulation and an exposure test. Hereafter it is necessary for us to optimize the new PSM for each panel process so as to allow us to use this mask in actual processes.

Recently, high-resolution exposure machine has been developed for production of high-definition (HD) panels, and higher-flat photomask substrates for FPD is being expected for panel makers to produce HD panels. In this presentation, we introduce about Shin-Etsu’s advanced technique of producing super-high-flat photomask substrates. Shin-Etsu has developed surface polishing and planarization technology with No.1-quality-IC photomask substrates. Our most advanced IC photomask substrates have gained the highest estimation and appreciation from our customers because of their surface quality (non-defect surface without sub-0.1um size defects) and ultimate flatness (sub-0.1um order having achieved). By scaling up those IC photomask substrate technologies and developing unique large-size processing technologies, we have achieved creating high-flat large substrates, even G10-photomask size as well as regular G6-G8 photomask size. The core technology is that the surface shape of the substrate is completely controlled by the unique method. For example, we can regularly produce a substrate with its flatness of triple 5ums; front side flatness, back side flatness and total thickness variation are all less than 5μm. Furthermore, we are able to supply a substrate with its flatness of triple 3ums for G6-photomask size advanced grade, believed to be needed in near future.

Two types of processors exist in the market. One is the conventional CPU and the other is Graphic Processor Unit (GPU). Typical CPU is composed of 1 to 8 cores while GPU has thousands of cores. CPU is good for sequential processing, while GPU is good to accelerate software with heavy parallel executions. GPU was initially dedicated for 3D graphics. However from 2006, when GPU started to apply general-purpose cores, it was noticed that this architecture can be used as a general purpose massive-parallel processor. NVIDIA developed a software framework Compute Unified Device Architecture (CUDA) that make it possible to easily program the GPU for these application. With CUDA, GPU started to be used in workstations and supercomputers widely. Recently two key technologies are highlighted in the industry. The Artificial Intelligence (AI) and Autonomous Driving Cars. AI requires a massive parallel operation to train many-layers of neural networks. With CPU alone, it was impossible to finish the training in a practical time. The latest multi-GPU system with P100 makes it possible to finish the training in a few hours. For the autonomous driving cars, TOPS class of performance is required to implement perception, localization, path planning processing and again SoC with integrated GPU will play a key role there. In this paper, the evolution of the GPU which is one of the biggest commercial devices requiring state-of-the-art fabrication technology will be introduced. Also overview of the GPU demanding key application like the ones described above will be introduced.

Inverse Lithography Technology (ILT) is becoming the choice for Optical Proximity Correction (OPC) of advanced technology nodes in IC design and production. Multi-beam mask writers promise significant mask writing time reduction for complex ILT style masks. Before multi-beam mask writers become the main stream working tools in mask production, VSB writers will continue to be the tool of choice to write both curvilinear ILT and Manhattanized ILT masks. To enable VSB mask writers for complex ILT style masks, model-based mask process correction (MB-MPC) is required to do the following: 1). Make reasonable corrections for complex edges for those features that exhibit relatively large deviations from both curvilinear ILT and Manhattanized ILT designs. 2). Control and manage both Edge Placement Errors (EPE) and shot count. 3. Assist in easing the migration to future multi-beam mask writer and serve as an effective backup solution during the transition. In this paper, a solution meeting all those requirements, MB-MPC with GPU acceleration, will be presented. One model calibration per process allows accurate correction regardless of the target mask writer.

For some years it has been known that the presence of a multi-layer stack creates an enhanced back-scatter effect at the 1μm length scale. Several authors have reported a non-Gaussian behavior – exponential or worse – that is challenging to both simulate and correct for in a production environment due to the long interaction area of the effect. With the onset of extreme ultra-violet (EUV) lithography, and the likely use in the new multi-beam mask writers, we revisit the EUV midrange effect from first principles, identify the impact from the new mask writers, and demonstrate a production-ready system to characterize and correct for the effect.

For IC design starts below the 20nm technology node, the assist features on photomasks shrink well below 60nm and the printed patterns of those features on masks written by VSB eBeam writers start to show a large deviation from the mask designs. Traditional geometry-based fracturing starts to show large errors for those small features. As a result, other mask data preparation (MDP) methods have become available and adopted, such as rule-based Mask Process Correction (MPC), model-based MPC and eventually model-based MDP.

The new MDP methods may place shot edges slightly differently from target to compensate for mask process effects, so that the final patterns on a mask are much closer to the design (which can be viewed as the ideal mask), especially for those assist features. Such an alteration generally produces better masks that are closer to the intended mask design. Traditional XOR-based MDP verification cannot detect problems caused by eBeam effects. Much like model-based OPC verification which became a necessity for OPC a decade ago, we see the same trend in MDP today.

Simulation-based MDP verification solution requires a GPU-accelerated computational geometry engine with simulation capabilities. To have a meaningful simulation-based mask check, a good mask process model is needed. The TrueModel® system is a field tested physical mask model developed by D2S. The GPU-accelerated D2S Computational Design Platform (CDP) is used to run simulation-based mask check, as well as model-based MDP. In addition to simulation-based checks such as mask EPE or dose margin, geometry-based rules are also available to detect quality issues such as slivers or CD splits. Dose margin related hotspots can also be detected by setting a correct detection threshold.

In this paper, we will demonstrate GPU-acceleration for geometry processing, and give examples of mask check results and performance data. GPU-acceleration is necessary to make simulation-based mask MDP verification acceptable.

A record 73 industry luminaries representing more than 30 different companies from across the semiconductor ecosystem participated in the 2016 eBeam Initiative perceptions survey. The eBeam Initiative also completed its second annual mask makers’ survey with feedback from 10 captive and merchant photomask manufacturers. Among the results of the members’ perception survey, respondents remained optimistic in the implementation of EUV lithography for semiconductor high-volume manufacturing (HVM), with confidence in EUV increasing over other next-generation lithography (NGL) techniques compared with last year’s survey. In addition, expectations on the use of multi-beam technology for advanced photomask HVM by the end of 2018 continue to remain strong. Results from the eBeam Initiative’s second annual mask makers’ survey indicate several surprising trends on mask making related to write times, turn-around time (TAT) for mask manufacturing, resists, mask yields and other critical issues. The author will review the key findings and offer his viewpoint on their significance.

We propose a new concept of tuning a point-spread function (a “kernel” function) in the modeling of electron beam lithography using the machine learning scheme. Normally in the work of artificial intelligence, the researchers focus on the output results from a neural network, such as success ratio in image recognition or improved production yield, etc. In this work, we put more focus on the weights connecting the nodes in a convolutional neural network, which are naturally the fractions of a point-spread function, and take out those weighted fractions after learning to be utilized as a tuned kernel. Proof-of-concept of the kernel tuning has been demonstrated using the examples of proximity effect correction with 2-layer network, and charging effect correction with 3-layer network. This type of new tuning method can be beneficial to give researchers more insights to come up with a better model, yet it might be too early to be deployed to production to give better critical dimension (CD) and positional accuracy almost instantly.

Mask writers need to be able to write sub-50nm features accurately. Nano-imprint lithography (NIL) masters need to create sub-20nm line and space (L:S) patterns reliably. Increasingly slower resists are deployed, but mask write times need to remain reasonable. The leading edge EBM-9500 offers 1200A/cm² current density to shoot variable shaped beam (VSB) to write the masks.

Last year, thermal effect correction (TEC) was introduced by NuFlare in the EBM-9500¹. It is a GPU-accelerated inline correction for the effect that the temperature of the resist has on CD. For example, a 100nm CD may print at 102nm where that area was at a comparably high temperature at the time of the shot. Since thermal effect is a temporal effect, the simulated temperature of the surface of the mask is dynamically updated for the effect of each shot in order to accurately predict the cumulative effect that is the temperature at the location of the shot at the time of the shot and therefore its impact on CD. The shot dose is changed to reverse the effects of the temperature change.

This paper for the first time reveals an enhancement to this thermal model and a simulator for it. It turns out that the temperature at the time each location receives backscatter from other shots also make a difference to the CD. The effect is secondary, but still measurable for some resists and substrates. Results of a test-chip study will be presented.

The computation required for the backscatter effect is substantial. It has been demonstrated that this calculation can be performed fast enough to be inline with the EBM-9500 with a reasonable-sized computing platform. Run-time results and the computing architecture will be presented.

Over the last two decades, eBeam mask writers have added inline correction features. Particularly when minimum feature sizes on mask went below 100nm a decade ago, the need for more precision within a reasonable write time increased the demand for more corrections. Inline correction is better for turnaround time and throughput, but inline correction is computationally limited because it is unacceptable for computation to limit the machine write time.

Simultaneously, the same need for linearity correction, printability enhancement, and resilience to manufacturing variation has caused much innovation in offline mask data preparation and mask process correction. Typically, the writer performs inline correction for backscatter, fogging, loading, charging and thermal effects, but leaves <10μm effects to offline correction.

With multi-beam writers, the write time is independent of shape count. Any set of input shapes is rasterized to a set of arrays of equal sized pixels that are each independently dosed to write the desired shapes. Multi-beam writers also have a certain minimum write time that is required for writing even a very small number of simple shapes. This gives rise to the possibility of providing linearity correction features, even for the short-range effects as inline correction in the writer. Such inline correction has zero impact on throughput and turnaround time of mask making.

This paper introduces the GPU-accelerated inline linearity correction capability of the NuFlare MBM-1000 for the first time.

Multi-beam mask writer MBM-1000 will be released in Q4 2017 for N5 semiconductor production. Performance of MBM-1000 is under verification and tuning by using alpha tool upgraded to high-volume manufacturing (HVM) system. It is designed to realize better resolution and higher throughput than EBM-9500, our latest variable-shaped-beam writer, at shot count higher than 500 Gshot/pass. Writing test after upgrade confirmed that MBM-1000 has better beam resolution than EBM-9500 as expected by optics design. It also showed that position of beam array projected on target was stable during one hour writing enough to accomplish registration target. Design of data transfer system and BAA for 300-Gbps data rate is described.

The Mask Data Correctness Check (MDCC) is a reticle-level, multi-layer DRC-like check evolved from mask rule check (MRC). The MDCC uses extended job deck (EJB) to achieve mask composition and to perform a detailed check for positioning and integrity of each component of the reticle. Different design patterns on the mask will be mapped to different layers. Therefore, users may be able to review the whole reticle and check the interactions between different designs before the final mask pattern file is available. However, many types of MDCC check results, such as errors from overlapping patterns usually have very large and complex-shaped highlighted areas covering the boundary of the design. Users have to load the result OASIS file and overlap it to the original database that was assembled in MDCC process on a layout viewer, then search for the details of the check results. We introduce a quick result-reviewing method based on an html format report generated by Calibre® RVE. In the report generation process, we analyze and extract the essential part of result OASIS file to a result database (RDB) file by standard verification rule format (SVRF) commands. Calibre® RVE automatically loads the assembled reticle pattern and generates screen shots of these check results. All the processes are automatically triggered just after the MDCC process finishes. Users just have to open the html report to get the information they need: for example, check summary, captured images of results and their coordinates.

The number of curvilinear patterns present on the masks will increase drastically in the next generations of semiconductor devices. Multibeam mask writers are foreseen to enable a more widespread use of curvilinear shapes. Several applications can benefit from curvilinear patterns like silicon photonics or Inverse Lithography Technology (ILT). We propose a set of innovative algorithms that uses a dedicated representation for curvilinear patterns. This approach simplifies the data handling and decreases file size by reducing the degree of freedom on the database. It also allows improving the output quality with a more precise control of the geometric correction. We illustrate the benefit of using the curvilinear data representation to the Mask Proximity correction and Mask Rule Check.

Lithography simulation is an essential technique for today’s semiconductor manufacturing process. In order to calculate an entire chip in realistic time, compact resist model is commonly used. The model is established for faster calculation. To have accurate compact resist model, it is necessary to fix a complicated non-linear model function. However, it is difficult to decide an appropriate function manually because there are many options. This paper proposes a new compact resist model using CNN (Convolutional Neural Networks) which is one of deep learning techniques. CNN model makes it possible to determine an appropriate model function and achieve accurate simulation. Experimental results show CNN model can reduce CD prediction errors by 70% compared with the conventional model.

Advanced Inverse Lithography Technology (ILT) can result in mask post-OPC databases with very small address units, all-angle figures, and very high vertex counts. This creates mask inspection issues for existing mask inspection database rendering. These issues include: large data volumes, low transfer rate, long data preparation times, slow inspection throughput, and marginal rendering accuracy leading to high false detections. This paper demonstrates the application of a new rendering method including a new OASIS-like mask inspection format, new high-speed rendering algorithms, and related hardware to meet the inspection challenges posed by Advanced ILT masks.

Continuous shrinking of the semiconductor device dimensions demands steady improvements of the lithographic resolution on wafer level. These requirements challenge the photomask industry to further improve the mask quality in all relevant printing characteristics. In this paper topography of the Phase Shift Masks (PSM) was investigated. Effects of hard mask etch on phase shift uniformity and mask absorber profile were studied. Design of experiments method (DoE) was used for the process optimization, whereas gas composition, bias power of the hard mask main etch and bias power of the over-etch were varied. In addition, influence of the over-etch time was examined at the end of the experiment. Absorber depth uniformity, sidewall angle (SWA), reactive ion etch lag (RIE lag) and through pitch (TP) dependence were analyzed. Measurements were performed by means of Atomic-force microscopy (AFM) using critical dimension (CD) mode with a boot-shaped tip. Scanning electron microscope (SEM) cross-section images were prepared to verify the profile quality. Finally CD analysis was performed to confirm the optimal etch conditions. Significant dependence of the absorber SWA on hard mask (HM) etch conditions was observed revealing an improvement potential for the mask absorber profile. It was found that hard mask etch can leave a depth footprint in the absorber layer. Thus, the etch depth uniformity of hard mask etch is crucial for achieving a uniform phase shift over the active mask area. The optimized hard mask etch process results in significantly improved mask topography without deterioration of tight CD specifications.

The introduction of EUV lithography to high volume manufacturing is now within reach for 7nm technology node and beyond (1), at least for some steps. The scheduling is in transition from long to mid-term. Thus, all contributors need to focus their efforts on the production requirements. For the photo mask industry, these requirements include the control of defectivity, CD performance and lifetime of their masks. The mask CD performance including CD uniformity, CD targeting, and CD linearity/ resolution, is predominantly determined by the photo resist performance and by the litho and etch processes. State-of-the-art chemically amplified resists exhibit an asymmetric resolution for directly and indirectly written features, which usually results in a similarly asymmetric resolution performance on the mask. This resolution gap may reach as high as multiple tens of nanometers on the mask level in dependence of the chosen processes. Depending on the printing requirements of the wafer process, a reduction or even an increase of this gap may be required. A potential way of tuning via the etch process, is to control the lateral CD contribution during etch. Aside from process tuning knobs like pressure, RF powers and gases, which usually also affect CD linearity and CD uniformity, the simplest knob is the etch time itself. An increased over etch time results in an increased CD contribution in the normal case. , We found that the etch CD contribution of ARC layer etch on EUV photo masks is reduced by longer over etch times. Moreover, this effect can be demonstrated to be present for different etch chambers and photo resists.

This invited paper reviews progress over the past ten years of contributed effort to the understanding and the mitigation of multilayer defects on the EUV mask blank. These defects are an EUV-specific type of mask defects. Whereas the only true solution is to totally avoid the presence of such ML-defects during blank manufacturing, some level of capability of printability mitigation has been demonstrated, both by absorber compensation repair and by pattern shift. In both cases, it is essential that one can build on a full-proof blank inspection capability, that detects all printable blank defects, at a very low false detection rate, such as by using actinic blank inspection. This capability, together with providing accurate defect location information, establishes an essential prerequisite for their mitigation or avoidance. On the latter, the proposal is made to extend pattern shift to intentional pattern deformation.

An EUV dark field image of a phase defect on a patterned mask was studied using simulation. The wafer images of the defect were obtained by simulation, and wafer CD deviation caused by the defect was calculated. The dark field image of the defect was also obtained by simulation, and the defect signal intensity was calculated and compared with the wafer CD deviation. There was a significant relationship between the wafer CD deviation and the defect signal intensity in the dark field image at the respective maximum in the through-focus range. Therefore, the wafer CD deviation can be estimated from the dark field image using though focus.

Recently TNO has established EBL2; an exposure and analysis facility for testing EUV optics, reticles and pellicles under relevant EUV scanner and source conditions. The facility and EUV source complies with the ASML power roadmap of EUV systems up to a power of 500 W IF. This enables life time testing of EUV optics, reticles and pellicles under conditions which are not yet available to industry, helping the industry in preparing for HVM production. The EBL2 facility consists of a EUV source, collector optics, exposure chamber, XPS chamber, and automated sample handling. The exposure chamber has capabilities for plasma analysis, imaging ellipsometry for in-situ analysis of the sample under radiation, photodiodes for power measurements and a scintillator disk for spot profiles. It is possible to insert spectral purity filters and apertures in the beam line for wavelength tuning and beam shaping. The source is Sn fueled DPP source made by our partner Ushio and is based on the proven technology from the ASML AD-tools, providing a similar spectrum and pulse shape as used in the ASML NXE scanners. We show the results of first light obtained in December 2016. The XPS is capable of handling and analyzing full reticles and data on the obtained surface sensitivity and imaging quality will be shown.

EUV technology is according to current trend approaching the final development phase in which defect free EUV masks are of key importance for development and optimization of the lithography process. This task consists of three contributing aspects- defect free multilayer blank, mask manufacturing process with very low defect formation probability and availability of repair process for EUV mask. In comparison to optical mask, development of the repair process for EUV mask is different in several aspects. The fact, that the TaN absorber is placed on top of Mo/Si mirror is making the process very sensitive to variation of the mask material, as the etch rate of the mirror is significantly higher, than that of absorber, when no capping layer is present between the absorber and ML mirror. The presence of the Ru capping layer increases the process window due to significant selectivity improvement by one or two orders of magnitude, however, the capping layer is very sensitive to damage by preceding manufacturing processes. Its thickness and also it chemical purity - lack of modification by incorporation of impurities is crucial for successful mask repair. The repair process for optical masks is typically optimized using AIMS for both development and qualification of the process. The availability of EUV AIMS system is very limited, for what reason we have to rely on other measures during the process development and use the AIMS for process qualification only, or use correlation between e.g. CD SEM or AFM measurement and AIMS data for selection and qualification of the repair process. Also the usage of mask – exposure on the scanner is modifying the mask surface. Therefore the impact of the mask exposure needs to be investigated, when EUV gets in HVM stage. In the past, the influence of the mask cleaning process on the integrity of EUV mask was investigated, with respect to several lithography-critical parameters as actinic reflectivity, critical dimension (CD) shift, edge roughness and surface roughness. The reparability of the mask was so far not in focus, assuming, that mask can be repaired anytime during its lifetime. This missing item needed for the successful usage of EUV mask needs to be checked and status confirmed prior start of the HVM.

Recently, much attention has been paid on nanoimprint lithography (NIL) because of its capability for fabricating device at a low cost without multiple patterning. It is considered as a candidate for next generation lithography technology. NIL is one to one lithography and contact transfer technique using template. Therefore, the lithography performance depends greatly on the quality of the template pattern. And there are some challenges to be solved for defect repair of template because pattern size of template is as same as that of wafer. In order to realize the defect repair of template using electron beam (EB) repair tools, it is necessary to control the EB irradiated area and dose amount of EB repair process more accurately. By optimizing these conditions, EB repair process for template has been improved. In this paper, we evaluated etching repair of a master template and the imprinting to replica. Programmed missing defects on master template were repaired by changing parameters of EB repair tool. It was confirmed that the relationship of critical dimension (CD) and depth of etching repair process for master template and the influence on replica imprinting. As a result, the repair process for master template with hole pattern enables the corresponding CD error of the replica template to be less than ±10% of the target CD.

Nanoimprint Lithography (NIL) has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography* (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for high volume semiconductor manufacturing. Included on the list are overlay, throughput and defectivity. Imprint lithography, like any lithographic approach requires that defect mechanisms be identified and eliminated in order to consistently yield a device. NIL has defect mechanisms unique to the technology, and they include liquid phase defects, solid phase defects and particle related defects. Especially more troublesome are hard particles on either the mask or wafer surface. Hard particles run the chance of creating a permanent defect in the mask, which cannot be corrected through a mask cleaning process. If Cost of Ownership (CoO) requirements are to be met, it is critical to minimize particle formation and extend mask life. To meet the CoO requirements, mask life must meet or exceed 1000 wafers. If, we make the conservative assumption that every particles causes damage to the mask pattern, the number of particle adders must be less than 0.001 pieces per wafer pass in the NIL tool. Therefore, aggressive strategies are needed to reduce particles in the tool. In this paper, we will report on the techniques required to meet this condition and will describe how the particle reduction techniques can be extended to our FPA-1200NZ2C system.

Semiconductor technology nodes are steadily miniaturizing. On the other hand, various efforts have been made to reduce costs, mass production lines have shifted from 200 mmφ of Si wafer to 300 mmφ, and technology development of Si wafer 450 mmφ is also in progress. As a photomask, 6-inch size binary Cr mask has been used for many years, but in recent years, the use of 9-inch binary Cr masks for Proximity Lithography Process in automotive applications, MEMS, packages, etc. has increased, and cost reduction has been taken. Since the miniaturization will progress in the above applications in the future, products corresponding to miniaturization are also desired in 9-inch photomasks. The high grade Cr - binary mask blanks used in proximity exposure process, there is a prospect of being able to use it by ULVAC COATING CORPORATION's tireless research. As further demands for miniaturization, KrF and ArF Lithography Process, which are used for steppers and scanners , there are also a demand for 9-inch size Mask Blanks. In ULVAC COATING CORPORATION, we developed a 9 - inch size KrF PSM mask Blanks prototype in 2016 and proposed a new high grade 9 - inch photomask. This time, we have further investigated and developed 9-inch size ArF PSM Mask Blanks corresponding to ArF Lithography Process, so we report it.

As technical advances continue, the pattern size of semiconductor circuit has been shrunk. Defect control becomes tighter due to decrease in defect size that affects the image printed on the wafer. It is critical to the photomask which contained considerably shrunk circuit and ultra high density pattern for sub – 20nm tech device. Therefore particle source from all processes should be controlled extremely. Most of defects generated in mask fabrication processes have been mainly created during each unit process. A different formation mechanism defect which formed between processes to processes is starting to emerge. In this paper, we introduce a very distinctive crosstalk defect between develop to etch process. This defect only in the presence of photoresist, developer, etching species and interaction will produce. We also successful to reproduce this crosstalk defect by particle monitor mask without exposing the production pattern. By the experiment results we will bring forward the possible defect generation mechanism. Based on this understanding, appropriate solution to mitigate defects caused by crosstalk defect between develop to etch will be proposed.

With wafer technology node migrating to 14nm, the noise of wafer critical dimension (CD) control from photomask become more significant due to a mask thickness no longer thin relative to the dimensions. Therefore, the Opaque MoSi-On-Glass (OMOG) photomask is widely used for high-end wafer production because its thin structure is an advantage for 3D electromagnetic field (3DEMF) mask modeling. In other words, it also means the CD control in such high-end wafer product become more and more important. The absorber layer of OMOG is composed of MoSiN which has faster etching rate. Although such kind of MoSiN can help repairing dark defect faster, it also bring some extra etchings what lead to over repair that impact photomask’s CD control and yield. In order to stabilize the post-repair CD variation, we performed several treatments at pre-repair cleaning and a post-repair treatment to stabilize film properties. In addition, we also performed compositional analysis by EDX line scan to compare the compositional differences.

SiN-based absorber materials are considered to be the new work horse for cutting-edge patterning using 193-nm immersion lithography. The high robustness against cleaning procedures and the low susceptibility for haze makes SiN an ideal material for phase-shift masks. Reliable metrology with high precision, on target as well as on feature, is enabled by the LMS IPRO^TM metrology tool. This is achieved by taking into account the optical properties of the novel materials and utilisation of the high-accuracy die-to-database algorithm. Simulation as well as actual measurement results are presented. Cost effectiveness of the LMS IPRO is demonstrated by comparison of high-performance mode results versus high-throughput results, confirming suitable metrology performance for high-volume manufacturing.

It has been still highly required for cost efficient solution with easy operation for full-automated CD measurement for line width about 500nm up to 5μm on photomask, because it is frequently use such photomask in the process of manufacturing MEMS sensor for IoT and some devices made in BCD (Bipola CMOS DMOS). As reply to such demand in photomask manufacturing field, we try to take a low noise digital camera technology and LED light source for i-line, which are recently developed, into new measuring tool in order to achieve 1nm (3σ) repeatability for line width measurement between 300nm to 10μm. In addition, for the purpose of full-automated operation, it is very important to find where an initial target line in dense pattern. To achieve such auto line detection precisely, we have improved accuracy of high precision stage (20nm as 3σ) and an alignment algorithm of MEMS Stepper to combine with this tool. As for user-friendly interface, Windows based software helps a lot for not only the operation but also recipe creation or edition in Excel. Actually, in the MEMS manufacturing process, there are various photomasks which need to be check and measure frequently therefore various recipe files are also have to be created and edited frequently.. In order to meet such a requirement in photomask management, we try to make it true by mixing old and new techniques together into one system, which comes to fully automated and cost efficient tool with 1nm repeatability in CD measurement.

The back end of line (BEOL) workflow in the mask shop still has crucial issues throughout all standard steps which are inspection, disposition, photomask repair and verification of repair success. All involved tools are typically run by highly trained operators or engineers who setup jobs and recipes, execute tasks, analyze data and make decisions based on the results. No matter how experienced operators are and how good the systems perform, there is one aspect that always limits the productivity and effectiveness of the operation: the human aspect. Human errors can range from seemingly rather harmless slip-ups to mistakes with serious and direct economic impact including mask rejects, customer returns and line stops in the wafer fab. Even with the introduction of quality control mechanisms that help to reduce these critical but unavoidable faults, they can never be completely eliminated. Therefore the mask shop BEOL cannot run in the most efficient manner as unnecessary time and money are spent on processes that still remain labor intensive. The best way to address this issue is to automate critical segments of the workflow that are prone to human errors. In fact, manufacturing errors can occur for each BEOL step where operators intervene. These processes comprise of image evaluation, setting up tool recipes, data handling and all other tedious but required steps. With the help of smart solutions, operators can work more efficiently and dedicate their time to less mundane tasks. Smart solutions connect tools, taking over the data handling and analysis typically performed by operators and engineers. These solutions not only eliminate the human error factor in the manufacturing process but can provide benefits in terms of shorter cycle times, reduced bottlenecks and prediction of an optimized workflow. In addition such software solutions consist of building blocks that seamlessly integrate applications and allow the customers to use tailored solutions. To accommodate for the variability and complexity in mask shops today, individual workflows can be supported according to the needs of any particular manufacturing line with respect to necessary measurement and production steps. At the same time the efficiency of assets is increased by avoiding unneeded cycle time and waste of resources due to the presence of process steps that are very crucial for a given technology. In this paper we present details of which areas of the BEOL can benefit most from intelligent automation, what solutions exist and the quantification of benefits to a mask shop with full automation by the use of a back end of line model.

Nanoimprint lithography (NIL) is one of the highest potential candidates for next generation lithography in semiconductors. NIL is very useful technology for pattern fabrication in high resolution compared to conventional optical lithography. NIL technology makes use of replication from quartz templates. The cross-sectional profile of the template is directly transferred to the resist profile on a wafer. Accordingly, the management of the cross-sectional profile on the template pattern is much more important than on each photomask. In our previous report, we had studied the performance of measuring cross-sectional profiles using grazing-incidence small-angle X-ray scattering (GISAXS). GISAXS has made it possible to analyze the repeated nanostructure patterns with a 2D X-ray scattering pattern. After various researches, we found the application is very effective in the method of cross-sectional profiling of sub-20 nm half-pitch lines-and-spaces (LS) patterns. In this report, we investigated the capabilities of measuring cross-sectional profiles for hole patterns using GISAXS. Since the pattern density of hole patterns is much lower than that of LS patterns, the intensity of X-ray scattering in hole measurements is much lower. We optimized some measurement conditions to build the hole measurement system. Finally, the results suggested that 3D profile measurement of hole pattern using GISAXS has sufficient performance to manage the cross-sectional profile of template. The measurement system using GISAXS for measuring 3D profiles establishes the cross-sectional profile management essential for the production of high quality quartz hole templates.

In accordance with improvement of FPD technology, masks such as phase shift mask (PSM) and multi-tone mask (MTM) for a particular purpose also have been developed. Above all, the MTM consisted of more than tri-tone transmittance has a substantial advantage which enables to reduce the number of mask demand in FPD fabrication process contrast to normal mask of two-tone transmittance.[1,2] A chromium (Cr)-based MTM (Typically top type) is being widely employed because of convenience of etch process caused by its only Cr-based structure consisted of Cr absorber layer and Cr half-tone layer. However, the top type of Cr-based MTM demands two Cr sputtering processes after each layer etching process and writing process. For this reason, a different material from the Cr-based MTM is required for reduction of mask fabrication time and cost. In this study, we evaluate a MTM which has a structure combined Cr with molybdenum silicide (MoSi) to resolve the issues mentioned above. The MoSi which is demonstrated by integrated circuit (IC) process is a suitable material for MTM evaluation. This structure could realize multi-transmittance in common with the Cr-based MTM. Moreover, it enables to reduce the number of sputtering process. We investigate a optimized structure upon consideration of productivity along with performance such as critical dimension (CD) variation and transmittance range of each structure. The transmittance is targeted at h-line wavelength (405 nm) in the evaluation. Compared with Cr-based MTM, the performances of all Cr-/MoSi-based MTMs are considered.

Lithographical patterning on the surface of a fine pipe with a thin wall is required for fabricating three-dimensional micro-parts. For this reason, a new exposure system for printing patterns on a cylindrical pipe by synchronous rotary scan-projection exposure was developed. Using the exposure system, stent-like resist patterns with a width of 251 μm were printed on a surface of stainless-steel pipe with an outer diameter of 2 mm. The exposure time was 30 s. Next, the patterned pipe was chemically etched. As a result, a stent-like mesh pipe with a line width of 230 μm was fabricated. It was demonstrated that the new method had a potential to be applied to fabrications of stent and other cylindrical micro-parts.

Recently, it is required to develop a method for fabricating cylindrical micro-components in the field of measurement and medical engineering. Here, electrolytic etching of fine stainless-steel pipes patterned by laser-scan lithography was researched. The pipe diameter was 100 μm. At first, a pipe coated with 3-7 μm thick positive resist (tok, PMER P LA-900) was exposed to a violet laser beam with a wavelength of 408 nm (Neoark,TC20-4030-45). The laser beam was reshaped in a circle by placing a pinhole, and irradiated on the pipe by reducing the size in 1/20 using a reduction projection optics. Linearly arrayed 22 slit patterns with a width of 25 μm and a length of 175 μm were delineated in every 90-degree circumferential direction. That is, 88 slits in total were delineated at an exposure speed of 110 μm/s. In the axial direction, patterns were delineated at intervals of 90 μm. Following the pattern delineation, the pipe masked by the resist patterns was electrolytically etched. The pipe was used as an anode and an aluminum cylinder was set as a cathode around the pipe. As the electrolyte, aqueous solution of NaCl and NH4Cl was used. After etching the pipe, the resist was removed by ultrasonic cleaning in acetone. Although feasibility for fabricating multi-slit pipes was demonstrated, sizes of the etched slits were enlarged being caused by the undercut, and the shapes were partially deformed, and all the pipes were snapped at the chuck side.

Printing of thick resist patterns with a high aspect ratio and vertical side walls was investigated. Such resist patterns are required for using as molds of electroplating, and patterning feasibility in a small field of 2 mm square was verified in the past researches. However, it is necessary to print patterns homogeneously in an exposure field with a practical size of larger than 10 mm square, for example. As profiles of resist patterns for the use of electroplating molds, rectangular cross-sections are preferable. For this reason, patterns were printed in the negative resist SU-8 with a thickness of 50 μm using an exposure system with a field size of 15 mm square. Before using the thick SU-8, the best focus position of the exposure system was investigated. To find out the best focus position, line and space (LS) patterns were printed using a positive resist OFPR-800 with a thickness of approximately 1 μm. The focus position where patterns were most clearly formed on the wafer was decided to be the focus origin, and defocuses were controlled by moving wafers downward. Next, 50-μm LS patterns were printed in 50-μm thick SU-8. As a result, LS patterns with rectangular cross sections and a height of 40 μm were obtained when the defocus and the exposure time were set at 2000 μm and for 70 seconds, respectively. It was demonstrated that patterns with rectangular cross sections were printed in 3x5 mm² exposure fields.

In extreme ultraviolet (EUV) lithography, development of review tools for EUV mask pattern and phase defect at working wavelength of 13.5 nm is required. The EUV mask is composed of an absorber pattern (50 – 70 nm thick) and Mo/Si multilayer (280 nm thick) on a glass substrate. This mask pattern seems three-dimensional (3D) structure. This 3D structure would modulate EUV reflection phase, which would cause focus and pattern shifts. Thus, EUV phase imaging is important to evaluate this phase modulation. We have developed coherent EUV scatterometry microscope (CSM), which is a simple microscope without objective optics. EUV phase and intensity image are reconstructed with diffraction images by ptychography with coherent EUV illumination. The high-harmonic-generation (HHG) EUV source was employed for standalone CSM system. In this study, we updated HHG system of pump-laser reduction and gas-pressure control. Two types of EUV mask absorber patterns were observed. An 88-nm lines-and-spaces and a cross-line patterns were clearly reconstructed by ptychography. In addition, a natural defect with 2-μm diameter on the cross-line was well reconstructed. This demonstrated the high capability of the standalone CSM, which system will be used in the factories, such as mask shops and semiconductor fabrication plants.

The positive tone resist consisted of methyl-α-chloroacrylate (ACM) and α-methylstyrene (MS) has higher sensitivity and higher dry etching resistance than poly (methylmethacrylate) (PMMA) due to the presence of a chlorine atom and a phenyl group. Copolymers consisted of ACM and p-chloro-α-methylstyrene (PCMS), where the additional chlorine atom is introduced in phenyl group compared with ACM-MS resist are synthesized and their exposure characteristics are investigated. ACM-PCMS resist with the ACM:PCMS composition ratio of 49:51 indicates the high solubility for amyl acetate developer. As the ACM composition ratio increases, the solubility of ACM-PCMS resist is suppressed. In both ACM-PCMS and ACM-MS resists, the sensitivity decreases while the contrast increases with increasing ACM ratio. When the composition ratio of ACM:PCMS is 69:31, 100/100 nm line and space pattern having a good shape is obtained at 120 μC/cm² which is comparable to the required exposure dose for conventional ACM-MS resist with ACM:MS=50:50. Dry etching resistance of ACM:PCMS resists for Ar gas is also presented.