This PDF file contains the front matter associated with SPIE Proceedings Volume 10807, including the Title Page, Copyright information, Table of Contents, and Conference Committee listing.

Nanoimprint lithography manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of widediameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. In this paper, we review the progress and status of the FPA-1200NZ2C wafer imprint system and FPA-1100NR2 mask replication system. To address high volume manufacturing concerns, an FPA-1200NZ2C four-station cluster tool is used in order to meet throughput and cost of ownership requirements (CoO). Throughputs of up to 90 wafers per hour were achieved by applying a multi-field dispense method. Mask life of up to 81 lots, using a contact test mask were demonstrated. A mix and match overlay of 3.4 nm has been demonstrated and a single machine overlay across the wafer was 2.5nm. There is Mask Replication criteria that are crucial to the success of a replication platform include image placement (IP) accuracy and critical dimension uniformity (CDU). Data is presented on both of these subjects. With respect to image placement, an IP accuracy (after removing correctables) of 0.8nm in X, 1.0nm in Y has been demonstrated.

Nanoimprint Lithography (NIL) has been shown to be an effective technique for replication of nano-scale features. The NIL process involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for high volume semiconductor manufacturing. Included on the list are overlay, throughput and defectivity. Imprint lithography, like any lithographic approach requires that defect mechanisms be identified and eliminated in order to consistently yield a device. NIL has defect mechanisms unique to the technology, and they include liquid phase defects, solid phase defects and particle related defects. Especially more troublesome are hard particles on either the mask or wafer surface. Hard particles run the chance of creating a permanent defect in the mask, which cannot be corrected through a mask cleaning process. If Cost of Ownership (CoO) requirements are to be met, it is critical to minimize particle formation and extend mask life. In this work, methods including in-situ particle removal, mask neutralization and resist filtration are discussed in detail. As a result of these methods, along with already developed techniques, particle counts on a wafer were reduced to only 0.0005 pieces per wafer path or a single particle over 2000 wafers, with a next target of 0.0001 pieces per wafer path. Particle adder reduction correlates directly with mask life, and a mask life of 81 lots (about 2000 wafers) is demonstrated. New methods are now under development to further extend mask and reduce cost of ownership. In this work on-tool wafer inspection and mask cleaning methods are also introduced.

Recently, high-resolution exposure machine has been developed for production of high-definition (HD) panels and higher-flat photomask substrates for FPD is being expected for panel makers to produce HD panels. In this report, we review the Shin-Etsu’s advanced technique of producing super-high-flat and shape-controlled large size photomask substrates that we reported the last PMJ 2017 a year ago and make a subsequent progress report thus far. Shin-Etsu has developed surface polishing and planarization technology of photomask substrates. Our most advanced IC Photomask substrates have gained the highest estimation and appreciation from our customers because of their excellent surface quality (non-defect surface without sub-0.1μm size defects) and ultimate flatness (sub-0.1μm order having achieved). By scaling up those IC photomask substrate technologies and developing unique large-size processing technologies, we have achieved creating high-flat large substrates, even G8.x-photomask and G10-photomask substrates as well as regular G6-G8 photomask substrates. The core technology is that the surface shape of the substrate is completely controlled by the numerical control system with height information inputs and the processing calculation. For example, we can regularly produce substrates with their flatness of 3μm or less for each size, measurement of which is carried out with high reliability tuned flatness tester. In addition, we can produce a substrate whose surface shape is arbitrary by using this core technology. It means we can deal with customers’ demanding shape or potentially necessary shape in the future to contribute to the soon-coming next generation FPD industries.

Liquid Crystal Displays (LCDs), which are the current prevalent displays, can be roughly separated into two modules. Of these, the Color Filter (CF) module is frequently manufactured using a proximity exposure system also known as proximity printing, which offers relatively lower resolution and higher throughput. This is because the CF only functions as an optical filter and so only requires rough patterning with the width of large sub-pixel units. However, due to the recent rapid shrinkage of pixel units, the productivity of CF is worsening. This is particularly evident in Black Matrix (BM), which requires finer patterns than for other CF layers and therefore is becoming a bottleneck preventing the progress of displays, especially for manufacturers who have only proximity printing equipment. We demonstrated that it is possible to achieve practical optical image miniaturization in FPD lithography via the appropriate use of Half-Tone (HT) exposure which suppresses the light intensity, as per the Fresnel diffraction theory which governs proximity printing. Two desirable results were subsequently obtained in tests using actual BM processes: stable formation with fine BM lines of less than 6μm width, and an improvement in the corner shape using sub-resolution HT features.

Multi-beam mask writer MBM-1000 is developed for N5 semiconductor production. It is designed to accomplish high resolution with 10-nm beam and high throughput with 300-Gbps blanking aperture array (BAA) and inline real-time data path. It has better beam resolution than EBM-9500 and has higher throughput at shot count more than 500 Gshot/pass. To further improve patterning resolution, pixel level dose correction (PLDC) is implemented to MBM-1000. It performs dose contrast enhancement by dose modulation pixel by pixel. Correction efficiency of PLDC is evaluated for linearity correction by simulation with threshold dose model. It is concluded that PLDC corrects linearity efficiently even without extra dose modulation, and improves dose margin with additional dose modulation of 140%.

We have investigated Cr film etching mechanism systematically in order to minimize CDU (CD Uniformity). As a result, employing our dry etching system ARESTM with optimized etch process we achieved an excellent CDU(3σ) (0.5nm with etch contribution). Cr film has been widely used not only for the light-shielding film at Cr Binary Mask but also as a hard mask film at even the leading edge photomasks (Hard Mask-PSM (Phase Shift Mask)). In case of used as a hard-mask, this plays very important role to determine etching process accuracy and to achieve the minimal CDU. As LSI downscaling and complication of their pattern layouts, the current dry etch technology faces technical challenges such as the difficulties in CD control and will be not sufficient to meet requirements. In this study, each behavior of Cr etching process at the various process parameters and various pattern layouts are investigated.

The specifications performance data for the latest generation system are compared to prior generations. These results are shown for both missing pattern (or hard) and unknown contamination (or soft) defects of various classifications in different patterns. For hard defects, capability will be demonstrated down to the 65 nm node, with soft defect repair and clean significantly exceeding to even smaller nodes down to 14 nm. The latter is of particular note, especially in the application of the cleaning of fall-on unknown contaminates on pelliclized photomasks. Finally, there will be a discussion of future work to further develop soft repair/clean process and laser processes for other mask technologies.

The specifications performance data for the latest generation system are compared to prior generations. These results are shown for both missing pattern (or hard) and unknown contamination (or soft) defects of various classifications in different patterns. For hard defects, capability will be demonstrated down to the 65 nm node, with soft defect repair and clean significantly exceeding to even smaller nodes down to 14 nm. The latter is of particular note, especially in the application of the cleaning of fall-on unknown contaminates on pelliclized photomasks. Finally, there will be a discussion of future work to further develop soft repair/clean process and laser processes for other mask technologies.

As advancement of semiconductor to 1Xnm nodes and beyond, the importance of multilayer lithography process is increasing. Generally, multilayer consists of photoresist layer, middle layer and underlayer. Theses layer materials prefer spin-on type to CVD type from the viewpoint of the cost of ownership and process simplicity. The key requirements which spin-on materials must satisfy are to be soluble in organic solvent and insoluble after bake process to coat upper layer materials, gap filling and planarization performances, etch controllability and easy strippability. In particular, the solubility switchable property, the gap filling and planarization performance on topo-patterned substrate are receiving much attention recently. In this report, novel spin-on carbon (SOC) material for multilayer lithography process will be described. The SOC materials we present here consist of the thermoplastic polymer which we originally developed and PGMEA or cyclohexanone as solvent, there is no any other additive. This varnish can be applied to a substrate by spin-on coating. It is worth noting that the SOC layer after bake process becomes insolubilized for PGMEA. This property enables to use PGMEA when stacking upper layer. Because of the intrinsic thermal flow nature of our thermoplastic polymer, the gap filling and planarization performances are excellent for the topo-patterned substrate which includes pad, open and dense line area. The etch rate of the SOC layer for C_xF_y gas is constant, so these materials have good etch controllability. Therefore, these SOC materials could be potentially candidate for planarization use in multilayer lithography process.

The eBeam Initiative completed its third annual mask makers’ survey in 2017 with anonymous feedback from 10 captive and merchant photomask manufacturers. Participation in the 2017 eBeam Initiative perceptions survey increased to more than 40 different companies versus 30 companies the previous year. In 2017, 75 industry luminaries responded from across the semiconductor ecosystem.

19x nm defect inspection is the strongest candidate for initial EUV production until high-throughput E-Beam or Actinic inspection is ready. However, EUV mask inspection on an optical, 19x nm wavelength tool has some difficulties compared to optical masks. The issue of varying base pattern contrast is an example of one such difficulty. This paper explores the defect sensitivity differences among the base pattern sizes, as well as the relationship between base pattern contrast and defect sensitivity. Focus offset and polarization adjustments on programmed defect test masks are used to create new inspection recipes.

The era of EUV technology is approaching and use of EUV lithography in chip manufacturing process was reported. The EUV technology has still serious challenges to overcome, to which belong defectivity, source power and throughput of the exposure tool, to name the most obvious. Important part of the lithography, which differs significantly from previous optical technology, is the mask. The mask stack, especially the multilayer (ML) mirror surface and its protection is of high importance, determining the reflectivity of the mask. The ML mirror is protected by a thin Ru capping layer, which however is very sensitive to oxidation and damage during mask manufacturing processes and its use.[1] Also estimation of the capping layer thickness is not trivial, and is unreliable by damage free analytical methods. In our work, we focus on the capping layer integrity and assess it as function of several applied cleaning processes. The integrity is examined via e-beam repair process and AFM measurement of the feature height. As identified in previous experiments, the UV exposure used in manufacturing processes has significant influence on the Ru layer at some conditions. However, there is good chance to find conditions at which the Ru layer is not attacked by the UV exposure, and removed by the subsequent wet process in which the products of Ru oxidization are diluted. Above mentioned procedure we intend to identify EUV mask manufacturing conditions, at which the capping layer is not impacted by the clean process. At the end of the manufacturing process, the EUV mask has to have a thick enough capping layer to perform the repair process and protect the ML mirror during the mask lifetime. Currently available processes allow us to manufacture EUV masks with a remaining capping layer up to five times thicker than required for the e-beam mask repair. This result confirms readiness of the mask manufacturing process for HVM from perspective of the mask health and integrity of the ML mirror and Ru capping layer.

With shrinkage of device pattern, optical proximity correction (OPC) will be used for EUV lithography, which leads to need sub resolution assist features (SRAF) on EUV mask. Currently, it is difficult to fabricate EUV mask with SRAF of sub-30nm using conventional resist mask process stably. Moreover, it is necessary to improve line width roughness (LWR) of mask absorber pattern for achieving the lithographic specifications beyond hp15nm patterning. In this paper, in order to meet the requirements of Ta based absorber EUV mask with SRAF, mask fabrication process using new structure blank is studied for sub-30nm SRAF patterning and for improved LWR of primary feature. New mask process using new blank with thinner resist and Cr based hard mask was developed. By using new mask process, resolution of absorber pattern was achieved to 30nm for SRAF patterning, and LWR was improved comparing with conventional process.

Multilayer defects (ML-defects) are the most specific type of defects on a mask for extreme ultraviolet (EUV) lithography. The intent of this paper has been to study the practical limits of the pattern shift technique to cover such defects by the absorber pattern. We have targeted to apply pattern shift to a 16nm half-pitch EUV single exposure, interconnect-like layer, in which absorber features are predominantly as small as 64nm at mask level. Three main contributors to successful defect coverage are the lateral size of the defect, the alignment of the mask pattern to the fiducial marks and the location accuracy of the blank defects relative to these fiducial marks. For our experimental analysis, we have used a specific approach in which, rather than explicitly targeting to cover the defects to render them non-printing, we kept the possibility to study their printability, together with the possibility to assess the achieved alignment of the mask pattern to the defectivity map of the blank. This was achieved by superimposing a dedicated marker frame, with the expected defect position at its center, onto a lines-and-spaces (l/s) pattern with 16nm half-pitch (at wafer scale). The marker frame allows to determine the deviation of the defect position from the expected one, and the printing impact of the defect on the l/s pattern can be compared to its expected behavior based on its relative position within the 32nm period. It is shown that mitigation feasibility is strongly dependent on the accuracy of the defect position information. Our results suggest targeting to improve that.

In this study, we fabricated a closed type EUV pellicle without any gaps by using the mask adhesive, forming the vent holes in the Si border part and putting the sufficiently wide area filters on the top side of Si border. Ventilation performance of closed EUV pellicle was examined during pumping and ventilation condition. As the result, we found that the closed EUV pellicle has enough ventilation performance under the practical pumping down condition. Furthermore, as for EUV pellicle, contamination growth on mask surface during EUV exposure should be suppressed. We fabricated EUV pellicle with coated adhesive as the mask adhesive to suppress the outgas generation which causes the contamination on mask during EUV exposure. EUV irradiation was performed to the base plate which has similar component of the EUV mask surface inside the pellicle space. Contamination growth was not observed for the sample with coated adhesive, but observed for the sample with general adhesive as mask adhesive. Coated adhesives for mask adhesive of EUV pellicle, which keep the adhesive properties, will be suitable for fixing method to suppress the mask contamination during EUV exposure.

As technical advances continue, the pattern size of semiconductor circuit has been shrunk. Defect control becomes tighter due to decrease in defect size that affects the image printed on the wafer. It is critical to the photomask which contained considerably shrunk circuit and ultra high density pattern for sub – 20nm tech device. Therefore particle source from all processes should be controlled extremely. Especially for dry etching process, Yttrium oxide (Y₂O₃) has been widely used for plasma resistance protective material such as lower electrode cover plate and inductively coupled plasma insulator. However, Y₂O₃ showed highest erosion rates under Cl₂ plasma condition [1], shorten protective lifetime. Therefore, selection of ceramic material must be important for particle control in dry etch process.

In this paper, we introduce Y₂O₃ coating film fluorination after plasma treatment. Y-F and Y-O bonding energies change after plasma treatment was observed with X-ray photoelectron spectroscopy (XPS). Expect fluorinated surface can prolong protective lifetime in Cl₂ plasma condition.

The number of masks required to produce an integrated circuit has increased tremendously over the past years. The main reason for this is that a single layer mask exposure and etch was no longer sufficient to meet the required pattern density. A solution was found in the application of multi-patterning steps, including multiple masks, before the final pattern is transferred into the underlying substrate. Consequently, the mask-to-mask contribution as part of the overall on-product (intra-layer) overlay budget could not be neglected anymore. While the tight on-product overlay specifications (< 3-nm) were initially only requested for the intra-layer (e.g. multi Litho Etch Litho Etch) overlay performance, recently these tight requirements are also imposed for the layer-to-layer overlay. Recently, we reported on an extensive study in which the mask-to-mask overlay contribution as determined by the PROVE mask registration tool was correlated with actual on-wafer measurements. Two ASML BMMO (Baseliner Matched Machine Overlay) masks were used for this purpose. Initially, no pellicles were mounted onto the masks. An excellent correlation was found between the measurements on the PROVE tool and the on-wafer results reaching R² < 0.96 with an accuracy of 0.58-nm. The accuracy level can be further improved since all underlying contributors were identified. It was concluded that the expected overlay as measured on-wafer can be fully determined by off-line registration measurements only. An important note is that the off-line registration measurements on the PROVE tool are performed in a static mode, while the exposures on an ASML TWINSCANTM are performed in a dynamic (scanning) mode. No impact was observed since both masks were not equipped with a pellicle. One can expect that also for the case where both masks are equipped with a pellicle of the same type, the impact is negligible. The reason for this is that all pellicle induced errors are likely to be the same for both masks in scanning mode and will cancel out in the overlay. However, the correlation between offline mask-to-mask overlay measurements and on-wafer measurements is expected to deteriorate when only one of the masks is equipped with a pellicle. Evidence for this was already found even when we operated the scanner in slow scan mode. In this work, we have extended the study by considering the impact of a pellicle on one of the masks and how it affects the intra-field overlay. As a logical consequence, it will have an impact on the correlation between the mask-to-mask and the on-wafer overlay measurements. An experimental technique has been developed to isolate the main impact of a scanning pellicle. We show that, in addition to the mask-to-mask writing errors, the pellicle induced errors can be characterized as well. We demonstrate that the correlation is restored when the pellicle contribution is removed from the on-wafer overlay measurements. The impact of the pellicle on the intra-field overlay performance should be treated as a separate overlay contributor that needs to be minimized separately. Calibration and scanner correction capabilities are in place to mitigate the pellicle induced overlay errors.

In this paper we combined the hotspot pattern library and the rule-based scoring system into a modularized hotspot-checking rule deck running on an automatic flow. Several DFM (design for manufacture) properties criteria will be defined to build a “score board” for hotspot candidates. When hotspots in the input design are highlighted, the scoring system can identify whether a hotspot is a high risk hotspot or not, and define the severity of the hotspots by extracted DFM properties. The automatic flow will detect which layers are contained in the design then generate a modular rule deck with several corresponding hotspot check modules. The flow also takes snapshots of the high risk hotspots according to the score board automatically. After all the essential hotspot data is collected, the flow will automatically create an HTML-format report which has histograms of properties and overview graph that shows the distribution of hotspots. The aforementioned HTML report containing scored DFM properties and snapshots can help result-viewers to identify the high risk hotspots on the design quickly; namely, users can examine hotspots by snapshots without loading the whole design into layout viewer tools. By comparing the hotspot checking result with real defects from wafer data, a true hotspot’s values of DFM properties can be obtained. We believe this is helpful for users to improve their hotspot rules in accuracy.

As EUV lithography moves towards high-volume manufacturing, standardized commercial EUV masks are becoming available. The overlay requirements for the technology nodes utilizing EUV lithography are very tight, therefore reliable and accurate reticle registration metrology—on target and especially on-device areas—is of great importance. We report investigations using the latest generation LMS IPRO system for reticle pattern placement measurements on EUV masks. High performance metrology is based on excellent optical imaging capabilities and consideration of the reticle optical properties for EUV mask-specific measurement setup. This enables highaccuracy, model-based measurement on the device. The die-to-database algorithm is optimized with respect to the mask pattern properties of EUV masks. Repeatability and accuracy results are presented. The cost effectiveness of LMS IPRO is demonstrated by comparing results of high-performance and high-throughput modes.

EUV lithography is expected to be the most promising technology for semiconductor device manufacturing of the 7nm node and beyond. The EUV mask is a key element in the lithographic scanner optical path. The image border is a pattern free dark area around the die on the photomask serving as transition area between the parts of the mask that is shielded from the exposure light by the Reticle Masking (REMA) blades and the die. When printing a die at dense spacing on an EUV scanner, the reflection from the image border overlaps edges of neighboring dies, affecting CD and contrast in this area. This is related to the fact that EUV absorber stack reflects 1-3% of actinic EUV light. To reduce this effect several types of image border with reduced EUV light reflectance (<0.05%) have been proposed; such an image border is referred to as a black border (BB). In particular, an etched multilayer type black border was developed; it was demonstrated that CD impact at the edge of a die is strongly reduced with this type of the black border. However, wafer printing result still showed some CD change in the die influenced by the black border reflection. It was proven that the CD change was caused by DUV Out Of Band (OOB) light which is emitted from the EUV light source. In our previous study, a new types of multilayer etched BB called ‘Hybrid Black Border’ (HBB) had been developed and showed a good potential for DUV light suppression. OOB light reflection on HBB is ~3x lower than that of normal BB. Imaging performance was also demonstrated on NXE:3300 scanner system for N10 imaging structures of 16nm dense lines and 20nm isolated spaces. These results were compared to the imaging results obtained for a mask with the normal BB and 3x improvement was achieved; less than 0.2 nm CD changes were observed in the corners of the die. However, OOB light reflectance suppression was still not enough in short wavelength. In this study, we focused on OOB light reflectance reduction in short wavelength, and we developed a new HBB called ‘Advanced HBB’. We measured the OOB light reflectance of Advanced HBB by synchrotron radiation facility at PTB (Physikalisch- Technische Bundesanstalt, Germany). These results were compared to the results obtained from previous HBB. Then Advanced HBB achieved over 50% OOB light reflectance improvement in average wavelength 100nm to 270nm. Imaging performance also simulated in the edges and corners of the die. The CD-drop is expected to be more improved for Advanced HBB than previous HBB. As a result, it is expected the implementation of the Advanced HBB will help to mitigate the effects of possible increases of OOB light in the future higher power EUV sources.

p-Chloro-α-methylstyrene (PCMS) has the chemical structure as the chlorine atom is introduced in phenyl group of α- methylstyrene (MS). In the present study, we synthesized a ternary copolymer consisted with methyl-α-chloroacrylate (ACM), PCMS and MS having the composition ratio of 53:16:31 with the averaged molecular weight (Mw) of 370k, in order to improve sensitivity while maintaining the same resolution as conventional ACM-MS resist. ACM-MS resist having the composition ratio of 46:54 with Mw of 290k is also synthesized to compare exposure characteristics. Firstly, solubility of ACM-PCMS-MS resist without the electron beam exposure for ester solvents is investigated. The dissolving rate of ACM-PCMS-MS resist for amyl solvent is markedly lower compared with ACM-PCMS resist having the composition ratio of 49:51 with Mw=30k reported before, which also includes the effect of the larger molecular weight. Sensitivity curves are made and line and space (L/S) patterns down to 20/20 nm (design value) are formed by using an electron beam writing system with an acceleration voltage of 50 kV. The 20/20 nm L/S pattern is successfully formed in ACM-PCMS-MS resist as well as ACM-MS resist. No significant difference between ACM-PCMS-MS resist and ACMMS resist is observed in L/S pattern shapes. The exposure doses required for pattern fabrication are larger in all L/S patterns compared to ACM-MS resist, reflecting sensitivity curves of them. The dry etching resistance of ACM-PCMSMS resist is also presented.