This PDF file contains the front matter associated with SPIE Proceedings Volume 11148, including the Title Page, Copyright information, Table of Contents, Author and Conference Committee lists.

Cities of the future will be founded on the transmission of data between various intelligent systems, including the design, manufacturing, and deployment of autonomous vehicles. As automotive companies transition from building and selling cars to offering mobility services, integrated solutions for information technology, product lifecycle management, and various engineering domains will be critical to success. Among these engineering domains, the development of advanced system-on-chip (SoC) devices will be especially crucial to the success of autonomous vehicles. Autonomous vehicles demand bespoke SoC devices that are optimized for the specific challenges of automated driving. Legacy automotive manufacturers, automotive suppliers, and new entrants developing autonomous vehicles will need to adopt a cross-domain approach to semiconductor development that enables early verification and validation of SoCs within the context of an autonomous vehicle. Integrating such a portfolio into a digital automotive enterprise will enable companies as they strive to realize the potential of new mobility technologies.

Captive and merchant mask makers participated in an anonymous survey in the summer of 2019 to capture the profile of the mask industry for the period of July 2018 through June 2019. The eBeam Initiative’s fifth Mask Makers’ Survey in 2019 covers a number of questions related to the profile of the mask industry, from overall number of masks to pattern generation type. The survey respondents – 11 different captive and merchant photomask manufacturers versus those who participated in last year’s survey – reported 599,536 masks this year. Respondents reported that eBeam variable shaped beam (VSB) wrote 30% of the masks they produced this past year with an average VSB mask write time of 8.64 hours. The use of Multi-beam mask writing was affirmed in this year’s survey results. Overall mask yields remain steady at around 94% and EUV mask yield was reported at 74%. The eBeam Initiative also conducts an annual Perceptions Survey of mask industry luminaries which can be found at www.ebeam.org.

The bulk of photomask demand is in technology nodes ≥65nm, using equipment, processes, and materials developed more than two decades ago1. Despite mature processes and tools, mask makers are challenged to meet continuing demand. The challenge comes not only in the forms of increased demand, but also that much of the equipment is approaching the end of its viable lifetime to support and maintain due to parts or expertise availability2. Mask writers in particular are problematic from a technical and financial perspective. Modern equipment and processes can be “too good” to simply use as a direct substitute when original equipment or processes become unavailable During initial lithography and device integration, device manufacturers tailored Optical Proximity Correction (OPC) and other wafer processing conditions based on the original mask signature for multiple mask layers. Changing to state-of-the-art mask fidelity would actually represent a liability, as the altered mask character could result in device shifts, yield reduction, or even unanticipated reliability failures. To account for the improved fidelity, re-optimization of the synergistic patterning between mask, wafer lithography and etch is required. Even on mature technologies, reintegration can require costly, difficult, and time-consuming requalification. While this path has often been pursued when manufacturers declare EOL of tools, we propose instead to contain the change in the mask shop by using Mask Process Corrections (MPC)3. Instead of using MPC to maximize mask fidelity, as is done in advanced nodes, we use MPC to replicate the original mask non-idealities on a new mask process.

While laser mask pattern generators (MPGs) continue to serve the application spaces for legacy-node chip production and second-level writing for advanced masks, they also capture some masks with large data volumes resulting from optical proximity corrections. To improve throughput and print performance for these masks, a software-based data path has been implemented on the ALTA multi-beam MPG platform. Running on a multicore architecture, the new data path provides more than an order of magnitude increase in processing speed for data preparation and rasterization compared to the existing hardware solution. The programs performing the data preparation and rasterization, along with the general-purpose computers on which they run, are referred to as the raster engine (RE). The RE accepts MEBES, OASIS, and GDSII formats, optimizes the data on a 0.1-nm grid, and applies both system and user-defined critical dimension (CD) corrections prior to printing. During mask printing, the prepared data are rasterized out to a 0.5-nm writing grid while applying additional corrections required by the ALTA architecture. A beam engine (BE) converts the rasterized data to radio frequency (RF) signals that drive the 32-channel acousto-optical modulator. The edge-placement resolution in the scan direction is controlled using timing, whereas the stripe-axis resolution is achieved using fixed beam spacing with 80 gray intensity levels. Significant improvements are observed in the scan-axis print performance and the consistency of corner rounding. This paper also examines the effects of the number of passes used in multi-pass printing on the tradeoff between print quality and mask write times. Finally, the capability to align to the fiducials defined by the SEMI P48 standard for EUV masks has been added to the ALTA system.

Deep learning has an increasing impact on our personal and professional lives. Deep learning has the potential to transform mask, semiconductor and electronics manufacturing. This paper reviews key results from the Center for Deep Learning in Electronics Manufacturing’s (CDLe’s) first year of operation. We consider results from adapting five common types of deep learning recipes to solve key challenges in the manufacture of photomasks, printed circuit boards (PCBs), and flat panel displays (FPDs). These deep learning applications include 1) grouping similar items to automatically categorize mask rule errors; 2) using U-Net architecture to construct fast mask designs; 3) using vision-based object classification to find and classify pick-and-place (PnP) errors on PCB assembly lines; 4) using anomaly detection to improve the quality of FPDs; and 5) using digital twins to create SEM images and optimize Inverse Lithography Technology (ILT). While we compare the relative benefits of these techniques, all show the importance of data to improve the success of deep learning networks and of electronics manufacturing. These applications rely on varying neural network architectures such as autoencoders, segmentation networks, deep convolutional networks, anomaly detection, and generative adversarial networks (GANs).

Deriving models for lithographic masks based either on first principles or using an empirical model is becoming increasingly challenging as complex effects (once relegated to noise level) become more relevant. Deep Learning offers an alternative solution that can leapfrog the shortcomings of these previous approaches but requires a source of input data that contains enough diversity to allow an effective training of the neural networks. The solution for mask lithography modeling presented in this paper makes use of carefully calibrated SEM images to extract the information required to allow the training and testing of a deep convolutional neural network that achieves accuracy beyond what can be done in metrology-based methods. We demonstrate how the input data is calibrated to be consumed in this flow and present examples demonstrating its predicting power which can, for instance, detect the location and shape of hotspots in the layout. One significant additional advantage is the improvement in the ease and speed of building models compared to previous solutions which can dovetail well with regular production flows and can be adapted to dynamic changes in the mask process.

Deep learning (DL) is one of the fastest-growing fields in artificial intelligence (AI). While still in its early stages of adoption, DL has already shown it has the potential to make significant changes to the lithography and photomask industries through the automation or optimization of equipment and processes. The key element required for application of DL techniques to any process is a large volume of data to adequately train the DL neural networks. The accuracy of the classification or prediction of any DL system is dependent on the depth and breadth of the training data to which it is exposed. For semiconductor manufacturing, finding adequate data – especially for corner cases – can be difficult and/or expensive. In this paper, we will present two digital twins that are themselves built from DL as a part of a DL Starter Kit. We will demonstrate the creation of DL-based digital twins for a mask scanning electron microscope (SEM) and for curvilinear inverse lithography technology (ILT).

With semiconductor technology approaching and exceeding 10 nm design rules the quality requirements for photomasks are continuously tightening. One of the crucial parameters is improved control of the critical dimension (CD) across the photomask. As long as linearity and through pitch effects are not involved, the quality measure is typically defined as CD uniformity. This parameter is normally measured on repeating structures of same size and shape, which are not necessarily placed in identical environments. Density dependent process effects, also called loading effects (LE), pose a challenge for the required CD control. There are several possible contributors to this kind of error within the mask manufacturing flow, such as etch driven loading effects, fogging effects during 50kV exposure and develop driven loading effects. All of these operate at different working ranges, starting at millimeters going down to only a few 100 μm scale. It is comparably easy to derive models for large scale phenomena like etch loading or fogging effects, in contrast to that it is not as straight forward to find suitable models for very short-range effects. A large amount of CD measurements taken by CD SEM is needed to identify such signals of low magnitude and short scales, which make the setup very resource intensive. Furthermore, this methodology requires artificial designs and test structures which aim to sample only the effect of interest. In this paper we present a strategy which combines CD SEM measurements from dedicated test masks with the results from regular product masks. The aim is the derivation and validation of the loading effect correction range and strength. In the first step the data from test masks is analyzed to set up the basic correction parameters. Following this, the approach is supplemented by product data where we combine mask CD and design data. The clear field distribution of the design is convoluted with respect to a hierarchy of length scales. This data is the input for a support vector machine analysis. Thus, we employ a flat machine learning algorithm. However, the input data has been set up to reflect multiple layers of convolution. This particular approach has been chosen, as each convolution length scale is associated with mask process properties, thus alleviating the burden of interpretation which typically mars the interpretation of models obtained by machine learning approaches.

Data technology for data handling, correction, and verification has become the essential technology of photomask. By the shrinkage of device pitch and the development of lithography technology, the data volume of photomask has been increased continuously and the correction and verification technology based on design data has an important role to meet the target of patterning quality. Especially, because EUV lithography makes single patterning possible, the decrease of device pitch rises to the challenge on the data technology for EUV photomask. Furthermore, the multi-beam mask writer which enables dose modulation for each pixel requires fundamental changes such as data format, data flow, and correction algorithm. Here, we will discuss about 7 kinds of data technologies and one proposal for the era of EUV lithography.

This work presents our investigations on a new resist-slope kernel for Mask Process Correction (MPC) applications, specifically modeling the contribution (including linear and higher-order) of the resist image slope to the overall etch bias. Mask Process Correction (MPC) models with different complexities, i.e., varying number of kernels, were calibrated and compared against each other for model accuracy, layout correction run-time and dose-dependent residual trends. The results demonstrate that using the resist-slope kernel with a simpler model can allow for up to 40 percent lower correction run-time (compared to complex models) without a major degradation of the overall model accuracy. Hence, this paper presents the resist-slope kernel as a valuable addition to MPC modeling techniques, especially for situations where conventional methods are not sufficient to meet the accuracy or run time requirements.

With 193nm optical lithography being extended to 12nm design rules and beyond, quality and performance requirements for photomasks are becoming increasingly challenged to support the increased pattern complexity. Additionally, interactions between mask, the lithography process, and OPC (Optical Proximity Correction) are becoming a more critical tool in tolerance reduction. One of the tools being used to reduce this variation is Mask Process Correction (MPC). Model-based Mask Process Correction (MB-MPC) is one of the key tools used to improve photomask Critical Dimension (CD) uniformity and provide high fidelity, and increase patterning stability of resolution limited features, such as assist features (SRAFs) at today’s leading-edge nodes. Since 2017, participants in the eBeam Initiative Mask Maker Survey have reported that MPC is considered a requirement for 16nm and below. Reduction of systematic photomask CD errors with MPC enables improvement of the accuracy of Optical Proximity Correction models by reducing mismatch between actual and modelled masks. While model-based MPC has been demonstrated to reduce mask fidelity and dimensional errors to sub 1nm on mask, one of the downsides is that it is a slow and resource intensive solution. An advanced model based MPC requires massive numbers of CPUs and their associated EDA licenses. In this paper, we will teach a technique for mitigation by use of a Rule-Based MPC (RB-MPC) solution with MB-MPC accuracy to reduce Mask Data Prep (MDP) runtime with no loss in patterning quality. We report on a full cycle of model to rule-based MPC simplification approaches and verification. We will describe the process by which we have been able to migrate a model-based MPC (MB-MPC) solution to a more cost effective, and equally accurate Rule-based MPC (RB-MPC) solution. This will included the methodology for derivation, implementation, and verification of the modified RB-MPC, which is based on both mask, and wafer performance metrics, and characterization of limitations of this process, as the challenges in converting to a RB-MPC from a MBMPC solution by application, including technology, mask process, target layer, and wafer-performance metrics.

Excursion prevention is one of the key points in the mission of leading edge foundries. In this paper, we concentrate on patterning excursions and how to prevent them. This strategy concentrates pro-actively on the task to minimize the distributions of critical input parameters as much as possible, independently upon a certain pre-defined specification is met or not. In our paper, we will describe this concept by improving intra-field CDU using CD Correction (CDC) by mask tuning. Mask Tuning by the ForTune system uses ultra-short pulse laser technology to locally change the mask transmission, based on the wafer intra-field CDU, and hence improves CDU on wafer (CDC). To ensure a save patterning with a large enough process window without any negative yield or reliability impact, our concept looks for the tail of the final CD distribution instead of traditional 3-sigma numbers. By using a calibrated 3D resist model, we simulate the wafer CD distribution under all combinations of the Litho input parameter distributions dose, focus and mask CDU. As a result of the simulation, we get thousands of CD-results. The tail of that CD distribution still needs to be larger than the minimum CD needed for a safe etch transfer. Based on our simulation data we can calculate patterning failure probabilities and thus expected yield loss for the different patterning cases, including systematic process deviations (mask, dose, focus). At the final step, we will show in detail how the pro-active optimization of intra-field CDU by Mask Tuning using the ForTune CDC process will give us more patterning margin and thus will reduce the failure probability dramatically. The calculated yield loss for the worst scenario (focus and dose offset additionally to the mask signature) will be reduced from several percentages close to zero.

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In this work, we review progress on pattern capability, throughput, mask life and overlay. To minimize distortion and improve overlay, a Drop Pattern Compensation (DPC) method has been implemented to minimize the added overlay distortion terms. In this paper we describe the origins of the out of plane errors, and describe the method used to correct these errors along with some examples. Improvements to both cross matched machine overlay (XMMO) and imprint mix and match overlay (IMMO) are presented.

It’s generally said that the management of particles is important. In DUV lithography, it’s needed to remove particles on photomask surface not to induce patterning defects on wafer. Moreover, in Nanoimprint lithography (NIL), particles on template cause not only patterning defects on wafer but also its own pattern collapse. Therefore, these particles have to be entirely removed from substrate surface with cleaning technology. In this paper, we proposed ‘Freeze Cleaning’ which has more than 99% PRE for 40nm SiN standard nanoparticle without pattern collapse and critical dimension (CD) shift. And it was also demonstrated that soft defects on template which remained after conv. cleaning could be removed with Freeze Cleaning. These results predict that Freeze Cleaning will contribute to progress of photomask and template technology to next stage.

Development of a photoresist is a complex physical process involving solid-to-liquid solution phase transition where a developer solution dissolves a section of a patterned resist. The developer can be selective towards either the exposed region (positive-tone) or the unexposed region (negative-tone). Accurate estimation of the development effects is crucial to the prediction of critical dimension (CD) in lithography simulations. Traditionally, the development effects have been captured by a front-propagation equation (such as Mack model and other similar models), which features a development front with a velocity dependent on the resist’s de-protection level. For a positive-tone development (PTD), due to the aqueous nature of the developer, where an exposed part of resist quickly dissolves when in contact with a developer, such a moving front simulates the development process accurately. However, in case of a negative-tone development (NTD), the rate of reaction and resist contrast is significantly lower than for PTD. Therefore it is important to take into account both the developer’s finite diffusion into resist and its reaction rate with the resist to reliably model the development process. In this paper, we discuss the mathematical model of resist’s development by taking into account the transport phenomena of diffusion and reaction taking place during the development step. The finite-element method is used to solve these reaction-diffusion equations over the non-trivial geometry of a patterned resist. We will analyze the results of reaction-diffusion process in comparison to the front propagation methods. The contribution of different model parameters will be described by studying the development rate for resist’s de-protection level and comparing it to the development rate obtained experimentally. We will briefly discuss the results from three dimensional lithographic patterns, which exhibit strong NTD effects.

With the advancement of semiconductor technology beyond 7nm, the speed and accuracy constraints on computational lithography are tightening. As the mask features become smaller and more complex, Inverse Lithography Technology (ILT) is increasingly being considered as a possible OPC solution in order to maximize process win- dow (PW) and improve CD uniformity (CDU). Until recently there has been a limitation on the adoption of curvilinear masks due to their undesirably long mask write times using vector shaped beam (VSB) mask writers, but with the introduction of Multi-beam mask writers (MBMW) in volume photomask production, mask write time is no longer a limiting factor for the usage of curvilinear masks. The key differences between correcting ILT patterns as compared to correcting rectilinear patterns explain the complexity associated with Curvilinear MPC and the corresponding longer convergence time. Continuous efforts have been made by the computational lithography community to employ solutions from the ever evolving machine learning technology. Machine learning based solutions have been proposed for a variety of problems like mask making proximity effect correction, model based OPC, ILT and hot spot detection. An artificial neural network is an information processing system inspired by the biological nervous system in the way the brain processes information. It consists of large number of highly interconnected processing elements (neurons), working together to solve specific problems. It is a powerful data modelling tool that captures complex input/output relationships. In this work we present a neural network based solution which predicts a smart pre-bias for curvilinear features, leading to faster convergence of the correction engine.

Silicon Photonics design layouts require use of curved shapes, since many of the structures built to route light through silicon are designed to curve smoothly to minimize the loss of signal strength. The design-to-silicon flow involves steps like Design Rule Checking (DRC), Optical Proximity Correction (OPC), Mask Rule Checking (MRC), Mask Process Correction (MPC), mask data fracture, mask writing and mask inspection. All of these steps involve software and techniques that have evolved over decades of use for predominately orthogonal design geometries composed of vertical and horizontal edges. In many cases, these tools and process steps will perform poorly or fail if they are used on free form curvilinear layouts – unless changes are made to accommodate the curvilinear designs. In this paper, we describe challenges in various steps of the design-to-silicon flow associated with supporting curvilinear photonics design layouts. We first present two flow alternatives, which we call “manhattanization” and “free form”. The manhattanization flow is where angles or curved layout edges are converted to short vertical and horizontal fragments closely matching the design intent. The advantage of the manhattan approach is that DRC, OPC, MRC and MPC decks designed for use on orthogonal CMOS designs can be used on photonics content that has been manhattanized. We present examples of layouts where the manhattan approach causes problems in several phases of the tapeout flow. We also present an example of a free form tape out flow, with particular focus on the unique challenges faced in correcting for different wafer processing steps in the OPC recipes. We also discuss some of the existing literature offering ideas on how to best manage free form layouts in OPC and mask data preparation. Ultimately, the goal of these data operations is to enable creation of a photomask for use as a master template in the chip production; since these mask writers almost exclusively operate with rectilinear data, the designs must ultimately be Manhattanized. We will explore the benefits, challenges, and drawbacks to manhattanizaiton specifically during mask making as well. The latter portion of the paper presents some of the challenges faced in mask making for free form photonics designs. We discuss the role that MPC plays in photonics mask production, where many features are sufficiently large to make MPC unnecessary, and we look some examples of more advanced photonics designs where MPC may need to play a role. We explain the challenges in trying to define and enforce MRC rules on curvilinear content to ensure mask inspectability and manufacturability. We describe the design and use of a programmed defect inspection test mask designed to formulate some simple MRC rules for free form mask designs. We demonstrate the linkage between curvilinear DRC and MRC, as the techniques and challenges faced in both areas are very similar. We also explore the relationship between the manhattanization and mask operational and performance metrics, such as data volume, write time, image fidelity, and design intent fidelity when going from manhattanized mask shapes to free form mask shapes for photonics layouts.

We have recently demonstrated that curvilinear shapes and multi-beam mask writing are necessary to minimize the impact of mask variability on wafer hotspots. Several key challenges and opportunities remain. We ask how we update mask-inspection rules, and how we correct for mask-process systematics for extreme ultraviolet (EUV), where the optical response must be taken into account. This paper proposes updated mask rule checks (MRC), derived from a mask variability perspective. We also demonstrate the need for MRC-aware inverse lithography technology (ILT) metrics as a pre-requisite to ensure the reticle shapes are what the wafer-side lithographer desires. Armed with a fully curvilinear ILT and mask data preparation (MDP) system, there is an opportunity to relax the restrictions on fully Manhattan designs where possible.

In advanced semiconductor memory manufacturing, mask and lithography are critical for patterning. In this paper we jointly study the benefits of a mask and wafer co-design that utilizes a new extreme single instruction multiple data (SIMD) approach to computing. Wafer results will be shown demonstrating the benefits of the approach. Unlike traditional EDA software that runs on customers’ computer farm, this new approach leverages and maximizes GPU acceleration. In this study, software speed and quality, mask writing strategy, wafer pattern fidelity and process window are examined and analyzed. Inverse lithography technology (ILT) has been seen as a promising solution to many of the challenges of advanced-node lithography, whether optical or EUV. However, the runtimes associated with this computational technique have limited its practical application. Until now, it has been used for critical “hotspots” on chips, but has not been used for entire chips. The solution to the runtime problem for ILT has been particularly vexing, as the traditional approach to runtime improvement – partitioning and stitching – has failed to produce satisfactory results, either in terms of runtime or in terms of quality. D2S has adopted an entirely new, stitchless approach, creating a holistically conceived, purpose-built system for ILT, This system includes a unique GPU-accelerated approach that emulates a single, giant GPU/CPU pair that can compute an entire full-chip ILT solution at once. This novel approach, systematically designed for ILT and GPU acceleration, makes full-chip ILT a practical reality in production for the first time. For the most advanced DRAM manufacturing using 193nm immersion lithography, every aspect of design, mask, and lithography, including quality of the process, accuracy, and turn-around-time, need to be optimized. Any new technique that significantly improve one or more elements of such complete process are welcome. Recently a number of new technologies, such as multi-beam mask writer, GPU accelerated computing for mask and wafer, are emerged and are reshaping the mask and lithography. This new stitchless full chip curvilinear ILT is applied to memory chip making. We will show mask making and wafer print results, including pattern fidelity and process window, to show the actual benefits of such technologies for semiconductor manufacturing.

Extreme ultraviolet (EUV) lithography is entering high volume manufacturing, and these lithography tools are expected to be the enabling technology for reaching the next several lithography nodes. With each successive node, features will continue to shrink following Moore’s law, and the relative error contributions from flatness-related topographies will increase. Photomask blank manufacturers are responding to increasingly challenging flatness specifications with more dynamic methods to mitigate any non-flat surface characteristics and thus their contribution to the final on-wafer error. Such methods include iterative dynamic polishing, write compensation, and scanner-related corrections, all of which utilize high-resolution interferometric measurements to provide feedback on the reticle's shape, which in turn can be used to calculate the reticle's contribution to overlay and image placement at wafer. As the industry progresses through each node, these flatness requirements restrict to a point where the production of photomask blanks is extremely challenging to achieve, requiring reticles with single-digit nanometer (peak to valley) flatness. The challenges associated with producing blanks to this level drive up production time and product costs. To alleviate some of these constraints, ASML has recommended the use of four functional, reticle flatness key performance indicators (KPIs), which characterize a blank’s contributions to the overall process window, including any relief provided by in-scanner correction methods, and allow for a straight-forward framework to identify which geographic features are “passable” and which are "prohibitive" to the ultimate overall system requirements. The calculation and application of the KPIs take into consideration numerous factors of the reticle's production and use, including their topographic features, the chucking mechanism used in the scanner, and the illumination of the scanner to best simulate the final on-wafer results. Previous publications explored the application of these KPIs to representative reticle data sets, both physical and simulated, using the architecture of the ASML NXE:3400 EUV platform, and explored what level of relief they may provide for reticle flatness requirements. In this paper, we again explore the application of ASML’s KPIs, now using the next generation 0.55 NA EUV scanner architecture, the ASML EXE:5000, to ascertain what level of relief or complexity may be required of blank polishers in order to meet the process window requirements of future nodes. In this fashion, we are then able to determine what general flatness-related guiding principles will be required for next generation blanks, and whether these principles will require additional process development or innovation.

As extreme ultraviolet (EUV) lithography enters high volume manufacturing, the semiconductor industry has considered a lithography-wavelength-matched actinic patterned mask inspection (APMI) tool to be a major remaining EUV mask infrastructure gap. Now, an actinic patterned mask inspection system has been developed to fill this gap. Combining experience gained from developing and commercializing the 13.5nm wavelength actinic blank inspection (ABI) system with decades of deep ultraviolet (DUV) patterned mask defect inspection system manufacturing, we have introduced the world’s first high-sensitivity actinic patterned mask inspection and review system, the ACTIS A150 (ACTinic Inspection System). Producing this APMI system required developing and implementing new technologies including a high-intensity EUV source and high-numerical aperture EUV optics. The APMI system achieves extremely high sensitivity to defects because of its high-resolution, low noise imaging. It has demonstrated a capability to detect mask defects having an estimated lithographic impact of 10% CD deviation on the printed wafer.

Deep Ultra Violet (DUV) inspection of Extreme Ultra Violet (EUV) mask has been known for high stability, high throughput, and low cost, since it has been used for a long time, even though sensitivity is thought to be insufficient for the EUV mask of under 20 nm half pitch (hp). We have been studying extendibility for 1X nm hp of the DUV inspection using optics named Super Inspection Resolution Improvement method for UnreSolved pattern (SIRIUS). In previous study, we demonstrated the DUV inspection has capability for the EUV mask of 17 nm hp Lines and Spaces (LS) on wafer. In this paper, the more extendibility for the DUV inspection of EUV masks under sub-15 nm on wafer was demonstrated by studying relationship of roughness and sensitivity. Firstly, an estimated model for effects of the EUV mask roughness to Signal Noise Ratio (SNR) of the inspection image was established, and simulation was carried out. Secondly, the SNR was evaluated using actual Line Width Roughness (LWR) improved masks. It was confirmed that the results are the same trend as the model and the simulation, and, the SNR is enhanced with the LWR improvement. Finally, the sensitivity of the LWR improved mask was evaluated. As a result, it becomes enough for the EUV mask over 13 nm hp on wafer. In conclusion, we confirm that the DUV inspection of the EUV mask by the SIRIUS can be extending to the 13 nm hp LS on wafer, this is around the limit of NA 0.33 EUV lithography, using the LWR improved mask.

EUV pellicles have been enabled to provide customers with defect protection for EUV reticles. However, due to the absorption that is much higher than for DUV pellicles, using the pellicle has certain disadvantages. Most significant is the reduction in throughput caused by the absorption of EUV photons in the pellicle. This leads to a customer decision to use a pellicle and accept the reduced throughput, or to not use a pellicle and have additional inspection steps to check the cleanliness of the EUV reticle. These tradeoffs vary by customer and use case. This study addresses the balance of factors for using or not using a pellicle through a cost comparison.

As EUV lithography wafer volumes increase, throughput and yield require more focus. Yield can be enhanced by introducing a pellicle to hold particles out of the focal plane and minimize their impact to imaging. Using a pellicle also minimizes the extra wafer inspections required to ensure that printable mask defects do not increase over time. However, if the associated transmission loss is high, the yield advantage is offset by reduced throughput. The CNT-based pellicle offers the advantage of very high EUV transmission. CNT pellicles have also demonstrated lifetime at 300W EUV scanner power. The challenge is balancing the CNT membrane design in three areas: physical presence/the ability to stop particles, EUV transmission/imaging impact, and lifetime in the scanner/thermal tolerance. Each of these areas will be described along with simulated and experimental data illustrating the value of a CNT-based EUV pellicle solution for the future.

Resolution enhancement technique requirements drive continuously increasing mask pattern complexity which creates an increasingly serious problem of ever longer mask writing times. Shot count is highly correlated to the writing time of VSB writing tools. Therefore shot count management is one proposed direction for practical writing time reduction. Shots may be induced from small features and pattern jogs due to OPC and other factors. Optimizing shot count without compromising pattern quality is required for the optimization solution. An effective shot count management solution is tested in this paper to remove the small-sized shots produced by misaligned vertices on both pattern edges under certain conditions. We demonstrate a post-OPC small shot removal solution with vertex alignment before pattern fracture. The shot optimization induced mask pattern differences are verified in the flow to ensure that they do not violate OPC requirements. As shot counts are reduced by the solution compared with the original pattern, the efficiency of the shot count reduction and writing time savings are evaluated. Meanwhile the pattern quality is also evaluated to ensure no degradation using both a mask level and wafer level check.

It has been demonstrated that the mask-to-mask overlay contribution can be fully characterized by off-line measurements on the PROVE mask registration tool. This characterization includes the impact of the marks that are used for reticle alignment inside the scanner. This is an important aspect since the scanner is blind to the features inside the image field and intra-field adjustments are only based on measurements of the reticle alignment marks. The off-line determined mask-to-mask overlay was compared with the measured on-wafer results and a perfect correlation (R² < 0.96) was found. The residual mismatch was around 0.6-nm, which is 30% of the dedicated chuck overlay performance of the scanner that was used. These results enable feed-forward corrections to the scanner to improve the intra-field overlay performance or to predict the intra-field overlay originating from mask writing errors (computational overlay). We recently extended the work to the layer-to-layer overlay impact by considering the mask writing error of a wafer alignment mark. This wafer alignment mark was exposed in the first layer. Apart from the reticle writing error of the wafer alignment mark itself, the reticle alignment contribution performed on dedicated reticle alignment marks inside the scanner plays an important role as well. The actual position of the selected wafer alignment mark is also impacted by the reticle alignment model corrections at that specific field location. Only when both contributors are considered, the layer-to-layer overlay can be predicted accurately. In this scenario, the layer-to-layer overlay is measured back to the layer in which the alignment marks were defined. This is referred to as the direct alignment use-case. In this paper, we further investigate the direct alignment use-case in relation to the layer-to-layer overlay. Apart from the reticle writing error and the reticle alignment corrections, the actual placement of the wafer alignment mark during exposure can also be affected by other applied corrections. We will present experimental results of the layer-to-layer overlay as function of the applied automated process corrections on the wafer alignment mark location printed in the first layer. It is shown that the wafer alignment sensor impact should be considered as well in the interpretation of the results. We finally present a strategy to control these kinds of overlay errors.

In the advanced technology photomask manufacturing industry, it is challenging to produce defect-free photomasks, especially for the increasingly smaller critical dimension current days . Since the 193nm immersion scanner numerical aperture (1.35) has remained the same as in previous nodes, more mult i-patterning and aggressive source mask optimizat ion illumination sources are being used to print smaller feature crit ical dimensions (CDs) and pitches. To accommodate such specialized sources, more model -based mask OPC and ILT are being used, making mask designs very complicated. This in turn makes mask manufacturing very challenging , especially for the defect inspection, repair, and metrology processes that are used to guarantee defect-free masks. So, it is necessary to develop an application for handling mask defects. In this paper, we introduce a new application called LPR (Lithography Printability Review) to verify any outlier defects or repairs before the mask ships to the wafer fab. The paper details how LPR works in the mask-making flow and how the LPR module is set up. This application has been tightly integrated with KLA’s server and inspectors. The paper concludes with showing the benefits realized in mask making cycle time as a result of implementing LPR into a high volume advanced photomask production line.

As CMOS technology continues to shrink, 2D edge placement errors in lithography can't be ignored especially for some key patterns. The pixel patterns of CMOS image sensor require high lithography fidelity since they will influence the optical properties and electric properties of the device significantly. So the corner rounding effect of pixel patterns should be of special concern. Generally, corner rounding effect in lithography can be compensated by adding serifs at the corner. Serifs can be generated by rule based OPC method or model based OPC method. In this article, a novel model based OPC method to add serifs to corners is introduced. This method first retargets the corners by replacing the corner vertex with a small rectangle placed along 45 degree with the x-y axis. After that, model based OPC is run based on the retargeted patterns. Then we simulate the lithography contour of the corners by commercial OPC software. The geometry of lithography contour is quantitatively evaluated according to the value of corner pullback and the deviation of edge rippling. The relation between the geometry of corner image contour and retarget pattern is investigated. This method has potentials in design of experiment of pixel layout patterns of CMOS image sensors.

We developed novel resist materials and developer with fluorine atoms. Fluorine expected to show higher absorption coefficient than carbon because of its higher atomic number. From QCM, GPC, and SEM evaluation, it was found that ZEP-Y1 and ZEP-Y2 have a potential for next generation resist materials. The combination of resist material including fluorine atoms and fluorine solution is promising. This study showed the possibility of the extension of range for resist materials and developers.

High temperature baking treatment is a method to remove chemical residue on mask before shipping to wafer fab. When developing advanced mask technology, we need to make sure the bake treatment have no side-effect to mask quality. In this investigation, some test has been devised to study the relation between baking process and mask registration, CD movement, repaired point, ion residue and cleaning performance. We also studied how to setup a stable and efficient bake process to make the mask making flow reasonable. The high temperature bake processes was tuned by different temperature, treatment loops setting and was put at different process position to verify the performance. In this paper, OMOG and EAPSM masks were chosen to test by different process condition.

In recent years, as represented by smart phone and head mounted device, high definition displays have been rapidly developed, and the importance of phase shift mask (PSM) to resolve high definition patterns is increasing. However, since the conventional PSM has high reflection characteristic, high reflection of PSM causes large line width distribution due to the influence of the standing wave on the resist pattern, which hinders the formation of high definition patterns. We have developed PSM with low reflectivity by using Cr and MoSi material. It has been confirmed that the developed PSM blanks show significant low reflection characteristics.

Standard cell library is the basic for building blocks and SoC (system on chip). And design in current standard cell library always meets the most critical design rule, leading to tight lithography process window and hotspots easily. Besides, passing design rule check (DRC) cannot fully guarantee manufacturability. Lithography simulation check is an essential check item before tape out. It is significant to qualify the standard cell library at the most possible early stage in order to avoid design rework during the tape-out stage. For 14nm technology and below, hotspots appear both inside cell, abut regions of standard cells and pins for routing. Therefore, our paper puts forward a fast DFM-driven standard cell qualification approach to detect the hotspots inside cell and the potential defects from special kinds of pins and abutting standard cells. It can discover problems early and set constraints for placement and routing as early as possible for a fast product yield ramp-up.

This paper addresses large dies stitching challenges. Stitching is a way to combine several shots "stitched together" to create a die larger than what can fit on a photomask. This technique that was originally dedicated to advanced research is now more widely used and requires a fully automated industrial flow. Technical constraints come from a number of different actors and results must be shared by even more teams. We will present the methodology used to optimize both the yield and the data exchange between cross-functional teams. We will show how this automated flow can be easily customized to save more silicon thanks to advanced dicing techniques.

EUV lithography has enabled shrinking feature sizes up until iN7 using the current Ta-based mask absorber. As we explore next generation nodes, iN5 and beyond, the mask three dimensional (M3D) effects will have a significant impact at wafer level due to the mask architecture, and the oblique illumination angles [1-2]. In order to mitigate these effects, we explore the optical performance of two alternative mask absorber candidates; a High-k absorber and an attenuated phase shifting mask absorber (AttPSM) and compare them to the current Ta-based mask absorber. We evaluate and compare the mask absorbers for memory and logic layers by lithographic source-mask optimization (SMO) using Mentor’s pxSMO tool with ASML’s NXE3400B settings. For memory, contact-holes are simulated using dark-field mask whereas the pillars case is simulated with bright field mask to evaluate bright field as a mask option for EUV with alternative mask absorbers. For logic case, we test these absorbers on iN5 self-aligned block (SAB) layer [3]. The self-aligned block layer is also simulated by adding sub-resolution assist features (SRAFs) to predict the insertion point of SRAFs for logic designs and see if new mask absorber material can reduce the need of SRAF insertion. SMO for memory case shows higher common depth of focus (cDOF) and lower edge placement error (EPE) for High-k absorber over the conventional TaBN mask absorber, whereas significant gain in normalized image log slope (NILS) is observed for the AttPSM absorber. The logic case also has better performance in terms of common depth of focus (cDOF), NILS, EPE mask error enhancement factor (MEEF) and process variation band (PV-band). Adding SRAF’s to iN5 SAB improves the PV-band and image shift through focus for all three cases.

With the advent of Multi-beam mask writers, curvilinear shapes are being realized with comparable metrics to Manhattan shapes when it comes to write times which has been the main issue with conventional VSB mask writers. Techniques like PLDC also enhance Multibeam writing of complex curvilinear patterns. In the past Standard Cell (SDC) design was done with a gear ratio (polypitch/m1pitch) of 1:1. This inadvertently results in congestion on lower layers namely M1 as we try to push the design density. This can be improved by going to a gear ratio of 2/3 by which we derive additional M1 tracks (3 M1 tracks for every 2 poly) but the benefit derived out of a 2/3 gear ratio cell somewhat gets negated with the need for M2 in standard cells where MINT layer doesn’t fully cover M1. To resolve the problem with higher M2 usage in standard cells we can introduce 1.5D or curvilinear routing to make the final/minor routing connections. Here we try to present a study of different challenges and opportunities that arises as a result of introducing curvilinear routing in Standard cells (SDC). In IN5 technology node when we go for a gear ratio (CPP/M1Pitch) of 2/3 we observe that for every standard cell we will need two variants of the cell. These two variants have M1 which are interleaved and shifted. We can live with only one variant of the cell but this inadvertently leaves gaps in between standard cells as the M1 grids will not align when they are abutted. Further study of the impact of the need of two variants reveals that in some standard cells (~9% in IN5) we end up with using M2 for completing the connections. This has many drawbacks (extra routing resources, congestion on M2, increase in area and reduced performance) which negates the benefit derived with 2/3 gear ratio. To fix this problem we have two options. One is to use 1.5D routing and the other to use curvilinear routing. With this approach all the benefits of 2/3 gear ratio can be preserved (improved routing density, area and performance) without the need for M2. A design implementation of the same in IN5 AO22D2 standard cell with CPP of 45nm and M1 pitch of 30nm has been done and the M2 routing (with default approach) has been eliminated. Although this approach has numerous benefits and extended applications (in signal routing) it does present significant challenges when it comes to EDA tools, verification, mask and OPC. We are in the process of evaluating different test cases for design, mask and OPC challenges with curvilinear routing in IN5 SDC. On the design front the challenges include library characterization, PPA and runtime analysis, RC extraction and design verification. On the mask and OPC front some of the challenges include regular versus ILT OPC and their process window comparison, understand the SRAF’s required, mask data volume and MRC. A comprehensive understanding of the challenges and resolution of the same will entail a new scaling paradigm for standard cell designs and also enhance signal routing which in turn has numerous benefits when it comes to PPA.

Atomic Force Microscopes are capable to provide non-destructive high resolution, CD-metrology and precise defect analysis. However, a conventional AFM has not enough throughput for today’s large scale semiconductor manufacturing. The primary point remains the increase of the scanning area in case of large wafers, masks, displays or dies. Cantilever array-based AFMs are intended to increase the imaging throughput by parallelizing the work of many AFM probes that may be practiced by parallel AFM systems that are capable to operate autonomously. An active cantilever scheme makes it possible to sense electronically the deflection and individually to control the actuation of every cantilever in the array. Each cantilever in the array represents a self-sustaining AFM-hardware system for metrology and imaging. In that, the multiple parallel probes are forming many AFMs capable to work independently.

An integration of atomic force microscopy (AFM) and scanning electron microscopy (SEM) within a single system is opening new capabilities for correlative microscopy and tip-induced nanoscale interactions. Here, the performance of an AFM-integration into a high resolution scanning electron microscope and focused ion beam (FIB) system for nanoscale characterization and nanofabrication is presented. Combining the six-axis degree of freedom (DOF) of the AFM system with the DOF of the SEM stage system, the total number of independent degree of freedom of the configuration becomes eleven. The AFM system is using piezoresistive thermomechanically transduced cantilevers (active cantilevers). The AFM integrated into SEM is using active cantilevers that can characterize and generate nanostructures all in situ without the need to break vacuum or contaminate the sample. The developed AFM-integration is described and its performance is demonstrated. The benefit of the active cantilever prevents the use of heavy and complex optical cantilever detection technique and makes the AFM integration into a SEM very simple and convenient. Results from combined examinations applying fast AFM-methods and SEM-image fusion, AFM-SEM combined metrology verification, and tip-based nanofabrication are shown. Simultaneous operation of SEM and AFM provides a fast navigation combined with sub-nm topographic image acquisition. The combination of two or more different types of techniques like SEM, energy dispersive x-ray spectroscopy, and AFM is called correlative microscopy because analytical information from the same place of the sample can be obtained and correlated [1]. We introduced to the SEM/FIB tool correlative nanofabrication methods like field-emission scanning probe lithography, tip-based electron beam induced deposition, and nanomachining/nanoidentation.

193nm mask inspection will remain a viable solution for inspection of ArF technology masks for the 7nm/5nm technology node and beyond, even in the era of EUV lithography. In the ArF technology, pitch multiplication (SADP, SAQP, etc.) will continue to be used along with aggressive OPCs to achieve scaling. Although no major technology inflection is seen, mask capacities will continue to grow until EUV will be fully inserted into mass production. As a result, mask inspection sensitivity and defect dispositioning will remain a gating factor. Moreover, mask metrology will become a critical factor in wafer fabrication and process control. In this paper, the mask inspection challenges for 7nm/5nm and beyond are described and suggested solutions are outlined. One of the main challenges in mask pattern inspection is reducing false defects by filtering the additive white Gaussian noise (AWGN) added to the pattern image (e.g. shot-noise). Common solutions for reducing AWGN are: creating multi reference (such as ‘cell to cell’ and ‘die to many dies’) and spatial averaging (such as ‘matched filter’). However, extra sensitivity is needed at 7nm/5nm technology inspection where defect signal is very weak and close to the noise level. We propose the ‘Multi-Shot’ method as a solution for this problem. ’Multi Shot’ is based on multiple acquisitions and inspections of every location in the mask. The ‘Multi-Shot’ information is exploited through the entire detection flow, taking advantage of information that cannot be used independently such as: defect polarity (random noise does not retain polarity over multiple instances while real defects do), averaged signal and defect rank (local SNR). The added throughput impact of the ‘Multi-Shot’ approach is negligible due to pixel-size optimization. Theoretical framework predicts a ~30% sensitivity (SNR) increase by this method over current approaches, corroborated by experimental data testing. Another significant inspection challenge is the difference between defect measurement methods. The captive mask shops, the merchants and wafer FABs all are interested in the amount of edge dispositioning caused by the defects, measured in units of nm, while traditionally the inspection output is defined by pattern intensity changes due to the defect, measured in grey level units. Translation from intensity to edge dispositioning requires two conditions: The first- applying an Aerial imaging with exact exposure conditions which enables correct dispositioning assessment; and the second- estimating a gray level threshold (print threshold) to be used to convert an Aerial image to a binary printing image (as an equivalent to the resist threshold used in wafer fabrication). Defect dispositioning measurement enables nuisance filtering (by ignoring non-printing defects and defects with very small dispositioning values even if they have high intensity values). The innovation of the solution described in this paper is the integration of metrology and inspection to provide robust detection solutions. 193nm wavelength inspection will continue to be a critical factor in mask manufacturing as well as one of the strongest candidates available today for the initial EUV mask inspection approach. In this aspect we are working to implement ArF new development for future EUV mask inspections.

Design weak points, or “hotspots” remain a leading issue in advanced lithography. These often lead to unexpected critical dimension (CD) behavior, degradation of process window and ultimately impact wafer yield. Industry technology development focus on hotspot detection has included full chip lithography simulation and machine learning-based hotspot analysis. Most recently, the machine learning approach is gaining attention because it is faster and more practical than lithography simulation-based hotspot detection. The machine learning case is a feedback approach based on previous known design hotspots. Conversely, the simulation method has the benefit of proactively detecting hotspots in a new design regardless of historical data. However, full chip simulation requires resources in calculating time, computing power and additional time-to-market that render it impractical in some scenarios. As design rules shrink, advanced mask designs have significantly increased in complexity due to Resolution Enhancement Techniques (RET) such as Source Mask Optimization (SMO), advanced Optical Proximity Correction (OPC) and high transmission attenuating mask films. This complicates hotspot detection by existing OPC verification tools or rigorous lithographic simulation with wafer resist model. These resultant complex mask geometries make OPC optimization and hotspot detection using post design very difficult. In this paper, we will demonstrate the limitation of traditional hotspot detection technology. Typical OPC tools use simple techniques such as single Gaussian approximations on the design, such as corner rounding, to take the mask process impact to the geometry into account. We will introduce a practical lithography hotspot identification method using mask process model. Mask model-based hotspot detection will be used to precisely identify lithography hotspots and will provide the information needed to improve hotspots’ lithographic performance.

In this paper we perform a foundational study on the impact of quartz etched depth, and optical density (OD) of mask opaque area, the 3D effect in ArF immersion lithography at advanced process node. The after development inspection (ADI) critical dimension (CD) variation may be caused by these 2 mentioned factors on the photomask, even the mask CD value of the measurement point is the same. Different cleaners and etchers which fix the same cleaning and etching time, induce different OD of reticle opaque patterns and several quartz etched depths. The relations between OD of reticle opaque patterns / quartz etched depth and ADI CD are the significant subject for successful pilot run which may moderate pilot run time and reduce rework costs in the lithography process. The focus of this study is the characterization of the correlation between OD of reticle opaque patterns / etched quartz depths and ADI CD. We experimentally study the structures from the theoretical introduction on the mask 3D phenomena, all of results are obtained using a MoSi binary ArF blank. A comprehensive wafer CD measurement result will be demonstrated in different OD of reticle opaque patterns and etched quartz depth, both simulation and experimentally based. The effect of fabricating the photomask quartz trenches will also be studied as well as the impact on through pitch CD and exposure latitude. The goal of this study is the demonstration of the practical influence on mask OD and the etched quartz depth of leading edge photomasks.

Model Based Mask Process Correction (MB-MPC) has been deployed in the photomask manufacturing process for almost a decade. It has now become a must have process for leading edge masks that require high level manufacturing accuracy. Recently, aggressive OPC methods such as ILT have significantly increased the complexity of mask data. This impacts Mask Data Preparation’s (MDP) processing time due to large mask data volumes. By its nature, MB-MPC process is quite time-consuming since it needs to perform complex calculations repeatedly, and so it takes the largest part of the total MDP time. This puts high pressure on turn-around time (TAT) reduction without losing accuracy and necessitates the need to develop algorithms that can operate on tight TAT budgets. Pattern Matching (PM) approach could be used to mitigate high processing times of MB-MPC by leveraging inherent repetitiveness of real-world mask data. Since a pattern simulation result is influenced by all patterns located within the mask model radius, to consider one pattern as a repetition of another, the central pattern as well as the neighborhood must match. This method is called Neighborhood Pattern Matching (NPM). In this paper, we evaluate the effectiveness of NPM when applied to the MB-MPC software developed by Synopsys. First, we introduce the fundamental concepts of NPM. Then we validate the algorithm with test patterns to evaluate its behavior. Finally, we measure processing time with several types of device patterns and confirm how NPM can reduce MPC calculation time on real mask data.

Over the last few decades, the scope of MDP has evolved from a handful of simple tasks, to veritable “jack of all trades”, capable of an enormous array of functions, in several different operational scenarios. These functions range from machine-specific fractures, to Boolean operations, OPC, MPC, checking, and beyond, under various scenarios including specific hardware configurations (such as single CPU vs. cluster, memory size, type, and location), software configurations (including operating system, load balancing, and prioritization), and inputs and outputs (formats, sizes, and so forth). While this versatile capability of tools, such as Synopsys’ CATS software, is powerful, the expertise required to operate them efficiently keeping abreast of the changing requirements and capabilities, poses a significant challenge to the average user.

We develop the monochromator and reflectometer to evaluate optical properties of an EUV optics and EUV resist at the BL3 beamline in NewSUBARU synchrotron light facility. This system supports from the EUV to out-of-band (OoB) energy region which corresponds at the wavelength region from 10 to 300 nm. This monochromator design is collimatedplane- grating monochromator with the constant-line-spaced grating of 1,000 lines/mm. The deviation angles are 150° for EUV region and 120° for the OoB region. The absorption edges of Si, Al and Mg filters are clearly observed using this system. The beam size on a sample position is 0.6(H) × 0.3(V) mm². We measured the EUV and OoB reflectance of a Mo/Si multilayer, an absorber TaN on the multilayer, and glass substrate which is used as a substrate of the black border on an EUV mask. The OoB reflectance of glass substrate was over 20%, which would affect to the EUV imaging performance in an EUV exposure tool. In addition, the OoB reflectance of the Mo/Si multilayer was quite different from that in calculation. Thus, it is important for evaluate the actual OoB reflectance of an EUV optics.

In an advanced IC fab, reticle inspection issues are critical as even one killer defect on the reticle can potentially affect thousands of wafers. Human errors such as defect mis-classification may lead to 70% of reticle issues that may affect production efficiency or even impact yield. With the adoption of RET techniques like aggressive OPC and SRAF combined with increasing MEEF and smaller defects, reticle dispositioning is becoming even harder and very time consuming in production. Even an experienced engineer may make a mistake especially when dealing with 40nm and below design nodes. The concept of automation to prevent mistakes in operation has been promoted for many years but a comprehensive solution which covers intelligent task assignment and auto reticle dispositioning in volume production has been missing. Working together with KLA, USCXM proposed a detailed methodology to overcome the above difficulties. From the very beginning, USCXM used Systematic Auto Recipe Creation (SARC) to create recipes for reticle inspections even before the reticles arrived in the fab. Also, an “OHT taxi mode” to improve pod utilization combined with the Reticle Management System (RMS) decision tree algorithm intelligently determined reticle inspection frequency based on wafer requirement and tool redundancy. Finally, USCXM automated final reticle dispositioning steps, such as, auto-releasing or auto-holding the reticle based on KLA’s Reticle Analyzer (RA) results. The overall implementation resulted in 25% improvement in inspection capacity and 50% reduction in operational cost compared to the traditional flow. Further, 92% accuracy for reticle auto-dispositioning was achieved with zero under-estimation. This integrated flow has proven to be invaluable for USCXM and is now deployed in full volume reticle manufacturing production.

Modern one-digit technological nodes demand strict reproduction of the optical proximity corrections (OPC) for repeatable congruent patterns. To ensure this property the optical and process simulations must be invariant to the geometrical transformations of the translation, rotation, and reflection. Simulators must support invariance both in theory, mathematically, and in practice, numerically. In the first part of this study we aim to examine manner and conditions under which optical approximations, such as Sum of Coherent Systems (SOCS) and Abbe decomposition, preserve or violate intrinsic invariances of exact imaging. In this age of asymmetrical pixelated sources, complex Jones pupils, and tilted chief rays, the full rotational invariance is observed only in some cases of annular illuminations; otherwise, it is rare in contemporary optics. In the second part we consider more important topic: invariances of compact process modeling (CPM) operators. Translational, rotational, and reflectional invariances are obligatory in CPM, because photoresist processing effects do not have preferential lateral direction, origin, or reflectional axis. The invariance of CPM operators has never been scrutinized before. We fill this gap by expanding generic translationally-invariant CPM operator into Volterra series, and then examine linear, quadratic, and high-order terms. Contrary to the straightforward invariance conditions for linear operators, the morphology of invariance for the second and high order operators is non-trivial. We found necessary and sufficient conditions for the invariance to take place, and provide examples of non-linear Volterra operators that can be used as atomic construction blocks in neural networks for CPM.