Two types of filters are proposed to detect a noisy target embedded in non-overlapping background noise by optimizing tow proposed criteria which are used in the filter design and performance assessment. Metric 1 is defined as the ratio of the square of the expected value of the correlation peak amplitude to the expected value of the output signal energy. Metric 2 is defined as the ratio of the square of the expected value of the correlation peak amplitude to the average output signal variance. It is shown that, for the non-overlapping target and scene noise model, the target window and the scene noise window affect the filter functions significantly.

A 32-channel system has been designed and built to process large-format synthetic aperture radar imagery. Eight Vander Lugt optical correlators operate in parallel, controlled by a single-board VME computer. The full-size images are divided into subscenes to match the processors' SLMs and compared to a stored filter bank. Each correlator incorporates two LCDs, four diffractive optical elements, a large CCD sensor, and a DSP based neural network post- processor. Custom drive electronics derive the LCDs at 60 Hz and double their normal operating resolution. The system is self-calibrating and automatically adjusts for a failure in any of the 8 processors. This paper will present a system level overview and discussion of each of the major sub- systems.

An optoelectronic detection system using two electrically addressed spatial light modulators in an optical correlator has been constructed to find regions of interest in cervical smear slides using the hit/miss transform algorithm. The purpose of the detector is to locate abnormal cells in the cervical smear and mark the region of interest for further classification by a second stage to the overall system. In addition, an image database of characteristic monolayer cervical smear images has been constructed for testing the system. The optoelectronic processing of cytological specimens can in theory provide both an improvement in the speed of scanning a slide for a region of interest and also a decrease in current manual screening errors. Results of the optoelectronic correlator and corresponding computer simulations will be discussed as well as further means of improving the system. Conclusions about further steps in the implementation of a complete medical diagnostic system including classification of regions of interest and improvements for automation will also be addressed.

A major concern in high speed, aided target recognition is getting enough information through the system, in the shortest possible time, to cover the desired targets while maintaining good target detection performance. With composite filter techniques, one can design a filter to respond over a range of scale and orientation for one target, and therefore, reduce the time required for a complete filter search. A variety of compositing techniques have been discussed on many occasions, and all have advantages and disadvantages. With available spatial light modulator technology, one must implement composite filters on devices with limited modulation states. Juday and others have proposed techniques for mapping desired filter functions onto these devices. This paper will present a filter generation methodology which combines Juday's mapping method with the MACE algorithm for generating composite filters.

Shape recognition is necessary in a broad band of applications such as traffic sign or work piece recognition. It requires not only neighborhood processing of the input image pixels but global interconnection of them. The Hough transform (HT) performs such a global operation and it is well suited in the preprocessing stage of a shape recognition system. Translation invariant features can be easily calculated form the Hough domain. We have implemented on the computer a neural network shape recognition system which contains a HT, a feature extraction, and a classification layer. The advantage of this approach is that the total system can be optimized with well-known learning techniques and that it can explore the parallelism of the algorithms. However, the HT is a time consuming operation. Parallel, optical processing is therefore advantageous. Several systems have been proposed, based on space multiplexing with arrays of holograms and CGH's or time multiplexing with acousto-optic processors or by image rotation with incoherent and coherent astigmatic optical processors. We took up the last mentioned approach because 2D array detectors are read out line by line, so a 2D detector can achieve the same speed and is easier to implement. Coherent processing can allow the implementation of tilers in the frequency domain. Features based on wedge/ring, Gabor, or wavelet filters have been proven to show good discrimination capabilities for texture and shape recognition. The astigmatic lens system which is derived form the mathematical formulation of the HT is long and contains a non-standard, astigmatic element. By methods of lens transformation s for coherent applications we map the original design to a shorter lens with a smaller number of well separated standard elements and with the same coherent system response. The final lens design still contains the frequency plane for filtering and ray-tracing shows diffraction limited performance. Image rotation can be done optically by a rotating prism. We realize it on a fast FLC- SLM of our lab as input device. The filters can be implemented on the same type of SLM with 128 by 128 square pixels of size, resulting in a total length of the lens of less than 50cm.

A self-pulling soldering technology has been demonstrated for assembling liquid crystal on silicon (LCOS) spatial light modulators (SLMs). One of the major challenges in manufacturing the LCOS modules is to reproducibly control the thickness of the gap between the very large scale integrated circuit (VLSI) chip and the cover glass. The liquid crystal material is sandwiched between the VLSI chop and the cover glass which is coated with a transparent conductor. Solder joints with different profiles and sizes have been designed to provide surface tension forces to control the gap accommodating the ferroelectric liquid crystal layer in the range of a micron level with sub- micron uniformity. The optimum solder joint design is defined as a joint that results in the maximum pulling force. This technology provides an automatic, batch assembly process for a LCOS SLM through one reflow process. Fluxless soldering technology is used to assemble the module. This approach avoids residues from chemical of flux and oxides, and eliminates potential contamination to the device. Two different LCOS SLM designs and the process optimization are described.

Development of optical information processing systems requires accurate models of the spatial light modulators employed in these systems. These models must recognize the multiport and non-linear nature of these devices. Here we describe the temporal characteristics of spatial light modulators by a quadratic multiport model. We use spectrum analysis and sinusoidal perturbation with synchronous detection to observe the nonlinear characteristics of a Hughes Model 4050 liquid crystal light valve. We present experimental results demonstrating some of the nonlinear characteristics.

In order to successfully transition optical processor prototypes from research laboratories to commercial markets, new packaging and manufacturing technologies will be needed. One approach which has been discussed is the use of reflective, off-axis diffractive optical elements (DOEs) in place of refractive optics. In this type of architecture the reflective DOEs are placed predominantly on a single planar surface which faces a second surface on which active devices such as laser diodes, spatial light modulators, and detector arrays are located. Light is deflected away form the surface normal of the planes so that it can propagate from one device to the next within the processor. This offers potential benefits of compact size, low cost mass production, and generic system designs. We are investigating the design, manufacture, and performance of optical processors which combine DOEs and FLC-VLSI spatial light modulators in this type of architecture.

Integration of vertical cavity surface emitting lasers (VCSELs) onto a prefabricated smart pixel chip introduces fabrication problems since they can not be grown on foundry fabricated Si CMOS or GaAs MESFET circuit. This paper presents an approach to flip-chip bump-bonding VCSEL-arrays to a pixel chip in which each VCSEL is bonding directly to the appropriate pixel circuit. Thus, no added area is required and the interconnect capacitance is held to a minimum. The technique requires contacting both the n- and p-mirror of the VCSEL on the same side of the VCSEL chip and in the same plane. This allows bump bonding both contacts to the pixel chip and subsequent removal of the VCSEL chip substrate. The steps required to accomplish the VCSEL coplanar bonding include reactive ion etching of mesas and device separation in BCL3/Cl, electroplating a 4.5 micrometers high gold coplanar contact post, In/Sn alloy solder deposition, bonding to the smart pixel chip, and accurate alignment of the VCSEL and pixel chips, epoxy underfill and at last substrate removal.

We describe an optoelectronic image processor that records in parallel multiresolution Gabor filter components of an image using incoherent light. The bandpass component of the output images is temporally modulated by modifications in the pupil plane. It is separated from spatial lowpass structures with the help of a modified image plane detector. OTF is invariant to shift in the pupil function; this property is used to implement parallel multichannel operation. A VLSI-based detector array is proposed to perform an extremum detection on each image pixel, thereby providing a low-pass representation of the bandpass image energy. Different Gabor-based filter characteristics and arbitrary resolution scale factors can be easily obtained by modifying a binary pupil plane mask. Preliminary experimental results for parallel optical implementation are presented.

The emergence of parallel switching and computational architectures are being technologically constrained by conventional electrical interconnects. The parallel nature of these new architectures have shifted the burden for increased throughput from increasing the device speeds to increasing the throughput of the communications between the many parallel switching nodes or processing elements. Some of the applications driving this demand are: video-on- demand, large database machines, high-definition television, control of large cellular communication networks, real-time graphics, weather and resource modeling, highly parallel communications with peripheral devices, video conferencing, telepresence, and 3D display. Optical interconnects can ameliorate the inherent interconnect limitations of electronics for these emerging digital parallel systems. This paper will review the status of optical interconnects.

In this paper, the structure and design of a crosspoint switch using the bi-directional free-space optical interconnect system is presented. An optical model for design of the system parameters such as VCSEL beam diameter, size and apodization of the hologram, and size of the detector is given based on crosstalk analysis of the system. Impact of VCSEL wavelength variation on the system design is considered. The hologram array design and a way to improve the diffraction efficiency by a copying technique utilizing DuPont photopolymer are presented. Aberrations due to the Fourier lens in the system are calculated and ways for correction of the aberrations are discussed.

This work describes the architecture and algorithms used in the computer-aided design tool developed for the automatic layout of integrated-optic, time-of-flight circuit designs. As in VLSI circuit layout, total wire length and chip area minimization are the goals in the layout of time-of-flight circuits. However, there are two major differences between the layout of time of flight circuits and VLSI circuits. First, the interconnection lengths of time-of-flight designs are exactly specified in order to achieve the necessary delays for signal synchronization. SEcondly, the switching elements are 120 times longer than they are wide. This highly astigmatic aspect ratio causes severe constraints on how and where the switches are placed. Assuming the continued development of corner turning mirrors allows the use of a parallel, row-based device placement architecture and a rectangular, fixed-grid track system for the connecting paths. The layout process proceeds in two steps. The first step involves the use of a partial circuit graph representation to place the elements in rows, oriented in the direction of the signal flow. After iterative improvement of the placement, the second step proceeds with the routing of the connecting paths. The main problem in the automatic layout of time-of-flight circuits is achieving the correct path lengths without overlapping previously routed paths. This problem is solved by taking advantage of a certain degree of variability present in each path, allowing the use of simple heuristics to circumvent previously routed paths.

Parallel optical memories have been proposed to meet high speed, high capacity storage requirements for input/output intensive computer applications. This technology offers the capability for storage and retrieval of optical data in 2D pages resulting in high capacity and high throughput. CUrrent raw bit error rates of experimental systems fall significantly short of the minimum industry requirement of 10^-12 for binary data. Thus, error control techniques for 2D data are necessary in order for such memories to be commercially feasible. In this paper, we discuss several error control schemes suitable for page- oriented data and specifically applicable to page-oriented optical memories. To better interface between the memory and the electronic host computer, we propose 'smart' photo- detector array devices in which the input is optical but the output is electronic. These arrays receive the optical signal form the memory and covert it to electronic data. Utilizing the speed of VLSI technology, the arrays perform fast parallel decoding and data correction, thereby providing an efficient optoelectronic interface between the memory and the electronic computer.

The output of parallel optical memories is a 2D set of data which propagates along the third dimension. Based on this characteristics we define a memory-computer optoelectronic interface and we analyze its functionality with respect to its degree of parallelism. Single-instruction multiple-data processing paradigms based on such interfaces are also discussed.

We have demonstrated an optoelectronic look-up table architecture using vertical-cavity surface-emitting laser- based logic. The system was implemented on a slotted plate understructure. An heterostructure photo-transistor-based optoelectronic XOR gate array was used to perform the necessary logic operations. The system's performance was satisfactory and based on the results we present here, we propose the design of a more compact version.

The design principles of inexpensive compact holographic read-only memory (CHROM) based on plastic card and its construction are discussed. CHROM capacity reaches 2...10 MByte.

A bi-directional free-space holographically interconnected crosspoint switch and FFT processor are under development at the Optoelectronic Computing Systems Center at the University of Colorado at Boulder. Both systems include two sets of optoelectronic modules which communicate with each other using free-space interconnects. The size of the detector array and the vertical-cavity surface-emitting laser (VCSEL) array on each module is 8 by 8. The packaging of such system is critical for the proper operation of the systems. The overview of the systems and the techniques used for fabrication are provided. A model f the tolerance analysis of the system is presented, in which the misalignments of the VCSEL array, microlens array, hologram array, Fourier lens, and the detector array are taken into account. The fabrication tolerances for each component required for correct system operation is given. Statistical analysis based on Monte Carlo simulation for the detection efficiency and signal-to-noise ratio is calculated given misalignment distribution of 17 misalignments of the components of the system. The methods used for the alignment of the system are discussed.

The features and operation of an electro-optically switched binary optical time delay system are discussed. THe system based on polarization switching using the low cost ferro- electric liquid crystal and polarizing beam splitters provides compactness, low complexity, low insertion loss and arbitrary time delay. We present the design, component selection, fabrication, testing, and evaluation of a prototype.