Two major concerns for ultrathin gate dielectric films have emerged with device scaling for CMOS devices: (1) B penetration in PMOS devices from the p⁺ boron-doped gate electrodes into the oxide and the underlying Si, (2) and increase in gate leakage current with decreasing oxide thickness. Oxynitride, nitride, and stacked nitride-oxide gate dielectrics have been proposed to overcome the above hurdles. Remote-plasma nitrided oxides (RPNO), involving nitridation of thermally grown oxides with a remote high-density nitrogen discharge, have emerged as promising candidates for ultrathin gate dielectric applications. These dielectrics are comprised of a thin layer of uniform and high N concentration at the poly/dielectric interface for an effective barrier to suppress B diffusion, and do not show the typical mobility and transconductance degradation observed (particularly in PMOS devices) with thermally grown oxynitride and nitride films. No increase in defect tail populations is observed from the nitridation. For stacked nitride-oxide films formed with this approach, a 10X reduction in gate leakage current is observed for T_ox,eqapproximately 2 nm. In applications involving metal gate electrodes, the RPNO films show significant reliability improvements over conventional oxides, attesting to potential advantages in preventing detrimental gate electrode/dielectric interactions. The potential advantages of such a gate dielectric scaling approach lie in: (1) the ability to start with a relatively thicker oxide where thickness targeting and process control is easier, (2) an essentially self-limiting process leading to 'built-in' uniformity of that of starting oxide, (3) the ability to control the thickness of the nitride layer and the spatial distribution of N, (4) adaptability/flexibility for integration with conventional oxide processing including cluster-tool processing, and (5) potential for scalability beyond the 0.10 micrometer technology node.

As COOS technology is scaled into the sub-0.25 micrometer regime, the poly-Si gate depletion effect becomes more problematic. This paper discusses various technological approaches to eliminating this effect. It is shown that poly- SiGe is an especially promising alternative gate material because it can be integrated into an existing COOS process with relative ease. As compared to poly-Si gate technology, poly-Si_0.8Ge_0.2 gate technology provides improved resistance to the gate-depletion effect, improved tradeoff between the gate-depletion effect and the boron penetration problem for p-channel devices, and superior device reliability. The viability of poly-Si_0.8Ge_0.2 as a gate material for sub-0.25 micrometer COOS technology is demonstrated in the fabrication of 0.1 micrometer channel- length MOSFETs.

In this paper we report on a simulation study on the impact of gate material on PMOS device performance. The gate materials studied were conventional poly-silicon gate, SiGe gate with varying Ge composition,and TiN/W metal gate. The motivation for alternative gate materials is to progressively alleviate or eliminate the poly depletion problem as observed with existing poly-silicon gate material, which becomes increasingly more important as the gate oxide becomes ultra thin (less than or equal to 26 Angstrom). Using these alternative gate materials, drive currents can be higher than those with conventional poly-silicon gate material, especially for PMOS devices where gate depletion is more pronounced. Two types of PMOS device designs were studied: (1) a high- performance design which is characterized by a maximum off current of 1nA/micrometer, and (2) a low-power design characterized by a maximum off current of 10 pA/micrometer. A plus or minus 10% variation in gate length is allowed for the high-performance design, and a larger variation for the low- power design. The minimum allowed gate length is 0.09 micrometer in both cases. Key results obtained from this study are as follows. First, use of TiN gate material results in a 30% improvement in pMOS nominal drive current compared to conventional poly-Si gate pMOS devices for the low-power device design, and a 15% pMOS nominal drive current improvement for the high-performance device design. Second, use of SiGe gate material results in a 25% improvement in nominal pMOS drive current compared to conventional poly-Si gate pMOS for the low-power device design, and a 13% pMOS nominal drive current improvement for the high-performance device design.

We developed FRAM (FRAM is a registered trademark of Ramtron International Corporation that stands for FeRAM) technologies that are fully compatible with half-micron CMOS logic's. The technologies achieve 1T/1C FRAM cell 12.5 micrometer² in a size and 68k-FRAM embedded 8bit-MCU. The CMOS transistors work at 5V for a cell operation and 3V for a logic operation. We did not use a COB to employ a present CMOS processing, and used the local interconnect to reduce a chip size. We used the W plug to contact to deep diffusion layers through high-aspect contact holes. The CMP planarization was used to relax PZT deposition and Pt etching. To prevent the process degradation of PZT, we used single Al wiring with SOG as an interlayer dielectric. The cover dielectric was formed with plasma TEOS- CVD without SiN to prevent the process degradation at this case. The SiN cover will be indispensable in real products. These technologies achieved a cell size 6.95 X 1.8 equals 12.5 (micrometer²) for 1T/1C and 4.2 X 6.5 equals 27.3(micrometer²) for 2T/2C that are the smallest cell size in FRAM's that do not use a COB structure and a poly-plug as a storage.

Gate insulator/stack scaling is arguably one of the most challenging aspects of device scaling. As gate lengths are scaled into the sub-100 nm regime, alternate materials other than SiO2 will be needed to continue device scaling. The SIA roadmap has called for introduction of high-k materials below the 100 nm technology node due to problems with direct tunneling in SiO2. However, introduction of high-k poses many challenges in the process/materials side in CMOS process integration. Also, there are device scaling issues that are equally important. When k is increased beyond a certain level, unforeseen effects come to play. A phenomenon known as fringing-induced barrier lowering (FIBL) increases Ioff and degrades the subthreshold swing of the device. This paper describes this phenomenon, and provides insight into device scaling with high k materials. A host of other tradeoffs, especially those concerning control of Ioff and speed, are examined using 2-D simulator and analytical models. Suggestions to control FIBL are also detailed.

Verdant Technologies is developing Laser Thermal Processing (LTP) as an alternative to rapid thermal annealing (RTA) for ultra-shallow junction and self-aligned silicide contact formation. Although new, the laser-based technology is a strong contender in the area of contact formation because it offers superior technical performance. The control of dopant diffusion and improvement in activation offered by LTP has led to junctions shallower than 35 nm and with sheet resistance lower than 100 (Omega) /square. Titanium silicide has been shown to form on linewidths down through 0.07 micrometer -- effectively extending the useful lifetime of titanium silicide processing. In addition, the laser-based process allows the silicide thickness over source/drain and gate regions, for both cobalt and titanium, to be controlled independently. This has resulted in gate resistivity of 1 (Omega) /square on linewidths down to 0.07 micrometer. In the Verdant approach, laser light is used to heat the silicon through an absorption process, directly driving the doping or silicidation process in a non-equilibrium and area-specific manner. These aspects of the process allow ultra-shallow contact formation with significantly lower electrical resistance in the silicon and silicide.

In this paper, we studied the feasibility of using a commercial etch chamber to perform plasma doping to form shallow p⁺-n junction. The plasma doping has the advantage of high wafer throughput compared to conventional low energy implanters. Ultra-shallow boron implantation was done in a plasma reactor with a Helicon plasma source and a gas mixture of He+B₂H₆. 0.18 micrometer class PMOS devices were fabricated using the plasma doping and compared with devices with a conventional BF₂ S/D extension implant (10 keV BF₂ implant, X_j approximately equals 650 Angstrom). The key results are as follows. (1) Shallow boron implant with good process uniformity on a wafer was achieved using the plasma doping process. Boron dose of approximately 5E14 cm^-2 and junction depth (X_j) of approximately 250 Angstrom was achieved after S/D annealing. (2) The pMOS devices fabricated using the plasma doping have much better short channel effect (SCE) characteristics than the devices fabricated with 10 keV BF₂ implant. The improvement of X_j in the vertical direction of a transistor (from approximately 650 angstrom to approximately 220 angstrom) using the plasma doping resulted in an improvement of approximately 450 angstrom in the lateral direction shown in L_g^min. (3) Degradation in gate-depletion was observed for the plasma doping devices; however, the degradation can be recovered by using an extra gate implant step. (4) Compared to devices with the conventional implant, higher R_sd was found in devices with the plasma doping process. This higher R_sd for the B₂H₆ cases was most likely due to the less gate-to-drain overlap and carbon/oxygen contaminants introduced during the plasma doping process. (5) Higher gate- edge diode leakage was also observed in the plasma doping devices. The high diode leakage was believed also due to the contaminants.

The impact of Rapid Thermal Anneal (RTA) temperature uniformity, ramp-up and cool-down rates on device parameters is a key issue that affects the manufacturability of the process. An L9 with center point designed experiment for RTA Source/Drain (S/D) anneal process parameters was done to characterize the process window for a 0.25 micrometer complementary poly CMOS process. The steady state RTA temperature was varied by plus or minus 20 degrees Celsius around the center point, the ramp-up rates varied from 60 to 110 degrees Celsius/sec, and the cool-down rates were varied by changing the cool-down N2 flow. The N-ch Vt was found to vary by 20 mV with the steady state temperature variation, 20 mV with the ramp up rate and had no dependence on the cool- down rate. The P-ch Vt was found to vary by 25 mV with the steady state temperature, and had no significant dependence on the ramp up or cool-down rate. The drive current and sub- threshold leakage variation for both types of devices tracked the Vt variation. No significant boron penetration was observed at the highest RTA temperature as evidenced by a tight P-Ch Vt distribution. The junction leakages were found to be reduced with higher RTA temperature, perhaps due to slightly deeper junctions. Over-all, the variation in the key device parameters was very small compared to the worst to best case variation allowed in the SPICE model. This establishes the robustness of the device design against variations in RTA parameters.

In order to continue scaling the gate to gate spacing in CMOS for higher packing density, the thickness of source/drain (S/D) spacer and the S/D junction depth (X_j) underneath the silicide film have to be scaled accordingly. Therefore silicided shallow junction with low diode leakage at S/D region has to be achieved. Silicide as diffusion source (SADS) is an attractive shallow function formation technology, because it is a relatively simple and low-cost technology compared to other shallow junction techniques, such as raised source/drain. In the SADS process, first the self-aligned salicide is formed and followed by the S/D dopant implant into the silicided region. Subsequently low temperature annealing is performed to drive out the dopants from the silicide film and form shallow junctions. Since dopants diffuse fast in silicide, ideally the junction follows the silicide/silicon interface contour (including the any existing spiking region), which low diode leakage can be achieved. In this study, nMOS devices fabricated with CoSi₂ SADS were compared with devices fabricated using the conventional cobalt silicided junction. The spacer thickness was varies from 350 Angstrom to 850 Angstrom. Different annealing conditions (temperature and time) used to drive As dopants out of the CoSi₂ film were also studied. The advantages and problems associated with the SADS in a deep sub-micron process flow will be discussed. The key results from this study are as follows. (1) Initially X_j of SADS junction increases with the annealing temperature, and then it decreases as the temperature continues increasing. Significant dopant loss occurred at high annealing temperature. (2) NMOS devices fabricated using SADS showed much better short channel characteristics compared to the conventional devices especially when the thin spacer was used. (3) Less inverse short channel effect was shown in SADS devices, which improved the variation of drive current with gate length. (4) SADS devices showed slight degradation in drive current, which was caused by the worse gate-depletion in these devices. (5) The best annealing condition for low diode leakage in the SADS junction was identified in this study. However, even in the best case, the diode leakage is an order of magnitude higher than the conventional silicided shallow junction. The drawbacks of SADS in deep sub-micron transistor design were identified and discussed.

This work compares the extendibility of titanium with pre- deposition amorphizing implant (PAI) and cobalt salicides to sub-0.25 micrometer technologies. Cobalt salicide has low sheet resistance and a tighter distribution of sheet resistances than titanium salicide with PAI for narrow linewidths. The reaction of cobalt with silicon is not affected by dopants in the silicon as the reaction of titanium is. Less cobalt need be deposited than titanium for a given sheet resistance target. Cobalt salicide requires fewer process steps than titanium salicide with PAI. Cobalt salicide has lower diodes for shallow junctions, requires a smaller thermal budget, and provides a lower contact resistances than titanium salicide. Thus, cobalt salicide process technology has better process control, is more compatible with sub-0.25 micrometer devices, and more compatible with interlayer connections than titanium salicide with PAI.

For scaled CMOS technology with gate length down to sub-0.25 micrometer, the conventional Ti salicide suffers from high polygate sheet resistance (R_sheet) due to difficulty in the low resistivity C54 TiSi₂ phase transition. To improve the sub 0.25 micrometer TiSi2 R_sheet, pre-amorphization implant (PAI) was added to achieve low R_sheet down to approximately 0.1 micrometer gate length, and PAI based TiSi₂ has been the base-line salicide process for current 0.25 micrometer CMOS technology. However, various studies on sub 0.18 micrometer devices have shown that PAI process tends to induce additional S/D dopant diffusion and results in the series resistance (R_SD) increase and drive current degradation, especially for pMOS transistors. On the other hand, Mo implant was found effective in enhancing the C54 TiSi₂ formation for narrow lines and has the potential to realize a simplified TiSi₂ process with one single thermal step. However, the Mo based Ti salicide is still relatively new to date, and a complete CMOS study is helpful in identifying the trade-offs for such a process. In this work, we present a detailed CMOS evaluation of Mo doped TiSi₂ process. Two different Mo based processes are studied: (1) Mo implant into gate before gate pattern (Mo-A case). In this case, the source/drain (S/D) diffusion regions have minimal Mo doping. (2) Mo implant into gate and S/D regions right before the S/D anneal (Mo-B case). For both Mo-A and Mo-B processes, we also studied the effect of Mo doses and the difference between the conventional 2-step rapid thermal process (RTP), low-temperature formation plus Ti strip plus high-temperature anneal, and the 1-step RTP process, namely low-T formation plus Ti stripe, where the high-T anneal is skipped. The results of the Mo processes are compared with three other reference salicide processes: conventional TiSi₂ without PAI (Conv.), TiSi₂ with Ge or As PAI and the emerging CoSi₂ technology. The following CMOS care-abouts are evaluated for the various salicide processes: (1) polysilicon and diffusion region R_sheet, (2) various bridging mechanisms, (3) diode leakages: bottom junction, trench edge and gate edge leakage currents, (4) drive current and R_SD, and (5) charge to breakdown (Q_BD).

A MOS transistor with a channel length under 0.20 micrometer was developed with the process equipment typically utilized for a conventional 2 micrometer device. The transistor was built on the vertical side walls of a 3 dimensional trench, thus achieving much higher channel width W, and lower channel length L than possible using 2 micrometer planar technology. The capability of having larger W coupled with non- photolithography limited L, gives this vertical MOS transistor great advantages in drain current I_DS, transconductance g_m, and operation frequency f_o over same technology planar transistors.

This paper discuses new experimental findings critical for process integration of deuterium post-metal anneals to manufacturing multi-level metal CMOS integrated circuits. Detailed account of the optimization experiments using the deuterium process is given varying temperature (400 - 450 C), time (0.5 - 5 hr), and ambient (10 - 100% D₂). It is shown that the deuterium/hydrogen isotope effect is a general property of MOS wear-out by evaluating many transistor structures from various CMOS technologies. Physical insight into the transistor degradation mechanisms is provided via fundamental STM Si-H(D) desorption experiments and physics based simulations.

Motorola's Graded Channel CMOS (GCMOS) provides a low cost and highly integrated solution for mixed-mode and RF applications. The GCMOS transistor has demonstrated performance advantages over standard CMOS processes with the same physical gate length. The graded channel, fabricated using lateral diffusion, provides a deep submicron Leff even with a gate length of 0.6 micrometer. The technology is constructed using a process that is fully compatible with standard CMOS manufacturing. However, in order to assure adequate threshold control, the lateral diffusions must be well-behaved. This means that both the channel implant and the source/drain implant must be truly self-aligned, requiring good control of the implants as well as the gate electrode profile. For aggressively designed GCMOS devices, small deviations of the implant beam from normal incidence can lead to unacceptable shifts in threshold. The sources of such error, and current industry standard machine tolerances for each, are discussed. Strategies for ensuring adequate control include a regimen of in-line process monitors, approximate error cancellation of the channel and source/drain implants, and the use of quadrature implants. By using these strategies a manufacturable process has been achieved.

An integrated shallow trench isolation process utilizing HDP (High Density Plasma) oxide and a highly manufacturable corner oxidation is described. The choice of trench corner oxidation temperature is shown to be critical in reducing silicon stress, and hence junction leakage, to the levels required by multi-million gate designs. This STI process is shown to be extremely robust and manufacturable. Optimal design of the trench depth and well profiles is shown to provide well-edge isolation adequate for sub-0.18 micrometer technologies.

In this paper, we compare four different approaches for transistor design for the 0.25 micrometer technology from the point of view of performance, stand-by power and ease of manufacturing. For the high performance logic applications such as high end microprocessors, 0.18 micrometer transistor (L_gate equals 0.18 plus or minus 0.02 micrometer) with super steep retrograde wells and halo implants but without extension implants can achieve maximum frequency of operation (F_max) exceeding 380 Mhz for the 0.25 micrometer technology. On the other hand, for low power applications such as mobile communication equipments, a different 0.22 micrometer (L_gate equals 0.22 plus or minus 0.02 micrometer) transistor design which simplifies manufacturing process by eliminating two photolithography steps becomes more attractive. The four transistor designs are compared using CV/I metric and manufacturability trade-offs are discussed.

In this paper a merged 2.5 V and 3.3 V high performance 0.25 micrometer CMOS technology is presented. Issues relevant to manufacturing, such as L_eff control and the impact of plasma-assisted back-end dielectric depositions on gate oxide reliability and isolation, are discussed. This technology features a 50 angstrom gate oxide, high-energy implant scheme, n⁺-polysilicon gate, and 4/5 levels of metal. An improvement of 1.45X in circuit performance and 4X in packing density is achieved over our 0.35 micrometer CMOS technology. The nominal ring oscillator delay time is 38(39) ps for 3.3(2.5) V operation.

For high-end or low-power CMOS devices, accurate control of the threshold voltage (V_th) is crucial because V_th deviation from the target value decreases the performance and yield of devices. In the conventional process, V_th is determined by channel doping performed early in the fabrication process, and cannot be corrected afterwards even if the variation in the gate length and gate oxide thickness resulting from the fabrication process is large. With the scaling down of devices, accurate control of V_th becomes even more difficult because the effect of the process variation becomes more pronounced. We propose a new feed- forward adjustment scheme for V_th by using post- metallization hydrogen ion implantation. The implanted hydrogen deactivates channel impurities and decreases V_th for both NMOS and PMOSFETs, and this effect remains stable after standard back-end process including post-metallization annealing (400 degrees Celsius). Th V_th change obtained was about 0.1 V at a hydrogen dosage of 1 x 10¹³ cm^-2 for NMOS and PMOS FETs. The impact of this technique on oxide reliability is small and acceptable for practical usage. Using this technique, we can adjust V_th after we measure its actual value and compensate for the V_th variation caused by processing. Hydrogen ion implantation is thus a useful technique for feed-forward yield management.

In this paper we investigate the material characteristics of implanted indium under channel doping conditions. Indium was implanted into CZ silicon at an energy of 200 keV and doses of 2e12/cm² to 1e14/cm². Subsequent rapid thermal annealing was conducted at 950 degrees Celsius to 1050 degrees Celsius between 10 sec and 30 sec. The diffusion of indium was studied by means of Secondary Ion Mass Spectroscopy (SIMS). Up to a dose of 1e13/cm², the diffusion of indium was in- significant. The activation of indium was studied by means of Spreading Resistance Profiling (SRP). It was found that at a concentration of about 2e17/cm³, the electrical solubility is reached above which no more activation can be achieved. Damage due to indium implant was studied by Transmission Electron Microscopy (TEM). Dislocation loops remain stable after high temperature anneal for higher dose implants and dissolve for lower dose implants.

Epitaxial Si_1-yC_y and Si_1-x-yGe_xC_y alloy layers are grown on monocrystalline silicon substrates by multiple energy ion implantation of Ge and C into single Si crystals followed by pulse excimer laser annealing. The properties of the alloy layers are determined precisely using spectroscopic ellipsometry (SE), x-ray diffraction (XRD) and Rutherford backscattering (RBS) techniques. We show that annealing energy densities higher than 2 J/cm² result in monocrystalline epitaxial layers with low quantity of defects. The lattice contraction due to the carbon inclusion increases with the implanted C concentration up to about 1.1%. For higher values a more complex behavior is observed with partial (or total) relaxation of the layer and/or carbide formation. With optimized condition, the growing of pseudomorphic epitaxial layers, from group IV semiconductor alloys was successful on large areas thanks to the high power excimer laser developed at SOPRA (1 J/cm² over 40 cm² in one pulse).

In CMOS technology for EEPROM, refractory metal silicide is currently used to shunt the doped polysilicon layer for the floating gate electrode. Due to their manufacturability, tungsten silicide (WSi₂) and tantalum silicide (TaSi₂) are widely used in integrated circuit manufacturing. In this paper, electrical tests are performed on MOS capacitors and on memory cells. We will compare three types of silicides: TaSi₂ deposited by sputtering and WSi₂ deposited with two chemistries: the monosilane reduction of tungsten hexafluoride (MS) and the dichlorosilane reduction of tungsten hexafluoride (DCS). Regarding the cycling performance of the memory cell, tantalumsilicide and tungsten silicide DCS are both good candidates for gate material, but in term of data retention results, they are not the best candidates because of their higher charge loss during bake.

Selective W-CVD technology with hydrogenation and hydrogen- termination treatment was developed to reduce source/drain sheet resistance in ultra-thin-film fully-depleted CMOSFET's/SIMOX, and it was applied to 0.25-micrometer-gate gate-array LSIs. It is clarified that this technology ensures single-contact cells, which are vital for higher packing density, with no degradation of device characteristics, circuit performance, and LSI yield. Moreover, recent results for devices with a W-covered gate/source/drain are presented.

PtSi source/drain Schottky barrier MOSFETs have been fabricated at sub-50-nm channel lengths with 19-angstrom gate oxide. These p-channel devices employ gate-induced field emission through the PtSi approximately 0.2-eV hole barrier to achieve current drives of approximately 200 (mu) A/micrometer at supply voltage of 1.0 V. Delay times measured by the CV/I metric extends scaling trends of conventional p-MOSFETs to approximately 2 - 3 ps. Thermal emission over the low Schottky barrier limits on/off currents to approximately 25 - 50 in undoped devices at 300 K, while ratios of approximately 10⁷ are measured at 77 K. On/off ratios at room temperature can be improved to approximately 10³ by implanting a thin layer of fully-depleted donors beneath the active region or use of ultra-thin SOI substrates.

In this paper, a simulation study to predict the performance of CMOS technology in the deep sub-micron regime (0.20 micrometer down to 0.05 micrometer) is presented. The metric used to evaluate the CMOS transistor performance is a Figure of Merit (FOM). Using tuned process and device simulators, the performance FOM of bulk CMOS technologies were evaluated, with varying (1) gate lengths in the range of 0.05 - 0.20 micrometer, (2) power supply voltages (Vdd) of 1.0 - 1.8 V, (3) gate oxide thicknesses (Tox) of 20 - 40 A, (4) maximum off-state leakage currents of 0.01, 1 and 100 nA/micrometer, (5) different source/drain resistances and (6) different polysilicon doping levels. Vdd and Tox were scaled with gate length such that Vdd/Tox is fixed at about 5 MV/cm. It is found that it is increasingly difficult to keep the proportionality between performance FOM and 1/L_gate as the gate length is scaled to around 0.10 micrometer or below. This deviation is due to the decreasing trend of transistor drive current caused by the low supply voltages to be used and the nonscalability of V_T. In order to try and improve the performance of CMOS technology, metal-gated Fully Depleted SOI CMOS transistors were evaluated in this study. It was found that although Fully Depleted Metal-Gate SOI provides an improvement in performance over conventional bulk CMOS technology, the FOM does not linearly scale with the gate length. The improvement in FOM obtained is almost entirely due to the smaller junction capacitance in SOI and not due to significantly increased drive currents in metal-gate FD-SOI when compared to conventional CMOS. Further, FOM performance falls short of the roadmap targets as the gate lengths are scaled below 0.10 micrometer just as in bulk CMOS. The effects of Off Current specifications and supply voltage on FOM were studied. It is shown that the CMOS performance can be improved by: (1) slightly increasing the supply voltage, and (2) using a dual- V_T approach in which low-V_T transistors are used in the critical path to improve circuit performance. With these approaches it is possible to extend the proportionality between FOM and 1/L_gate down to about 0.08 micrometer gate length.

This paper reports experimental results of polysilicon gate patterning for sub-100 nm and deep sub-100 nm (less than 50 nm) MOS technology development. Sub-100 nm and deep sub-100 nm polysilicon gates have been achieved using an aggressive etch bias process combined with deep ultraviolet (DUV) lithography. In this paper, we report results on BARC effect, uniformity and iso/dense bias, etch selectivity, poly profile sensitivity, endcap pullback and metrology issues. We have achieved pitting free etch for ultra thin gate oxides down to 15 A. Deep sub-100 nm (approximately 50 nm) photo resist lines and deep sub-100 nm (less than 50 nm) poly gates with a good profile have been obtained.

An optimal design for 0.1 micrometer PMOS, consistent with SIA-NTRS Roadmap projections, is developed using a Response Surface methodology (RSM). The impact of four different low thermal budget growth and deposition gate dielectric processes (Furnace oxidation, Rapid Thermal Oxidation (RTO), Rapid Thermal CVD (RTCVD) and Remote Plasma Enhanced CVD (RPECVD) on the design optimization is examined. A Design Of Experiments (DOE) approach was independently employed in each case with simulated baseline surface channel PMOSFET structures having a 2.0 nm gate oxide to statistically explore the channel and extension junction parameter spaces. Channel and extension junction parameters were separately optimized, with channel optimization performed for both doubly-implanted and uniformly doped channels. The condition for constrained optimization was the maximization of I_sat at the NTRS Roadmap specified I_off value of 3 nA/micrometer. A 20% manufacturing tolerance in channel length was factored into the optimization strategy by measuring both I_sat and I_off under their respective worst case tolerance conditions. Optimal designs with modestly differing implant specifications but exhibiting largely comparable performance characteristics were identified for each gate stack. Excellent current drivability of 279 (mu) A/micrometer was obtained at the nominal L_eff of 70 nm. Optimized doubly-implanted channels provide 7.5% higher current than the uniformly doped ones. Optimum extension junction design was achieved by a high surface concentration of 2 X 10²⁰ cm^-3, extension depth of 32 nm and spacer width of 49 nm, and the analysis clearly revealed that a necessary condition for junction optimization was the onset of drain decoupling from the channel.

Device degradation due to hot-carrier injection in sub-100 nm gate length devices has been investigated. 90 nm gate length (CD SEM) N-MOSFETs with 2.2 nm nitrous oxide (Idsat equals 735 uA/micrometer, Idoff equals 1.1 nA/micrometer Vdd equals 1.5 V) are electrically stressed and measured up to 200,000 seconds. Both VgIsubmax and Vg equals Vd stressing conditions at 1.8, 2.0, 2.2 V, 2.5 V and 2.8 V are performed. Contrary to traditional understanding, Vg equals Vd, i.e. channel hot carrier injection CHCI), stress causes more idlin, Idsat, Vt and Gm degradations. Similar trends are observed in NMOS devices fabricated with 1.6 nm thermal and nitrous oxides as well as 1.3 nm nitric oxides. CHCI being a worst case DC hot carrier stress condition for sub-100 nm devices with ultra- thin gate oxides is a gate-length and stress-voltage dependent phenomenon. For 90 nm NMOS devices, VgIsubmax degradation becomes dominant again when stress voltage is 2.0 V or less. For a set stress voltage, e.g. 2.5 V, VgIsubmax degradation is observed to be dominant for gate length (L_eff) larger than 130 nm (90 nm). Negligible device degradation (less than 1%) under high uniform gate field tunneling stress suggests lateral electric field is causing the device degradation and CHCI as the dominant stress mechanism in sub-100 nm N-MOSFETs with direct tunneling oxides. Post-stress sub-threshold swing, charge-pumping and DC-current-voltage characterization suggest that stress-generated interface trap is a major cause of device degradation.

This paper presents a new approach to model the pocket implanted transistors for simulating sub-0.18 micrometer CMOS. The simulation approach presented in the prior publications for pocket implanted transistors has limitations in accurately matching the experimental Vt-rolloff and DIBL characteristics for gate lengths in the sub-0.18 micrometer regime. This is due to the fact that the pocket profile used in the prior simulator does not account for the 2-D boron redistribution effect caused by the source/drain extension implant (MDD). The new model incorporates two-dimensional redistribution of pocket caused by the drain extension implant. There are no additional modeling parameters added for the simulations when compared to the previously published model. The calibrated simulator with the new pocket model shows good agreement with the experimental data for 0.10 - 0.18 micrometer technology transistors.

For scaled CMOS technologies, the source/drain-extension (MDD) junction depth (Xj) is important in achieving optimized device performance. According to the SIA roadmap, Xj is about 0.3 - 0.5 times the nominal gate length (Lgnom) for previous device generations as shown in Fig. 1. For devices with fixed Lgnom, shallower MDD can improve the short channel effects and the drive current sensitivity, however, trade-off occurs due to the increase in effective gate length and channel resistance. Various engineering techniques such as pocket implant can also change the requirement for Xj. It is therefore important to predict the Xj requirement for various transistor designs and facilitate faster turn-around time and minimize the design cost. In this work, a tuned 2-D MEDICI simulator is used to investigate the effect of Xj for 0.1 micrometer to 0.15 micrometer gate length devices. Effects of pocket implant and the use of an additional MDD spacer are compared. Both high performance (maximum off current equals lnA/micrometer) and low power (maximum off current equals 0.01nA/micrometer) devices are studied. For a given device design, an optimum Xj is found where the nominal drive current is maximized for fixed Lgnom and source/drain resistance (R_SD). Key results are as following. (1) For high performance devices with pocket implant, the optimum Xj for S/D extension is approximately 300A (450A) for 0.1 micrometer (0.13 micrometer) Lgnom devices. Without pocket implant, the optimum Xj is reduced to approximately 250A (300A) which falls below the predicted lower limit of 0.3xLgnom. The improvement in the short channel roll-off by pocket implant allows the use of deeper junctions. Furthermore a 5% increase in nominal drive current is also observed for 0.1 micrometer devices with pocket implant. (2) The Xj requirement can be relaxed by using a thin MDD sidewall spacer. By adding a 200A MDD spacer, the optimum Xj for high performance device with pocket implant is approximately 450A and 550A for 0.1 micrometer and 0.13 micrometer node devices. However, addition of a MDD spacer will result in reduced gate overlap and hence larger R_SD. It is found that a 200A spacer would result in an additional S/D resistance of 80 (Omega) for nMOS devices and cause 3 - 6% degradation in drive current. (3) For low power version devices with higher threshold voltage, Lgnom is adjusted to 0.11 micrometer and 0.15 micrometer while the minimum gate length (Lgmin) is set to be 85% Lgnom to account for the better short channel effects. The optimum Xj for low power devices with pocket implant is 250A (350A) for 0.11 micrometer (0.15 micrometer) Lgnom devices which is about 50 - 100A shallower than the Xj for high power devices. MDD spacer is more effective for low power devices and a 200A MDD spacer increases optimum Xj by 200A, matching the requirement for high power devices.

Reducing parasitic series resistance is an important issue for producing deep-submicron high-speed CMOS. Some valuable methods for determining parasitic resistance have been developed. However the extracted parasitic resistance for the pMOS (1000 (Omega) (mu) m) is much larger than rough estimation base of extension sheet resistance, silicide-bulk contact resistance and silicide sheet resistance would indicate. This paper described the inverse modeling technique to determine the active doping profile from measured CV and IV characteristics. We found that contribution of extension profile to the parasitic resistance was about 80% and the rest was caused by silicide-bulk contact resistance. The reason is that only 5% of implanted boron was activated. For more complete activation, a higher RTA temperature is effective. RTA at a temperature of 1050 degrees Celsius for 5 seconds confirmed by spreading resistance measurements that the activation ratio was three times larger than that at a temperature of 1000 degrees Celsius for 10 seconds. Consequently a parasitic resistance reduction of 100 (Omega) can be expected by using the higher temperature process.

Accurate modeling of ultra-low energy ion implantation is becoming increasingly more important as MOS devices shrink to deep submicron dimensions, and the required junction depths become shallower than 50 nm. To this end, an efficient Monte Carlo ion implantation model based on a substantially modified Binary Collision Approximation (BCA) has been developed and implemented in UT-MARLOWE. The model eliminates the asymptotic path approximation and explicitly includes 3-body interactions, allowing for accurate modeling of ultra-low energy collisions. In this paper, we report on the experimental verification of the model, as well as refinements and corrections subsequently introduced. This paper also discusses the difficulties in obtaining accurate SIMS profiles for ultra-shallow implants, and methods for overcoming them. Surface effects are also discussed, and their impact on the dose-dependence of the profiles is examined. The model has been verified for arsenic and boron, for energies down to 1 keV and 500 eV, respectively. This new model is found to be in good agreement with the experimental data.

Computationally efficient ion implantation modeling is highly essential for efficient silicon device technology development and improved process control. Indeed, analytic models are particularly desirable for two-dimensional simulations, which are very expensive in terms of computation time. This paper describes analytic models for both the impurity and the damage profiles in one and two dimensions. Legendre polynomials are used as model functions and their orthogonality property is exploited to simplify and allow the automation of parameter extraction. Using 14 Legendre polynomials (16 model parameters), a wide variety of impurity and damage profiles can be modeled accurately. In addition, the shortcomings of the conventional superposition approach to 2-D modeling are explained, and a modified approach based on dose-splitting is proposed. The 2-D impurity and damage profiles generated by this modified superposition approach are shown to have very good agreement with the physically based and experimentally verified Monte-Carlo simulator, UT-MARLOWE. Computation times can be reduced by approximately a factor of 50 without sacrificing accuracy when the analytic approach is used instead of a Monte-Carlo simulation.

Matching NPN and PNP collector profiles for high-speed complementary bipolar technology presents a special challenge to epi processing. This paper describes a novel thin epi process that is designed to reduce the effect of boron autodoping and improve the NPN collector doping in the deep portion of the collector region. Summary evaluations of autodoping are presented for different H₂ bake and HCl etch cycles, and for the use of intrinsic- and As-doped cap layers. An epitaxial technique, which introduces As dopant during the high temperature H₂ bake, is described. This technique has proven very effective in suppressing the effects of boron autodoping and correcting the NPN collector profile.

Production the high-quality ohmic contacts to AlGaAs layers with high contents AlAs (more than 25 - 30%) is a complicated and still incompletely resolved problem. This is connected with the presence of a thick surface layer of native oxide. The possibility of producing contacts to Al_xGa_1-xAs with the use of preliminary cleaning of the surface in atomic hydrogen has been investigated. Used in the experiment were n- type (approximately 65% AlAs) and p-type (approximately 35% AlAs) Al_xGa_1-xAs substrates. The cleaning of the specimen surface in atomic hydrogen (T equals 300 - 400 C, t equals 10 - 90 min) and the deposition of the contact metal (Au/AuGeNi/AuGe for n-type, and Au/AuZn/Au for p-type) were conducted in a unified vacuum cycle. Annealing in the ambience of hydrogen was produced under T equals 400 - 520 C. The technological conditions required to realize the cleaning of the surface of Al_xGa_1-xAs in a thermal film deposition system with a moderate vacuum has been investigated. The AES method was used to find the cleaning modes that allow removal of the oxide film with the stoichiometric composition of Al_xGa_1-xAs retained. It has been shown that the operations of cleaning and metal deposition combined in a unified vacuum cycle make it possible to produce a high-quality low- resistance contact showing high adhesion.

This paper describes a new method to improve the base- collector breakdown voltage of high frequency NPN bipolar transistor. It consists of introducing a suitable P floating region in the N collector by ion implantation or by molecular beam epitaxy. The basic profile of the intrinsic transistor is not changed. Computer device simulations show that a nearly 20% improvement of the base-collector breakdown voltage can be achieved in a common emitter configuration. Additional advantages are a reduction of the multiplication factor and an enhanced impact-ionization base current reversal voltage.

High efficiency is the key to large-scale applicability of photovoltaic systems. The efficiency depends on material fabrication and design parameters. One of the most successful approaches to improve efficiency is to aid the drift of minority carriers by a stronger electric field. This can be effectively accomplished through bandgap profiling. In this paper, we have developed a model to describe bandgap profile, the electric field and the current-voltage characteristics of p-i-n solar cell. A technique for optimizing graded bandgap profile in p-i-n aSi:H solar cell has been developed using a Fletcher-Powell minimization technique. The parameters to be optimized are replaced by independent variables without constraints. The variables include the coefficients of a third order equation describing the bandgap profile under consideration. The method allows a simultaneous optimization of parameters leading to maximization of solar cell efficiency. It suggests a new cell design criterion in terms of optimum and bandgap profile.

Historical microprocessor product trends show an increase in product frequency of 1.25x per year and a transistor count increase of 1.4x per year since the early 70s. This tend is forecast to continue over the next decade to the 0.07 micrometer generation. To support the trend, challenges in lithography, transistor definition, interconnect system, and manufacturability must be overcome. Solutions to the lithography challenge, will require successful implementation of 157 nm optical or next generation lithography (NGL). The transistor solution will require integration of sub 2.0 nm gate oxides with improved gate electrode materials, improved low resistance shallow source-drain technology, advanced channel dopant engineering, and operation at or below 1.0 v. Interconnect challenges will require support of 10 or more interconnect layers using low resistivity metalization and reduced epsilon dielectric. Manufacturing challenges require support of larger die sizes, integrated at higher technology complexity, while maintaining lowest possible cost.

Recently, IBM announced the first silicon integrated circuit technology that incorporates copper on-chip wiring. This technology, which combines industry-leading CMOS ULSI devices with 6 levels of hierarchically-scaled Cu metallization, has reached the point of manufacturing, after passing the qualification tests required to prove feasibility, yield, reliability, and manufacturability. The discussion of the change from Al to Cu interconnects for ULSI encompasses a wide variety of issues. This paper attempts to address these by way of example, from the broad range of detailed studies that have been performed in the course of developing these so-called 'copper chips.' Motivational issues are covered by comparative modeling of performance aspects and cost. The technology parameters and features are shown, as well as data relating to the process integration, electrical yield and parametric behavior, early manufacturing data, high-frequency modeling and measurements, noise and clock skew. The viability of this technology is indicated by results from reliability stressing, as well as the first successful demonstrations of fully functional SRAM, DRAM, and microprocessor chips with Cu wiring. The advantages of integrated Cu wiring may be applied even more broadly in the future. An example shown here is the achievement of very high-quality integrated inductors; these may help prospects for complete integration of RF and wireless communications chips onto silicon.

This paper gives an overview of the foundry model and foundry technology trend in the future. The foundry model is a part of the natural trend toward the vertical dis-integration (or horizontal specialization) of the semiconductor industry. Foundry technology is already in the leading pack, and will be on the leading edge from now on. Foundry technology will be market driven toward low voltage (core), low power, high performance, high density, and system on chip (SOC). Examples of leading-edge 0.25 micrometer logic and 0.18 micrometer and beyond process features will be used to illustrate this trend.

ULSI circuit performance is constantly increasing, in speed, functionality and device density. This performance increase is supported by the constant development of new processes and new materials, on new equipment platforms, which support the demand for improved defect density and throughput. A key challenge for equipment infrastructure to continue to support this performance acceleration is the shortening of cycle time for equipment development and new material acceptance.