This paper explores the effectiveness of a proposed methodology for selecting feedback variables for real-time feed-back control (RFC). Both analytical and simulation results are presented. In many manufacturing processes, the important product characteristics cannot be measured in real-time and therefore cannot be directly controlled using RFC. Although the product characteristics may not be fed back, the benefits of RFC, which include reduction of variation through disturbance rejection, may be gained by feedback of process variables closely related to the product characteristics. A general condition under which RFC will reduce process variation, expressed in terms of sensor noise, process disturbance characteristics and process noise, is derived. Generally, process knowledge is used to selected the process variables appropriate for feedback, however in many case this knowledge is not sufficiently quantitative. A methodology which utilizes statistical analysis of experimental data has been developed for the purpose of identifying the best process variables to regulate in order to minimize variation in the product characteristics. The methodology includes the following steps: design of experiments, candidate model selection, final model selection, check for controllability, and verification. An efficient, exhaustive search of all possible regression models which satisfy the constraints imposed by the RFC control problem is used to implement the candidate model selection step. The effectiveness of the methodology is evaluated using simulation. Through simulation a wide range of conditions were explored in a relatively short period of time. Situations considered include various degrees of sensitivity to process disturbance, limitations in sensor availability and variation in the importance of unmeasured process variables.

Fast-ramp vertical furnace technology has been established on the 200-nm wafer platform providing higher capacity production, decreased cycle time and lower thermal budgets. Fast-ramp furnaces are capable of instantaneous temperature ramp rates up to 100 degrees C/min. This fast-ramp technology is now applied to 300-nm wafer processing on the SVG/Thermco Rapid Vertical Processor Vertical Furnace. 300- mm fast-ramp capability using the latest in real-time adaptive model based temperature control technology, Clairvoyant Control, is reported. Atmospheric Thermal Oxidation, LPCVD Nitride and Polysilicon Deposition, and LPCVD TEOS-based SiO2 Deposition results are discussed. 300- mm wafer Radial Delta Temperature dependence on temperature ramp rate, wafer pitch, and wafer support fixtures are discussed. Wafer throughput is calculated and reported. The Clairvoyant Control methodology of combining thermal, direct and virtually-sensed parameters to produce real-tim e estimation of wafer temperatures, thermal trajectory optimization, and feedback to minimize variations in film thickness and electrical properties is presented.

The conflicting demands for finer features and increased production rates in integrated circuit manufacturing have emphasized the need for improved wafer positioning technology. In this paper we present operational test results from a magnetically levitated platen with structurally integrated piezoelectric actuators. The strain based actuators provide active damping of the platen's flexible body modes, enabling increased bandwidth on the mag-lev positioning system. Test result reveal a dramatic reduction in steady state positioning error and settling time through implementation of active vibration control.

With the introduction of high-throughput, multi-arm chemical-mechanical planarization (CMP) tools, a new source of process variation is introduced to the CMP process. These arm-to-arm variations are caused by small differences in the polishing rates of each arm. Modeling the arm-to-arm interactions of a CMP tool allows the application of a model-based, multi-variable, run-to-run control scheme. This control scheme is an optimization-based approach using pilot wafers applied to 'out of control' processes.In addition, this paper outlines a controller that can be applied directly to production wafers. The production-based run-to- run controller allows for monitoring the process through statistical process control methods and utilizes known relationships between product and pilot wafer removal rates in order to keep the process 'in control'. The product-based controller will be automated and deployed in AMD's Fab25- micron facility in Austin, TX using the software developed under the Advanced Control Framework Initiative.

One method to achieve lower process variance is through inter-process feedforward control. There are two problematic issues associated with feedforward recipe adjustment: (1) there is noise in the measurement tool and adjusting for inaccurate measurements could increase the variance; and (2) it is difficult to alter one parameter in a manufacturing process without worsening other key parameters. The first issue is addressed by integrating statistics theory into the controller design. One way to solve the second issue is to constrain the controller to select a recipe form a finite set of pre-qualified recipes. We call this feedforward recipe selection control (FRSC). Each recipe in FRSC has a unique adjustment and, by definition of pre-qualified, every recipe will give acceptable values for all other key characteristics. The goal of this paper is to guide the reader through a complete FRSC design. The modeling data set is from an industrial CD patterning processes. Simulation of FRSC implementation shows a standard deviation reduction of 16 percent. We also derive a re-centering methodology order to place more integrated circuits into the fastest speed grade. Our simulation doubled the number of ICs in this fastest speed grade.

The complexity of semiconductor equipment and processes drives the need for equally complex troubleshooting systems. Advanced data collection software allows the user to collect and store data and review individual wafer information or wafer data trends has become an effective tool for troubleshooting. Situations that are extremely difficult to troubleshoot without the ability to retrieve process data include intermittent equipment malfunctions, problems found during subsequent processing or inspections, and problems detected at probe. Data collection and archiving gives maintenance and engineering the opportunity to analyze the data long after the process is complete. Analysis of the data often leads to solutions that will prevent another occurrence. This paper includes fiber case studies from a previous paper, plus an additional five case studies that are used to display the effective utilization of data collection for troubleshooting complex problems.

Process faults usually lead to changes in the normal relationship among process variables. These changes can be detected by a principle component analysis (PCA) model based on the data from normal batches of operation. Therefore, monitoring process variables via a PCA model may lead to the earlier detection of process fault than traditional SPC method which depends on periodic information from test wafers.However, PCA is a linear method, and does not explain the relationship among process variables with time. Because the relationship among process variables for a wafer processing equipment is both nonlinear, applying PCA method directly to the monitoring of such processes may prove to be difficult. A multi-PCA modeling technique is proposed in our study of process in our study of process monitoring and fault detection for a semiconductor manufacturing tool. A series of local PCA models can be built with each local model only describing a local relationship among process variables at a particular time.During monitoring, if an observation from the k^th sampling time of previous normal runs, this observation can be considered normal. A method is also proposed to eliminate redundant local PCA models. The proposed method has been implemented for the monitored of a commercial Rapid Thermal Anneal (RTA) tool. The RTA process is a typical single wafer process. For the same product, all wafers should be processed according to the same recipe. First, the data from normal lots were collected and verified by wafer electrical test data to be normal data. A multi-PCA model was built based on all data for these normal production lots. In the modeling, only 2 or 3 principal components were necessary for each local PCA model to explain 99 percent variance of each sub-matrix of data. This paper will discuss using Multi-PCA as a modeling method for detecting real-time process variations based on equipment signals, with abnormal process signals being indicated by a single parameter - Squared Prediction Error - from the PCA mode. Issues related to the use of this technique in a state-of-the-art semiconductor fab will also be discussed.

A chemical kinetic rate model for the deposition of titanium nitride films from the surface reaction of tetrakis(dimethyl-amido)titanium (TDMAT) was developed. Without ammonia addition, TDMAT forms a titanium nitride film by pyrolyzing on the hot substrate surface. Experimental data from the applied materials 5000 deposition tool was modeled using a CSTR formulation. With the parameters of the surface reaction model regressed to fit portions of the experimental results, reasonably accurate model predictions over the entire domain of experimental data were obtained.

One of the most widespread uses of polysilicon in MOS devices is as the gate electrode for transistors. The gates described here are processed via a two stage poly deposition. The first stage is a thin gate poly deposition used as an implant screen for threshold adjust implants followed by a thick gate poly deposition. Soon after on- product measurement was introduce at a thin gate polysilicon deposition, QBD failures became the most frequent failure mode. A cross-functional team discovered the wafers failing for QBD were used as on-product measurement wafers at polysilicon deposition. Process mapping revealed the wafer failures for QBD were always loaded directly next to poly dummy wafers during deposition. TEM of nucleation sites disclosed there is a competing reaction between the poly dummy wafer directly above the product wafer and the product wafer. The silane prefers to react on the dummy wafer, leading to less area coverage on the product wafers, which leads to rougher, larger grains. The preclean process for the thick gate poly deposition uses a HF dip. It was proposed that HF was penetrating more easily into the rougher poly grains during the HF dip, damaging the gate oxide, and subsequently causing shorts.

A multistep plasma process based on chlorine and nitrogen chemistry was developed, characterized and optimized to anisotropically etch the metal stack consisting of a thin titanium nitride ARC, aluminum copper tungsten over titanium nitride and titanium, using LRC single wafer metal etcher. The new process must produce selectivities of metal-to- resist and metal-to-oxide under layer (TEOS) better than 3:1 and 8:1, respectively. With the help of design of experiment techniques, multivariable factorial experiments were conducted to determine the optimal processes for the bulk metal etch, barrier metal layer and overetch steps. It was found that the key to control of the metal profiles, CD linewidth and oxide loss is the metal etch selectivities to resist and oxide. Increasing the chamber pressure and chlorine chemistry improves the metal-to-resist selectivity for the bulk etch step. Reducing pressure and increasing chlorine and nitrogen help minimize the CD linewidth and oxide loss during an overetch etch step. In addition, it was found that the changes in other variables such as RF power and BCl3 produce no significant effects on selectivities of metal to photoresist and TEOS oxide.

The continuing trend toward smaller device feature sizes and the associated use of high numerical aperture lenses has decreased the depth-of-focus budget available to resolve critical vias. This problem is aggravated by localized topographical variations in device structure, such as double poly capacitors or EEPROM structures, which can induce excessive vertical variation in via height. Such variation places severe demands on the available focus beget, and can result in localized regions of the die experiencing incompletely formed via structures. Topographical variations in device structure can also induce highly isolated and incompletely formed active area contacts as a result of localized resist pooling. In this situation, the topography usually consists of large double poly structures which surround an active area contact, and induce a dramatic variation in resist thickness over the contact area. This can lead to incompletely formed active area contacts and device failure. In both cases, topography play has a key role in inducing these failures mechanisms. This paper presents two case studies: one involving incompletely formed vias due to topographically induced focus failure, and the other a case study involving a EEPROM contact failure caused by topographically induced resists pooling.

As the device feature size continues to shrink, the restriction of particles size is more critical. More effective tools are needed to identify the shaped and the contents of particles, then take corrective actions. In this paper, the source and formation of the flat type metal residue that cause metal line bridge were identified by KLA scan defect inspector and optical microscope review. The duplication of this flat type metal residue also has been achieved. And the effective monitor tool is provided in the paper to prevent the particle forming.

This article presents a methodology used to obtain nearly identical photoresist thickness and uniformity results from four SVG 8800 coat tracks. The intent was to investigate the impact of equipment deviations on the resist thickness mean. The before-and-after paired comparison experimental design is the method of investigation used. Evaluation techniques include extensive use of the T-test to check the effect of the experiments upon thickness means. Variables in this study include: softbake temperature, cast spin sped, exhaust flow, two spin chuck types, resists sit time in the pump, arm retraction time, and resist dispense temperature. The sample sizes were sets of three to ten wafers per group. The most significant variable found was the arm retraction time. Any delay evaporated the solvent from the resist prior to the cast step resulting in a thicker measurement. Software modification to the arm program eliminated this effect. Additional findings include the effects of resist dispense temperature, resist sit time in the pump and type of spin chuck. A decrease in temperature lowers the resist thickness. Excessive sit time results in thinner resist values and a non-normal distribution of thickness. One chick type had slightly thicker resist values and more variation in thickness.

The etch characteristics of titanium (Ti) film in Cl₂/N₂ plasmas and titanium nitride (TiN) film in Cl₂/N₂/BCl₃ plasmas are examined by design of experiment using central composite-face centered type design and modeled by response surface methodology (RSM). The Ti and TiN etch experiments are carried out in a Lam Research Rainbow 4600 single wafer parallel plate metal etcher. For the Ti etch process, the effects of variation of the process parameters such as Cl₂, N₂ gas flow, RF power and reaction pressure on output responses, etch rate and etch uniformity, are investigated. For TiN etch process, BCl₃ gas flow is added as a factor in addition to the factors listed above. A statistical analysis software package, JMP, is used to design experiment and analyze the results. The factors are normalized with respect to center point for the design and analysis of the experiment in order to compare the relative significance of the model terms. Using the etch rate and uniformity data obtained from the experiment, a quadratic model is developed for etch rate and uniformity for each rate and uniformity data obtained from the experiment, a quadratic model is developed for etch rate and uniformity for each of the films. From the coefficients of the models thus developed, it is easy to determine the relative influence of the first and second order effects of factors, and two factor interactions on the etch rate and uniformity response. Contour plots, which are helpful in determining the optimum process window, are generated for both etch rate and uniformity factors. Addition of nitrogen is found to decrease the etch rate due to dilution effect. The reaction pressure decreases the etch rate probably due to loss of energies of radicals, ions and electrons. Increasing of all the factors except nitrogen flow lead to better etch uniformity. Increase in nitrogen flow is causing poor uniformity probably due to dilution of etchant species leading to across-the-wafer nonuniformity.

In CMOS technology, polycide material is often used to from the gate electrode. This bilayer composed of tungsten silicide layer and of doped polycrystalline layer, preserves a good silicon/oxide interface and has low resistivity. Different processes can be used to deposit the polycide. The first process which is conventional corresponds to a polysilicon deposition in furnace followed by a POCl₃ doping technique. Then the tungsten silicide is deposited. The second process involved a single wafer reactor. It allows to deposit the in-situ doped polycrystalline layer an the WSi_x layer in the same equipment. The aim of this work is to study the impact of these tow processes on the electrical behavior of the EEPROM, more especially on the endurance and on data retention. After the presentation of the fabrication processes, physical and electrical characteristics of both types of devices are discussed. The conventional gate degrades more the cycling performance of the memory cell.

The bitline contact hole and the storage node contact hole of 0.22 micrometers in 1G DRAM device manufacturing of 0.18 micrometers design rule were formed with thin nitride barrier self- aligned contact (TNBSAC) technology. In this work the isotropic dry etching process for the removal of nitride used as an oxide etching barrier in TNBSAC was characterized with respect to the parameters such as O₂/(NF₃ + O₂) flow rate ratio, total flow rate, pressure, chiller temperature. From these tests, an isotropic nitride etching recipe was evaluated as the following: 0.8Torr 900Watt 60NF₃ 140O₂ 10 degrees C, nitride etch rate equals 1200 angstrom/min, selectivity of nitride to middle temperature oxide (MTO) equals 7.2, selectivity to Boro Phosphor Silicate Glass equals 7. When this condition was applied to TNBSAC technology, good etching characteristics was achieved enough to be implemented into device manufacturing like MTO loss less 100 angstrom on wordline corner, no Si substrate damage and contact hole CD bias about 160 angstrom. When the bitline contact hole and the storage node contact hole in 1G DRAM device fully processed form isolation to metallization were defined with TNBSAC technology, the electrical characterization of the bitline contact hole was investigated comparing TNBSAC with sidewall oxide spacer contact (SOSCON) technology. TNBSAC employing the isotopic nitride etching showed the short free connection, the lower junction leakage current and the lower contact resistance compared with SOSCON.

Atomic absorption (AA) spectroscopy was applied to study thermalization of neutral atomic species in a dc magnetron sputtering system. Resonance absorption by Ti atoms was measured with a hollow cathode lamp based AA monitor. Absorption versus deposition rate curves for Ti were obtained at different pressures, ranging from 2 to 38 mTorr, using a quartz crystal microbalance for mass measurements. To study the thermalization of sputtered atoms as a function of distance from the target, the probing beam was positioned at different locations. Experimental data were collected on the influence of argon pressure, sputtering power, and chamber geometry on the absorption signal. The thermalized atoms were found to play a dominant role in determining the sensitivity of AA monitor. Comparisons were also made between the sensitivities of AA monitor for sputtering and thermal evaporation processes. The feasibility of using a tunable diode laser to measure the absorption line profile was established and demonstrated on Zr sputtering process. We found the AA monitor to be a powerful tool for studying sputtering. With proper procedures, the AA monitor can also be used for real-time control of deposition rate in sputtering processes.

A method of Chemical-Mechanical Planarization (CMP) endpoint detection of shallow trench isolation wafer is discussed in this paper. The detection algorithm was developed based on the interferometric intensity modulation of the light reflected from the wafer being polished. The physical model of the process proved to reliably predict behavior of the reflected signal during successive removal of a silicon oxide film and transition into patterned silicon nitride layer. The model calculates film thickness removed from STI wafers with known layer structure, from the reflected signal recorded during CMP process. The in-situ miniature system incorporating fiber-optic coupled diode laser and InGaAs photodetector was successfully implemented for the purpose of Endpoint Detection. On a patterned wafer the system can control nitride thickness removal with a better than 200 angstrom accuracy. The wireless modular design permits real- time simultaneous multiple points operation in a fully automated mode.

A new in-situ tool developed to control accurately the deposited thickness in a multichamber deposition process is presented. It is applied here to a BALZERS multichamber PECVD deposition system for the fabrication of gate structures for flat panel display applications. Based on a simple spectroscopic reflectometer it is composed of a xenon lamp, which is used to illuminate up to 20 optical fibers that enter to each reactor. A very simple optical setup allows illuminating the center of the glass substrates at 87 degrees of incidence from normal. After reflection, all the beams are focused on 20 others optical fibers that enter the same high-resolution prism spectrograph equipped with a multichannel detector. The reactor is selected using shutters. The signal reading and pretreatment is made using a DSP board. Regressions including backface reflection effect are performed in real time. Practical examples are given in the case of SiN_x and amorphous silicon depositions and the performances of the system are discussed.

We present the ability of a focused ion beam system (FIB) to perform as an effective metrology tool. This feature is a benefit in areas where FIB technology is or can be used, or where pre-measurement cross-sectioning is required, such as the case in thin film head trimming, integrated circuit inspection, and micro-electromechanical device (MEMS) development. The FIB is a proven tool for taking high- resolution images, performing mills and depositions, and cross-sectioning samples. We demonstrate the FIB's ability to perform these tasks in a repeatable manner and take accurate measurements independently of the operator. First, we find a quantitative method for analyzing the image quality in order to remove any operator discrepancy. We show that this task can be achieved by analyzing the FIB's Modulation Transfer Function (MTF). The MTF is a proven method for measuring the quality of light optics, but has never been used as a standard in FIB imaging because sub- 100m pitch resolution targets can not easily be fabricated; however, we demonstrate a new method for obtaining the MTF. By correlating changes in FIB parameters to changes in the MTF, we have a FIB image standard, as well as an image calibration tool that is transparent to the operator. Second, we describe how current FIB software can use an automated 'measure tool' to take accurate measurements independently of the operator. We show that when using both these methods, the FIB is a repeatable metrology tool for a variety of applications.

New methods for physical and technological parameters measurements are demonstrated. These methods are based on slow-wave structures application as sensitive elements and are using the dependence of phase velocity in slow-wave structure upon parameters of medium and the distance between slow-wave structure's conductors and between a slow-ave structure and other conductive surfaces. The phase velocity alteration leads to a sensitive element resonant frequency alteration which can be converted into a measuring generator frequency alteration. The peculiarities and advantages of slow-wave structure-based sensitive elements are considered. The possibility of the new method application in microelectronics and other brands of industry are shown. The practical realization of the mentioned above method have confirmed its sensitivity, accuracy and simplicity. It is shown that the use of sensitive elements based on the slow- wave structures is extremely promising in different technological processes and scientific research. Resistivity, permittivity, and permeability, thickness, continuity, linear and angular displacement, vibration, and many other physical and geometric parameters can be measured with high accuracy.

Chamber leakage, transfer shift and particle on lower electrode are the major causes of yield loss during plasma etch process. However, there is still no effective tool for real-time detecting these abnormal chamber conditions. The experiment result demonstrate that the plasma spectrum intensities are strongly correlated to the chamber conditions. One can real-time monitor the chamber conditions by comparing the plasma spectrum intensity with specific control rules. This paper provides an effective method to detect the chamber condition by observing the plasma spectrum intensity.

The influence of Metal (M) and Semiconductor (SC) inclusions on magnetoresistance (MR), Hall effect R and temperature dependence of resistivity (rho) (T) of heterophase materials is investigated for a case, when the signs of magnetoresistance effects for these phases are opposite. According to model used the relative position of signs inversion borders for MR and temperature coefficient of (rho) (T) in coordinates resistivity - phase concentration ought to be independent on configuration of inclusions. For HgSe_1-xS_x crystals in the vicinity of pressure- induced structural phase transition the result of calculations coincide with the experimented data of MR and (rho) (T).

An electromagnetic Lorenz force transducer has been coupled to an Angstrom elastic transducer to form a new compound transducer in which the displacement output is proportional to the current input. It is called the HECTOR transducer and has been built in a form which provides very small displacements in response to modest currents. The transduction effect is shown to be linear and hysteresis- free which provides for accurate calibration of the transducer and highly repeatable performance. The HECTOR transducer can generate reliable and repeatable small displacements in the trans-nanometer region: that is the region characterized by dimensional sizes between about 100nm and smaller than an angstrom. HECTOR's displacements may be used as physical artifacts in the calibration of metrology instruments. This paper describes HECTOR's operating principles and calibration techniques and discuss the accuracy and stability of the artifacts that HECTOR can generate.

The application of polyimide materials on ICs processes are widely accepted. They can be applied as passivation layer, alpha particle barrier, stress buffer and interlayer dielectric, etc. The polyimide materials presented in this article is a negative tone, photosensitive type I-line/G- line compatible polyimide. It is spin-coated onto passivation-etched wafers to form a thick stress buffer with initial thickness 9.5 micrometers after coated and final thickness around 5.0 micrometers after cured. The bonding pad is defined with reversed tone mask compare to passivation mask through exposure and development. In this article, the mechanisms of two types of polyimide defect formation are resolved. One is polyimide residue formed through atomization during rinsing and the other is polyimide bubble take place through chemical reaction of moisture with silicon coupler after coated.

In the modern VLSI, SOG coating followed by SOG etching back process (SOG-ETB) has been an essential process and used for planarization in multilevel integration circuit manufacture. No clean treatment could be done after SOG-ETB process of Inter Metal Dielectric due to the concern of reliability. Consequently, the elimination of the particles of SOG-ETB is the only solution to overcome the production yield impact. The 'random particles' issue means that there were 'high flake type particles' induced at SOG-ETB stages and only dropped on few wafers within one lot. It was hard to catch this issue and to take action instantly. Several investigations were done to find out the source of 'random particles' and eliminate it by adopting an appropriate particle monitoring procedure to reflect the real SOG-ETB process machine status and modifying the replacement cycle of key parts.

The investigation of the conditions for the generation of the misfit dislocations during the dopant impurities in silicon is of a grate interest for the defect control of the highly doped device structures [1 ,2J. Although the solid solubility of boron in silicon is lower than that of the phosphorus atoms, we expect that high densities of misfit dislocations to be induced in silicon even during the boron doping process (prediffusion step). We present in this paper our results concerning the control of the misfit dislocations after the boron diffusion in silicon at high concentrations (higher than the concentration of the intrinsic carriers n1, at the diffusion temperature). The defect control process consists in two main components: (i) the development of suitable criteria to evaluate the conditions for the generation of the misfit dislocations; (ii) the development of suitable techniques to reveal the region of the boron diffusion-induced misfit dislocations in the doped region. We evaluate the theoretical criteria for the generation of the misfit dislocations induced by the boron diffusion in silicon and we compared with the experimental results. We investigate by the bevel-angle selective chemical etching technique (BASCET) and by secondary ion mass spectroscopy (SIMS) the conditions for the generation of the misfit dislocations in the boron-doped silicon by predifflision at 1 100°C for 60mm. As we reported previously [3], the critical conditions for the generation of the misfit dislocation into the phosphorus highly-doped silicon layers can be explicitly given taking into account the behavior of the flat region of the phosphorus diffusion profile during the diffusion in silicon. In this paper we present an analytical model suitable to calculate the critical conditions for the generation of the misfit dislocation during the boron prediffusion in silicon is proposed. However, the substantial difference between the shape of the concentration profiles of boron with respect to that of phosphorus in silicon leads to corresponding differences in the way in which the problem of the misfit dislocation during the boron diffusion in silicon is approached. It is therefore necessary first of all to focus on the specific shape of the boron diffusion profile in silicon and the possibility of the evaluation of its properties.

In order to characterize 300mm wafers at different stages of the IC manufacturing, a new tool based on spectroscopic ellipsometry has been recently developed at SOPRA. This new instrument called SE-300 has some important new features compared to the other ellipsometers of SOPRA or of the competition. First the optical setup allows to obtain very small measurement spots down to 35 X 45 micrometers in polychromatic light to be able to work form deep UV 190nm to near IR; second the combined monochromator/spectrometer is directly setup on the analyzer arm and allows both multichannel and scanning measurements on the same spot. Scanning measurement made with a real double monochromator including prism and grating allows very accurate measurement that can be used to extract optical indices and solve complex multilayer structures. Multichannel measurements are made through a prism/grating spectrometer with quasi-linear dispersion in wavelength. All the elements are fully compatible with the new generation of 300mm wafers. Practical results obtained in a real environment are presented.

In this paper we present a statistical experiment design for stepper NA/PC optimization. The design starts with 2-level 3-factor full factorial. After optimizing ring width, we further optimize NA/PC with a 3-level design. Two responses of DoF and EL are measured using CD-SEM. Process fluctuation is simulated by using wafers with slightly different resist thickness as replication runs. Special stepper jobfile is created top expose different NA/PC settings on the same wafer at adjacent fields in order to eliminate the bias caused by center-of-edge and wafer-to-wafer variation. Production verification of the DOE results is also reported.

Backend metallization processes routinely consist of three separate steps when metallic barrier layers are sputtered: (1) deposition of the primary, conducting metal layer, (2) removal from the deposition system, and (3) deposition of a capping layer of a different metal, usually a metallic anti-reflective (ARC) coating. Physical sputtering systems sometimes are not configured to deposit the metal layers sequentially (insitu) without removal from the system, even though these modern tools have multiple chambers. This paper details how different metallization processes were consolidated to eliminate the air break between the primary conducting layer, typically Al or Cu, and the capping layers. This paper details the motivation, characterization, development, and electrical results of these new insitu processes for separate technologies on an Applied Materials Endura 5500 PVD. The motivation for backend process consolidation consisted of significant cycle time reduction, reduced cost of ownership across multiple tools, and reduced chance of depositing wrong capping layers. Wafer scrap risk and process integration is detailed for developing the insitu depositions for the A1CuW/TiN ARC stack. Optimization and characterization of the multiple step A1CuW deposition has been detailed previously [1] and is used as basis for this work. The concerns for both metal 1 and metal 2 A1CuW layers are described in addition to possible impact on existing photolithography and metal etch processes corresponding to these metal layers. Results show no significant difference in the critical dimensions after develop and after metal etch on both metal layers for the insitu AICuW ITiN ARC process even though there was a 32% increase in the insitu A1CuW ITiN stack reflectivity compared to the standard stack A1CuW ITiN ARC process. Data is presented showing throughput increased by close to 20% using the insitu AICuW ITiN ARC process compared to the standard process for both metal stack layers. Cycle time reduction and reduced cost of equipment ownership was achieved without any decrease in wafer die probe yield or significant change to existing photolithography and etch processes.

This paper discusses an unusual series of problems encountered in etching the poly 1 floating gates of an EEPROM device. Such devices feature two levels of polysilicon: a control gate composed of poly 2, and a 'floating gate' which consists of lightly doped poly 1. The failure modes originates as a result of the highly anisotropic nature of floating gate etch recipe, as well as the unusual implant doping scheme used with this particular device. We experienced a significant yield problem involving the definition of the floating gate which resulted in localized 'pitting' of the silicon adjacent to the floating gate structure. This pitting occurred as a result of an unusual behavior mode sometimes exhibited by etchant ions, and it caused the poly 2 control gate to short to the substrate. This short resulted in a byte failure. The initial solution to this problem eliminated the pitting, but introduce dan unintended degeneration of the side-wall profile of the poly 1 floating gate. This new failure modality generated bit failures. This paper presents a detailed description of both failure mechanisms and the sophisticated four-step etch recipe used to eliminate them. As the importance of non-volatile memory to the semiconductor industry increases, these failure modes will become more commonplace, and the solutions presented here of increasing value.

Historical microprocessor product trends show an increase in product frequency of 1.25x per year and a transistor count increase of 1.4x per year since the early 70's. This trend is forecast to continue over the next decade to the 0.07micrometers generation. To support the trend, challenges in lithography, transistor definition, interconnect system, and manufacturability must be overcome. Solutions to the lithography challenge, will require successful implementation of 157nm optical or next generation lithography. The transistor solution will require integration of sub 2.0nm gate oxides with improved low resistance shallow source-drain technology, advanced channel dopant engineering, and operation at or below 1.0v. Interconnect challenges will require support of 10 or more interconnect layers using low resistivity metalization and reduced epsilon dielectric. Manufacturing challenges require support of larger die sizes, integrate data higher technology complexity, while maintaining lowest possible cost.

Recently, IBM announced the first silicon integrated circuit technology that incorporates copper on-chip wiring. This technology, which combines industry-leading CMOS ULSI devices with 6 levels of hierarchically-scaled Cu metallization, has reached the point of manufacturing, after passing the qualification test required to prove feasibility, yield, reliability, and manufacturability. The discussion of the change from Al to Cu interconnects for ULSI encompasses a wide variety of issues. This paper attempts to address these by way of example, from the broad range of detailed studies that have been performed in the course of developing these so-called 'copper chips'. Motivational issues are covered by comparative modeling of performance aspects and cost. The technology parameters and features are shown, as well as data relating to the process integration, electrical yield and parametric behavior, early manufacturing data, high-frequency modeling and measurements, noise and clock skew. The viability of this technology is indicated by results from reliability stressing, as well as the first successful demonstrations of fully functional SRAM, DRAM, and microprocessor chips with Cu wiring. The advantages of integrated Cu wiring may be applied even more broadly in the future. An example shown here is the achievement of very high-quality integrated inductor; these may help prospects for complete integration of RF and wireless communications chips onto silicon.

This paper gives an overview of the foundry technology trend in the future. The foundry model is a part of the natural trend toward the vertical disintegration of the semiconductor industry. Foundry technology is already in the lading pack, and will be on the leading edge from now on. Foundry technology will be market driven toward low voltage, low power, high performance, high density, and system on chip. Examples of leading-edge 0.25 um logic and 0.18 micrometers and beyond process features will be used to illustrate this trend.

ULSI circuit performance is constantly increasing, in speed, functionality and device density. This performance is supported by the constant development of new processes and new materials, on new equipment platforms, which support the demand for improved defect density and throughput. A key challenge for equipment infrastructure to continue to support this performance acceleration is the shortening of cycle time for equipment development and new material acceptance.