Microelectronics industry leaders routinely name mask technology and mask supply issues of cost and cycle time as top issues of concern. A survey was created with support from International SEMATECH (ISMT) and administered by SEMI North America to gather information about the mask industry as an objective assessment of its overall condition. The survey was designed with the input of member company mask technologists, merchant mask suppliers, and industry equipment makers. This assessment can be used as a baseline for the mask industry and the microelectronics industry to gain a perspective on the technical and business status of our critical mask industry. It should serve as a valuable reference to identify strengths and opportunities and to guide investments on critical-path issues. Questions are grouped into five categories: General Business Profile Information; Data Processing; Yields and Yield loss Mechanisms; Delivery Time; and Returns and Services. Within each category are a multitude of questions that create a detailed profile of both the business and technical status of the critical mask industry.

This work involved a demonstration of the infrastructure and the ability of mask-making equipment to produce 9 inch reticles. While the choices for this particular work made the timing and logistics long and complicated, we find that there currently exists adequate infrastructure to create 9 inch reticles and we have used this ability to produce several demonstration quality examples.

Alternating Aperture Phase Shift Masks (AAPSMs) are becoming increasingly important as a reticle enhancement technique (RET) in meeting the key lithography requirements for the ITRS Lithography Roadmap. Fused silica etch depth is the critical parameter that determines the phase shift and must be monitored closely for depth and uniformity. At present the methods that measure phase-shift and etch depth, such as interferometry, profilometry, AFM, and SEM, are expensive, slow, and/or destructive, making alternate techniques attractive for a production environment. This paper will present a novel technique, which utilizes a special type of broadband spectrophotometry, specifically developed for high-throughput, accurate, and non-destructive real-time measurements of trench depth. The measurement takes only three seconds per measured site, so that a full uniformity map can be obtained in two to three minutes. The technique involves simultaneous measurement and mapping of reflectance (R) and transmittance (T) from 190-1000 nm and analysis based on the Forouhi-Bloomer dispersion equations, to efficiently and nondestructively monitor trench depth. This new measurement system exhibits excellent repeatability, correlates very closely with AFM, SEM, as well as direct phase shift measurements, and has been proven to perform very well in production environments. Data will be presented from the user's (Etec Systems, Applied Materials Mask Business Group) viewpoint.

Synthetic silica photomask substrates are currently manufactured by cutting from glass boules, which are prepared using a flame hydrolysis process. An alternative technique based on sol-gel processing demonstrates several potential advantages in fabricating high quality substrates. This new approach allows near net shape fabrication of synthetic silica photomask substrates, eliminating the need for cutting and grinding. The complex relationship between glass properties and process parameters in the formulation, drying, and sintering steps has been determined, and a repeatable process has been established. The resulting substrates meet all SEMI specifications for ultra-low thermal expansion (ULTE) photomasks for 248-nm lithography. The technology may also be extended to 193-nm and 157-nm photomask substrates. This sol-gel-based process may represent a unique and cost-effective alternative for manufacturing photomask substrates for deep UV lithography.

To achieve and eventually surpass the 90 nm design rules described in the ITRS roadmap, precise control of etch process endpoint is necessary. To this end, the authors have conducted a study comparing various photomask endpoint schemes, including reflectance laser endpoint, traditional optical emission spectroscopy (OES) endpoint, and OES endpoint employing various statistical techniques. A series of experiments were performed to determine the best combination of process and spectrometer to optimize the signal to noise ratio. Using this combination, a series of masks with exposed Cr loads ranging from 0.5% to 20% were etched. Sensitivity (represented by signal-to-noise ratio) and repeatability was analyzed for each endpoint technique. A discussion of the relative strengths and weaknesses of each technique is included.

For today’s advanced reticle production, process bias should be reduced as possible, and be “zero” ideally, because of its negative impacts on CD control and pattern fidelity against minute features. In this paper, blanks with Cr film thinner than 100 nm were examined as promising materials to meet this demand. Results from two aspects, reticle production and lithographic performance, are presented. Dry etching properties such as etching bias, CD Linearity, impact on pattern-pitch were investigated. Thin Cr film blanks showed excellent results in process bias less than 50 % of conventional ones with proper etching conditions. They also showed about 50 %’s decrease of etching bias variations for pattern-pitch with smaller CD error in CD Linearity at the same time. Results of aerial image simulations showed possibilities of them as substitute of conventional binary blanks in ArF lithography. There was no impact of Cr film thinning on depth of focus and optical proximity effect with optimized exposure condition. These experimental results imply that Cr film thickness plays an important role to decide the qualities of reticle CD. Thinner Cr film blanks have capability to realize a 90 nm-node reticle with minimized process bias enough to produce fine OPC features.

CD requirements for advanced photomasks are getting very demanding for the 100 nm-node and below; the ITRS roadmap requires CD uniformities below 10 nm for the most critical layers. To reach this goal, statistical as well as systematic CD contributions must be minimized. Here, we focus on the reduction of systematic CD variations across the masks that may be caused by process effects, e.g. dry etch loading. We address this topic by compensating such effects via design data correction analogous to proximity correction. Dry etch loading is modeled by gaussian convolution of pattern densities. Data correction is done geometrically by edge shifting. As the effect amplitude has an order of magnitude of 10 nm this can only be done on e-beam writers with small address grids to reduce big CD steps in the design data. We present modeling and correction results for special mask patterns with very strong pattern density variations showing that the compensation method is able to reduce CD uniformity by 50-70% depending on pattern details. The data correction itself is done with a new module developed especially to compensate long-range effects and fits nicely into the common data flow environment.

Currently available commercial model-based OPC tools do not always generate layouts which are mask rule compliant. Additional processing is required to remove mask rule violations, which are often too numerous for manual patching. Although physical verification tools can be used to remove simple mask rule violations, the results are often unsatisfactory for more complicated geometrical configurations. The subject of this paper is the development and application of a geometrical processing engine that automatically enforces mask rule compliance of the OPC'ed layout. It is designed as an add-on to a physical verification tool. The engine constructs patches, which remove mask rule violations such as notches or width violations. By employing a Mixed Integer Programming (MIP) optimization method, the edges of each patch are placed in a way that avoids secondary violations while modifying the OPC'ed layout as little as possible. A sequence of enforcement steps is applied to the layout to remove all types of mask rule violations. This approach of locally confined minimal layout modifications retains OPC corrections to a maximum amount. This method has been used successfully in production on a variety of DRAM designs for the non-array regions.

As the industry accelerates the reduction in sub-wavelength device feature sizes, it is necessary that the traditional barriers between design, mask data preparation (MDP), and the lithography process be broken down or eliminated. These processes, which now possess increased levels of complexity and interconnectivity, can no longer work independently but must be linked and all applicable information about the processes propagated upstream. Options associated with phase shift masks, optical proximity correction, increasing constraints for the minimum defect size requirements, improving yield and throughput, etc. have been key to the increased demands placed on the photomask manufacturers. Knowledge of the lithographic performance of a selected option prior to mask build is key to reducing mask cost, improving turn around time and staying on the aggressive path established by the mask user. Integrating CD and lithographic process window analysis with MDP provides a convenient means of helping the mask makers to predict the performance of a mask within the wafer fab. This paper will discuss the integration of CD and lithographic process window analysis tools with CATS mask data preparation software. The benefits of implementing this methodology will be explored and illustrated with data.

Mask data preparation (MDP) systems are becoming more and more complicated due to increasing demand for higher resolution, and more commonly adopted technique of optical proximity correction (OPC). Conventionally, as a standard format to describe mask patterns, GDSII has been widely used in the EDA field as well as in the mask production field. These days, however, GDSII is revealing its disadvantage in terms of efficiency in data compaction. On the other hand, mask pattern data in a variety of formats, including GDSII, are flowing into mask manufacturers, and this is making their process extremely complicated. In this paper, we propose a unified format, tentatively named "GDSII-NEO." GDSII-NEO is designed to retain GDSII upper compatibility in consideration of the utilization of existing GDSII data and to have several times higher compression rate than GDSII. GDSII-NEO can be seen as a multi-purpose format used widely in the EDA and mask field. An intended use, among others, of this format is to describe the pattern data fed into Electron Beam (EB) mask writers.

The continuous tightening of CD and registration specifications demands most advanced metrology equipment and highly sophisticated logistics and measurement strategies. Not only the smallness of structures but also the increasing number of measurement sites is a challenge. Until recently, CD measurements in mask mass production were done at a handful of different positions using mainly optical microscopy. The measurement locations were usually picked randomly according to the visual image and some general rules that were agreed upon between lithographers and the mask shop. In this paper we describe a flow for SEM based CD measurement in automated production. A new type of instances is introduced solely to provide a simple and effective way for transferring the desired measurement locations from design to a mask shop. Therefore, we use the new CATS features that allow highly automated and flexible off-line preparation of measurement jobs. On the KLA-Tencor 8250-R CD-SEM we furthermore utilize its capability of converting CATS output files into fully functional SEM measurement jobs with large numbers of sites and multiple steps of pattern recognition. A comparison of results obtained with the CATS jobs with those of native SEM jobs proves the consistency of data.

As the industry enters the development of the 65nm node the pressure on the data path and tapeout flow is growing. Design complexity and increased deployment of resolution enhancement techniques (RET) result in rapidly growing file sizes, which turns what used to be the relatively simple task of mask data preparation into a real bottleneck. This discussion introduces the data preparation scheme in the mask house and analyzes its evolution. Mask data preparation (MDP) has evolved from a flow that only needed to support a single mask lithography tool data format (MEBES) with minimal data alteration steps to one which requires the support of many mask lithography tool data formats and at the same time requires significant data alteration to support the increased precision necessary for today’s advanced masks.. However, the MDP flow developed around the MEBES format and it’s derivatives still exists. The design community has migrated towards the use of hierarchical data formats and processes to control file size and processing time. MDP, which from a file size and process complexity point of view is beginning to look more and more like the advanced RET operations performed on the data prior to mask manufacturing, is still standardized on a flat data format that is poorly optimized for a growing number of mask lithography tools. Based on examples it will be shown how this complicates the data handling further. An alternate data preparation flow accommodating the larger files and re-gaining flexibility for turnaround time (TAT) and throughput management is suggested. This flow utilizes the hierarchical GDS-II format as the exchange format for mask data preparation. It complements the existing flow for the most complex designs. The introduction of a hierarchical exchange format enables the transfer of a number of necessary data preparation steps into the hierarchical domain. Data processing strategies are discussed. The paper illustrates the benefit of hierarchical processing based on GDS-II files with experimental data on file size reduction and TAT improvement for direct format conversions vs. re-fracturing as well as other processing steps. The implications for the established data preparation approaches and potential alternatives for the communication between the mask manufacturer and the customer will be discussed. The potential for further enhancements by converting to a hierarchical format that has a more efficient data representation than the commonly used GDS-II format will be discussed and illustrated.

This paper proposes a new concept, The Inspection Plan file, which provides a solution for managing the increased complexity that is associated with the Photomask Inspection process. The Inspection Plan gives a statement of intent on how the inspection process should be performed, as distinct from the Inspection Map that is produced as the output from the completed inspection. This is analogous to the construction industry, where Plans represent statements of requirements, which are then followed by Maps that are created as a result of surveying the area. The paper looks at existing management of the inspection process by the use of Do Not Inspect Regions (DNIRs) that provide a Boolean control mechanism using rectangular regions. The suggested Inspection Plan File is a multi-layer database that can consist of polygonal regions. Examples are provided of the benefits of an inspection strategy based on Inspection Plans. The paper provides suggestions for software tool vendors on the capabilities that are required in order to easily generate Inspection Plan files. Some of the suggested techniques are also applicable to the generation of DNIR regions. The paper concludes by giving suggestions to the manufacturers of Inspection systems, on how these systems could make use of Inspection Plan files.

There are a number of factors influencing how integrated circuits are designed and manufactured notwithstanding the ongoing demand for the broader, ubiquitous, multi-functional, uninterruptible and transparent use of such technology. Functionality, speed and power are being compressed into finer, thinner and denser circuit elements the delineation of which requires manufacturing tools to operate at resolutions on the atomic scale and compute engines that render geometric data at rates exceeding tera-pixels per second. The linguistics of the design and manufacturing of integrated circuits is fractious and unruly. There is a common nature to the design and manufacture of integrated circuits but no common structure. This burgeoning confluence of fractious design and manufacturing linguistics, terabyte/second intensive data paths, a finer need to delineate features nearly the size of atoms and the ongoing need to resolve a smaller subset of larger, more complex, design and manufacturing problems with more data and computational power, needs a comprehensive and common data model. The SEMI Universal Data Model is an abstract mapping of the nature and structure of the IC design and manufacturing process. It is a common, bit-efficient, bi -directional, extensible, portable, hierarchical data base and model that expresses the organization, input/output and management of all design and manufacturing data.

In this contribution we will demonstrate how the use of negative tone CAR can significantly improve the CD control of mask layers in which CD is measured on opaque features. A thorough investigation of the individual contributions of sequential process steps in mask making revealed that the final CD uniformity can by improved by 20% when a negative tone resist is used. In case of 50 keV electron beam (EB) mask writing systems, that employ variable shaped beam (VSB) writing, the writing time can be reduced by 40-50 % when a chemically amplified resist (CAR) is applied. Therefore we have evaluated and characterized a commercially available negative-tone CAR. The resist showed good pattern performance down to 150 nm for isolated and semi-isolated opaque lines thus having the ability to form assist bar features. Vertical profiles have been obtained. Line edge roughness (LER) is more pronounced for this material when compared to standard EB resist ZEP 7000. But analysis of CD uniformity (3σ) of 500 nm opaque lines in local area with negative CAR and with positive tone ZEP 7000 showed 4,8 nm and 6,2 nm, respectively. Thus substantiating that the negative CAR is advantageous in terms of opaque line CD control. Regarding soft bake (SB) and post exposure bake (PEB) latitude, the CAR is stable with respect to soft bake temperature variation (3,7 nm/°C). Much more severe is the steep PEB latitude with respect to dose of 0,7-1,3 (μC/cm²)/°C. This requires the use of high precision baking tools for the PEB step. Since all mask blanks have been coated in-house, we have investigated a variety of pre-treatment steps. The influence of each step was characterized by contact angle measurement. We found out that the best results have been achieved when the sequence H₂SO₄/H₂O₂-cleaning-UV/ozone-clean-dehydration bake is applied to virgin blanks as delivered by the blank supplier.

It has long been understood that there is an image fidelity difference between the integrated circuit design pattern and the photomask made from that pattern, largely due to the finite spot size of pattern generators. Furthermore, there are known differences in photomask image fidelity (rounding, jogs, etc.) between e-beam and laser pattern generators. Using a novel technique developed by DuPont Photomasks, Inc. (DPI), actual photomask fidelity has been simulated from design data to produce a more true-to-life representation of the mask. We have performed analytical simulations and printed-wafer measurements on Cypress 100-nm technology designs to determine the differences and effects on optical proximity correction (OPC) of two types of pattern generators: 50 keV e-beam and DUV laser. Both JEOL 9000MV-II+ and ETEC ALTA 4000 images were simulated and saved in GDSII format (“mask-GDSII”). These new mask images were processed through standard lithography simulation software to predict the effects each mask writer has on localized optical proximity effects. Simulations were compared to printed wafer results. A detailed comparison of the accuracy of the mask-GDSII and original design GDSII is performed. Furthermore, comparison of 50 keV e-beam and DUV laser image fidelity is completed, and recommendations are made on how to correct OPC models for each type of photomask generator. Lastly, conclusions are drawn about the use of DUV laser and 50 keV e-beam photomasks.

The first pattern generator, Sigma 7100, using the novel optical SLM (Spatial Light Modulator) technology is now shipping. This paper analyses the writing strategy, how the quality differs from that of a stepper/scanner, and some improvements in development for the next product, here called the SIGMA 7X. The improvements include higher NA, smaller grid size, optimized illumination for reduced proximity effects, and weak phase shifting. The use of embedded addition of corner enhancements is discussed. Finally there is a brief discussion of chrome as the absorber film in binary masks.

Photomask complexity is rapidly increasing as feature sizes are scaled down and as optical proximity correction (OPC) methods become widespread. The growing data content of critical mask levels requires that pattern generator solutions be adapted to maintain productivity. Raster shaped beam (RSB) technology has been developed to enable the production of 70 nm photomasks and the development of 50 nm masks. RSB is built on and extends the capability of the 50 kV MEBES platform. The beam is shaped as it is scanned, printing the mask pattern on a calibrated flash grid. Complex OPC patterns are efficiently tiled by combining a relatively small maximum shape size with a high flash rate of 100 MHz. The maximum shape size and the current density can be adjusted to match a wide set of mask applications. Proximity effects are corrected with dose modulation using a real-time computation.

Laser pattern generators have demonstrated cost-effective reticle manufacturing for critical layers down to the 180nm generation. This paper considers the issues that will need to be resolved to allow laser pattern generators to pattern critical levels for 130nm and 90nm node technology. The performance of current Wafer Optical lithography systems is used as a benchmark. The differences between Wafer and Reticle lithography, in particular, image formation, resist processing, substrate design and etch requirements are all discussed. Areas where wafer lithography expertise can benefit mask makers are discussed and approaches to extend Laser pattern generators down to 200nm feature sizes and below are suggested.

As feature sizes of semiconductor devices shrink, mask errors have a large impact on critical dimension (CD) variation on a wafer and lead to lithography margin reduction. Observed CD error on a wafer is 2 to 4 times as large as CD error on a mask under the low k1 lithography due to mask CD deviation enhancement factor. Mask errors, e.g. CD uniformity, mean to target error, should be controlled and assessed to prevent CD variation on a wafer and lithography margin reduction. Therefore, assessment of mask quality is a critical step in mask manufacturing. This paper proposes a methodology for assessment of mask quality, flexible mask specifications. The methodology consists of two major concepts. One is flexibly selected patterns to guarantee mask quality for each device and each level of devices using full-chip level lithography simulation. The other is flexibly changeable combination of each tolerance for each error component. The validity of flexible mask specifications is proved on masks of a 130nm node memory device. Using the flexible mask specifications, we have confirmed that mask-manufacturing yield rises by 20% for masks of a 175nm node memory device compared with the yield of the masks judged by conventional mask specifications.

With the decreasing gate length and pitch, line-width variations on the mask become more and more important. In low k1 imaging situations often a high Mask Error Enhancement Factor (MEEF) is present and optical proximity correction (OPC) is used to correct for printed CD variation through pitch. In such situations it is often not clear what the impact of reticle line-width variations is on the performance of the litho process and what the interaction is with other process variations present in the litho process. In this manuscript a method will be explained to derive the impact of the reticle CD deviations on the process windows for low k1 imaging. This method will allow varying the various reticle specifications: the CD mean-to-target and uniformity, the writing grid size and the pitch proximity effect during reticle fabrication. By varying these input parameters and looking at the corresponding process window reductions a more founded decision can de made about the specification for these parameters when ordering reticles. After explaining the method also a reality check will be done for a 100nm CMOS process with a modern 193nm resist on a high NA (.63 and 0.75) ArF scanner.

For nonzero mean-to-target (MTT), critical dimension (CD) recovery to the nominal CD in the reference region by simply changing the dose cannot be achieved in the other regions with different pattern densities. The mask error enhancement factor (MEEF) and the exposure latitude (EL) depend on the pattern density, which cause the final CD mismatched to the nominal CDs. The formulaic expression of the mask margin for the MTT and uniformity is constructed as a function of the MEEF, the EL, and the nominal CD tolerance. Line and space (L/S) pattern of 200 nm pitch size and isolated space pattern of 120 nm are designed and chosen as dense and sparse patterns, respectively. Simulation is performed using Gaussian convolution method, and the diffusion length is found to be 40 nm by fitting it to the measured data. The designed L/S pattern and isolated space pattern are exposed on chrome-on-glass mask using ArF scanner with 0.75NA and annular illuminating condition. The nominal CDs of L/S and isolated space pattern are 105 nm and 115 nm, respectively. The MEEF and the EL are measured to be 2.45 and 6.6 nm-cm²/mJ for L/S Pattern, and 1.86 and 8.60 nm nm-cm²/mJ for isolated space pattern, respectively. The summation values of the MTT and uniformity are calculated to be 8.6 nm with the tolerance of 5 nm for both patterns, and 6.7 nm with the tolerance of 3 nm for L/S pattern and 5 nm for isolated space pattern. The mask margin for the MTT and uniformity proves to be changed for the variation of the nominal CD, or the feature size with the nominal CD fixed. By properly optimizing the conditions of illumination condition, mask type to be sued, and the feature size, the allowable mask tolerance for the MTT and uniformity could be increased.

Chromeless phase lithography (CPL) has been shown as a viable technology for 65nm technology node. Unlike alternating PSM, the CPL aerial image is formed by the interference from a pair of symmetrical phase edges. It is thus less vulnerable to mask phase errors and to the mask defect types that are otherwise highly sensitive to asymmetrical phase imaging. Among the various types of mask defects, the quartz bump has been singled out as the phase defects that must be captured and repaired during the CPL mask manufacturing. In this paper, we focus on the CPL mask inspection and repair technologies for the quartz bump defect. Using a set of programmed CPL mask defects, we characterize the quartz defect inspectablity and repair capability. We then use AFM and SEM tools to scan the defect for the precise location and dimension. The FIB induced etching process, gas assist etching (GAE), are used for the quartz bump repair. In order to better control the repairing effect, a multi-pass GAE process was proposed. The defect repair performances were verified by AIMS and resist printing. We show that the quartz bump can be detected using the current state-of-the-art mask inspection tool and most importantly, it can be repaired effectively with minimum or little impact to the printing performance.

Nanomachining is a relatively new technique to the semiconductor industry. This technique utilizes the positional control of an atomic force microscope coupled with RAVE LLC's nanomachining head to perform material removal with nanometer level precision. This paper discusses the benefits of that technology as applied to photomask repair. Specifically, we will show the capability of the RAVE nm1300 to reconstruct completely missing contacts on 193 nm - 6% MoSi phase shift material utilizing both symmetric and asymmetric NanoBit tips. Wafer print test data confirmed the MSM-193 (AIMS)TM data that symmetric NanoBit tips have the ability to consistently produce contacts with through focus critical dimensions within 15 nm (1x) of unrepaired contacts. Experiments show that in order to reproduce the correct through focus behavior, the nanomachined depth into the quartz substrate must be controlled to within 5 nm on the photomask. In addition, 193 nm AIMS data show that placement errors of the reconstructed contacts are less than 15 nm (1x). Throughput and tip lifetime for both tip types on these repairs will also be examined.

Alternating Phase Shift Masks (altPSM’s) are an option for the production of critical layers at the 100 nm technology node and below produced at ArF lithographic wavelength. Successful implementation of altPSM’s depends upon the ability to successfully inspect, disposition and repair defects that occur during the manufacturing process. One technique previously described to improve phase defect contrast was the use of simultaneous transmitted and reflected light. The previously described technique provided for improved phase defect detection in altPSM’s produced for the 130 nm node at a 248 nm lithographic wavelength. This work describes the results from a die-to-die inspection method that improves phase defect contrast in transmitted light for altPSM’s produced for the 100 nm node at a 193 nm wavelength. The improved phase defect detection technique addresses the challenges of decreasing linewidth/pitch and reduced defect phase resulting from the decrease in lithographic wavelength relative to the inspection wavelength of light. The improved phase defect detection method also provides a method to determine whether a defect is a binary, phase bump or phase divot type of defect. Results are compared against the previous inspection methods. A test vehicle for gathering sensitivity performance data is described along with the results obtained from the inspection system.

The paper presents a new technology to inspect alternating phase shifting masks. Instead of finding defects based on a size-dependent defect specification, defects are found according to their impact at the wafer CD result. The inspection methodology used is aerial imaging. Phase effects are taking into account inherently. The main advantage of this method is that only defects, which actually affect the wafer result, will be detected and classified. The paper presents first inspection results on alternating phase shifting test masks designed for the 70nm generation.

Traditionally, mask defect analysis has been done through a visual inspection review. As the semiconductor industry moves into smaller process generations and the complexity of mask exponentially increases, the traditional mask defect analysis method becomes very time consuming. The Automatic Defect Severity Scoring (ADSS) module of i-Virtual Stepper System from Numerical Technologies offers an extremely fast and highly accurate software solution for defect printability analysis of advanced masks such as OPC and phase-shifting masks in a real production environment. In a previous paper [1], we have introduced the ADSS concept and discussed some results for line-space patterns on OPC and non-OPC masks. In this paper, we will discuss the ADSS results for both line-space and contact patterns on attenuated phase-shifting masks (ATTPSM), together with some ADSS results for line-space patterns on binary masks. The ADSS results are compared to wafer results. The wafer exposures were performed using 248 nm imaging technology and inspection images were generated on a KLA-Tencor’s SLF27 system.

Today's reticle inspection tools can provide a wealth of information about defects. We introduce here a system called DIVAS: Defect Inspection Viewing, Archiving, and Simulation that fully uses and efficiently manages this wealth of defect information. In this paper, we summarize the features of DIVAS and describe in more detail PRIMADONNA, one of its components. Current reticle defect specifications are based, primarily, on defect size. Shrinking design rules, increasing MEEF and use of Optical Enhancement Techniques cause size to be an inadequate criterion for disposition. Furthermore, visual disposition of defects is not automated, strictly reproducible, or directly tied to wafer lithography. To compensate for these inadequacies, reticle specifications are set conservatively adding direct and hidden costs to the manufacturing process. PRIMADONNA, utilizing Prolith as the simulation engine, retrieves all defect and reference images saved from a KLA SLF77 inspection tool and processes them through a series of increasingly rigorous simulation stages. These include pre-filtering, aerial image formation, and post filtration. Difference metrics are used to quantify a defect's wafer impact. We will report results comparing PRIMADONNA decisions to manual classifications for a significant volume of inspections. Correlation between PRIMADONNA results and AIMS metrology will be presented.

The semiconductor industry continues to aggressively shrink linewidths and manufacture more closely spaced patterns to improve power and speed performances, as well as increase die per wafer counts. Current development is near 100 nm and high volume manufacturing is commonly near 150 nm. These smaller linewidths and more dense patterns are hampered with new populations of defects that were previously unimportant second or third order effects. As a result, new defects of interest must specifically be investigated, detected, and prevented on the reticles that hold master images of what is being printed. This is often difficult because reticle manufacturing, reticle defect detection, and reticle end-usage (manufacturer) typically spans three corporations. If defects occur on wafers that were not detected with current reticle inspection capabilities, there must be correlation from the printed wafer back to the reticle to assist the reticle supplier in locating the defect and working towards eliminating the problem. In some cases, photo defects may not impact device functionality. As a result closed-loop analyses and actions, which determine whether an event actually causes yield loss, must be developed into the business practices of multiple companies. This paper reports on an inter-company process (ICP) involving Cypress Semiconductor Corporation, Dupont Photomask Incorporated, and KLA-Tencor. The ICP evaluates reticle defects on wafers, their impact on yield, and the transfer of the defect information back to the reticle vendor in an effort to improve overall reticle quality for a 150 nm and beyond semiconductor manufacturing fab.

The applicability of electron-beam induced chemical reactions to mask repair is investigated. To achieve deposition and chemical etching with a focused electron-beam system, it is required to disperse chemicals in a molecular beam to the area of interest with a well-defined amount of molecules and monolayers per second. For repair of opaque defects the precursor gas reacts with the absorber material of the mask and forms a volatile reaction product, which leaves the surface. In this way the surface atoms are removed layer by layer. For clear defect repair, additional material, which is light absorbing in the UV, is deposited onto the defect area. This material is rendered as a nanocrystalline deposit from metal containing precursors. An experimental electron-beam mask repair system is developed and used to perform exploratory work applicable to photo mask, EUV mask, EPL and LEEPL stencil mask repair. The tool is described and specific repair actions are demonstrated. Platinum deposited features with lateral dimensions down to 20 nm demonstrate the high resolution obtainable with electron beam induced processes, while AFM and AIMS measurements indicate, that specifications for mask repair at the 70 nm device node can be met. In addition, examples of etching quartz and TaN are given.

Photomask dimensional metrology in the scanning electron microscope (SEM) has not evolved as rapidly as the metrology of resists and integrated circuit features on wafers. This has been due partly to the 4x (or 5x) reduction in the optical steppers and scanners used in the lithography process, and partly for the lesser need to account for the real three-dimensionality of the mask structures. So, where photomasks are concerned, many of the issues challenging wafer dimensional metrology at 1x are reduced by a factor of 4 or 5 and thus could be temporarily swept aside. This is rapidly changing with the introduction of advanced masks with optical proximity correction and phase shifting features used in 100 nm and smaller circuit generations. Fortunately, photomask metrology generally benefits from the advances made for wafer metrology, but there are still unique issues to be solved in this form of dimensional metrology. It is likely that no single metrology method or tool will ever provide all necessary answers. As with other types of metrology, resolution, sensitivity and linearity in the three-dimensional measurements of the shape of the lines and phase shifting features in general (width, height and wall angles) and the departures from the desired shape (surface and edge roughness, etc.) are the key parameters. Different methods and tools differ in their ability to collect averaged and localized signals with an acceptable speed, but in any case, application of this thorough knowledge of the physics of the given metrology is essential to extract the needed information. This paper will discuss the topics of precision, accuracy and traceability in the SEM metrology of photomasks. Current and possible new techniques utilized in the measurements of photomasks including charge suppression and highly accurate modeling for electron beam metrology will also be explored to answer the question “Has anything really changed?”

This paper presents the use of specially designed electrically testable structures to measure and characterise linewidths on both binary and alternating aperture phase-shifting masks (altPSM). The technique behind the use of these modified cross-bridge structures is explained together with the specific designs used to characterise both dense and isolated features. The practicality of measuring masks with and without anti-reflective chromium dioxide are discussed and the the difference in the repeatability of the measurements is presented. CD SEM measurements of these features are compared with those obtained electrically and an excellent correlation between the electrical dimension (ECD) and the dimension measured both on mask and wafer by SEM is shown.

The new MueTec , an advanced CD metrology and review station operating at DUV (248nm) wavelength, has been extensively characterised in a reticle production environment. Performance data including resolution, measurement repeatability and throughput will be discussed. The system has demonstrated the ability to image 100nm Cr lines and sub-nanometer (3-sigma) long-term repeatability on lines and spaces down to 200nm in size. Metrology capability on contact hole and serif structures will also be discussed. The paper will also introduce the application of a long working distance DUV objective compatible with pelliclised masks. With a 9% EAPSM reticle for 193nm wavelength a very appropriate image contrast was obtained with both objective types, allowing reliable automated linearity measurements on this type of reticle also. In addition to the metrology performance of the tool, its integration into a manufacturing environment will also be described. This will show how the availability of networked co-ordinate data (either in the form of ASCII files or CATS data) and the high-accuracy stage of the tool enable efficient, automated measurement of large numbers of dense features under production conditions.

Rapid changes in the feature size of photo masks have made it clear that there is an obvious limitation to the use of optical measurement tools, and mask makers now have the necessity to use CD-SEMs as a measurement tool for forefront patterns. The level of measurement precision and accuracy required for mask CD metrology has reached a point at which magnification calibration using the standard scale becomes indispensable. Since CD-SEM measurements are heavily influenced by local pattern irregularities compared to optical measurements, however, proper statistical treatment of data is necessary to estimate accurate values. In this paper, the tool repeatability, sample dispersion, line edge roughness amount and tool's long-term precision will be determined by the treatment of numerous measurement data. The general calibration of the tool is done by line pitch measurement of JQA standard, in that case the disagreement between line width measured values and user's desired values could be appeared. In this case we propose the method to change threshold value of measurement, and in this paper the evaluation of this method will be shown.

An overview is given of the achievements on this initiative over the past year. The achieved 1-dimensional (1D) terminology is now published and can be downloaded from the SEMI Standards website. The present focus is on 2-dimensional (2D) terminology. For this purpose a general approach based on area is suggested. Based on this, specific cases such as corner rounding and line-end shortening have been covered. Likewise OPC and contacts become easily assessed. The suggested approach requires overlay of the actual and the nominal pattern. Techniques to do this are discussed. Other qualification techniques, already in use today, such as corner rounding radius, are covered in the present draft also, but they require extensive work to reduce the ambiguity of their application to an acceptable minimum. Another problem tackled, is the coupling between 1D feature size error and 2D characterization. Correction procedures to decouple faulty 1D control from 2D assessment results are proposed. As the suggestion has been made to the task force (TF) several times to use the printability on wafer as a qualification for the mask, motivations are given why it is thought that this is not yet in reach in full, and suggestions are made on the path forward to consider it for later inclusion. It is believed that the general approach based on area is a good basis for such assessment by printability.

NIST is preparing to issue the next generation in its line of binary photomask linewidth standards. Called SRM 2059, it was developed for calibrating microscopes used to measure linewidths on photomasks, and consists of antireflecting chrome line and space patterns on a 6 inch quartz substrate ( 6 × 6 × 0.25 inches, or 15.2 × 15.2 × 0.635 cm). Certified line- and space-widths range from nominal 0.250 μm to 32 μm, and pitches from 0.5 μm to 250 μm, and are traceable to the definition of the meter. NIST's reference value, the definition of the meter, is well defined and unconditionally stable. Any replacement or duplicate NIST linewidth standard will be traceable to this same reference, and thus traceable to any other NIST length standard. Such measurement traceability can be achieved only by evaluating the measurement uncertainty (not just the repeatability) of each length comparison in the metrology chain between the definition of the meter and the NIST linewidth standard. This process results in a confidence interval about the calibration result that has a 95% probability of containing the true value. While the meter (and the μm) are well-defined, the geometrical width of a chrome line with nonrectangular cross section is not, and so the "true value" linewidth must be carefully defined to best meet users' needs. The paper and presentation will describe how these mask features are measured at NIST and how their measurement traceability is accomplished.

We describe the application of a novel imaging technique to ultra-high spatial resolution measurements of photomask phase shift. An Actinix TMT-193 photomask transmission tool has been retrofitted with a breadboard Mach-Zehnder interferometer and ancillary signal detection electronics and software to demonstrate actinic phase shift measurement capability for ArF-generation photomasks. Using a simple proof-of-principle layout, we have successfully acquired high-contrast interference fringe data on ultra-high resolution (250 nm) photomask geometries. Minimum detectable feature sizes are limited only by the resolution of the imaging system. The measurement techniques are suited to both embedded-attenuator and alternating-aperture phase-shift masks, and may be directly applied to F2-generation mask tools. Engineering advances in the laser source will increase measurement precision to the 0.4° level as called for in the 2001 ITRS. We discuss the tool architecture and measurement method, and present recent results of phase scans performed on a customer-supplied MoSi EAPSM.

As the fabrication density increases in semiconductor manufacturing processes, cost effective determination of the exact dimensions of various device-interconnects becomes a critical issue. Single detector based critical dimension metrology systems are attractive due to cost effectiveness. Yet, deducing dimensions like sidewall curvature and 3D shape of the semiconductor surface are quite difficult using a single detector system. Non-destructive metrological systems are also very desirable in evaluating critical dimension and manufacturing error because they are inexpensive compared to multi-detector systems. In our paper, we build upon the physical modeling approach to modify a classical shape from shading algorithm to reconstruct the 3D shape from a single non-stereoscopic SEM image. Our ultimate aim is to design an efficient real-time, non-destructive CD-SEM system using a single detector. Appropriate reflectance function is utilized for low-excitation SEM imagery for reconstructing the depth map of the surface using the shape from shading algorithm. In this paper, we present the results from low-excitation SEM reflectance model used for SFS approach. We compare the results with a standard SFS algorithm that uses Lambertian reflectance model. We also discuss the advantages of this computer vision based approach compared to other destructive CD-SEM technologies.

Fabrication of low defect density mask blanks remains as one of the key challenges to commercialization of Extreme Ultraviolet Lithography (EUVL). A low defect deposition process for EUV-reflective Mo/Si multilayers has been developed on 200mm silicon substrates because of the availability of sensitive, fast defect inspection tools for wafers. A defect level of 0.05 defects/cm² at 90 nm defect size detection threshold can now be achieved repeatedly on wafers. We upgraded the low defect multilayer deposition (LDD) system to allow coating of standard format 152mm square mask blanks. Mask blank defect inspection was performed at IBM with a typical sensitivity of 100 nm PSL equivalent. We used the single reticle SMIF pod (RSP) standard both for clean, automated handling and for shipping of the mask substrates and blanks. The added defect level during shipping was improved to 0.02 defects/cm². We achieved a process-added defect density of 0.38 defects/cm² on a lot of 5 blanks, which was the same defect level as on wafers coated before and after the blanks. We also improved the reflectance and thickness control on blanks to achieve 66.5% EUV reflectance, and a thickness uniformity of 0.07% P-V or 0.04% rms. The improved reflectance and uniformity meet the SEMI P38 specifications for EUVL mask blanks. We have discovered no differences in defect levels or film quality in the coating of standard square format as compared to silicon wafers.

Extreme ultraviolet lithography (EUVL) is the leading candidate for next generation lithography with the potential for extendibility beyond the 50-nm node. The inspection contrast of DUV and 193nm optical reticles is essentially 100%; however, EUVL reticles are reflective in nature and do not allow for transmissive inspection. The Mo/Si multilayer (ML) mirror has a reflectivity of 55-60% with 257nm illumination. The reflectivity of the multilayer at the inspection wavelength dictates that the patterned areas of the mask must be dark to achieve high inspection contrast (i.e., 0% reflectivity at the inspection wavelength). Furthermore, the reticle should retain the same tone during the pre-repair stage and the final reticle stage to allow reuse of inspection algorithms and easier defect repair verification. The use of an anti-reflection coating (ARC) on a TaN absorber has been shown . This article will describe additional options for a wide range of anti-reflection coatings and their impact on the design and fabrication of the EUV absorber stack. Both experimental and modeling results will be presented for different absorber stack configurations.

EUV mask blanks consist of two thin film systems deposited on low thermal expansion 6 inch substrates (LTEM). First there is the multilayer stack with around 100 alternating layers of elements with different optical properties which are topped by a capping layer. The absorber stack which consists of a buffer and a absorber layer is next. Here a minimum absorption of EUV light of 99 % is required. The stress in both layer systems should be as low as possible. The reduction of defects to an absolute minimum is one of the main challenges. The high-reflective Mo/Si multilayer coatings were designed for normal incidence reflectivity and successfully deposited on 6-inch LTEM substrates by ion-beam sputtering. X-ray scattering, transmission electron microscopy and atomic force microscopy were used for characterization of the multilayer interfaces and the surface morphology. The results are correlated to the measured normal incidence reflectivity using synchrotron radiation at the "Physikalisch- Technischen Bundesanstalt" (PTB) refelctometer at BESSY II, Berlin, Germany. A high resolution laser scanner was used to measure the particle distribution. First multilayer defect results are presented.

EUV masks are exposed at a wavelength of 13.4 nm, but patterned mask inspection will be in the wavelength range of 157 nm to 257 nm. This large mismatch in wavelength raises questions as to whether the defects that are found in inspection will be the defects that print in a EUV exposure tool. This paper addresses part of this question by considering how small certain nuisance defects must be in order to not limit the optical inspection tool’s sensitivity. That is, the tool must be capable of finding critical printing defects and must not find nonprinting defects. A nuisance defect is considered to be one that the inspection tool may be sensitive to, but will not print on a wafer. We have used a 3D Maxwell equation simulator to simulate the inspection images obtained for a variety of nuisance defects of different types and sizes. We have done these calculations assuming that the EUV lithography will be performed at mask dimensions of 200 nm lines and spaces with a 4X mask, so the features would print at 50 nm lines and spaces. We have determined the critical size of such nuisance defects to be 40nm or larger, depending on defect type. Nuisance defects larger than about 40 nm square may limit the inspection tool’s sensitivity to printing defects. The ITRS roadmap specification for patterned defects at the 50 nm node is 40 nm. Therefore, the limit in size for such nuisance defects is not more stringent than the limits that must be met to match the patterned defect size specification. This work should provide guidance in developing a EUV mask specification that ensures that inspection tools will be able to meet the needs of EUV lithography. This work has been sponsored in part by NIST-ATP Cooperative Agreement #70NANB8H44024.

Extreme ultraviolet (EUV) multilayer defects (phase defects) are a defect type unique to extreme ultraviolet lithography (EUVL) masks. A manufacturable inspection capability for these defects is key to the success of EUV lithography. Simulations of EUV scattering from multilayer defects suggest that defect printability is related to the phase error induced by the defect, which is in turn strongly coupled to the size of a multilayer surface protrusion or intrusion. We can adopt a strategy of measuring the multilayer surface to detect phase defects. During the past year a working group composed of members of Intel Corporation, Lawrence Berkeley and Lawrence Livermore National Laboratories, and International Sematech searched for a commercial tool for EUVL mask substrate and blank inspection. This working group established the tool requirements, methodologies for tool evaluation, collected data and recommended a supplier for further development with International Sematech. We collected data from several vendors and found that a multibeam confocal inspection (MCI) system had a capability significantly better than the tools used today. We will present our strategy, requirements, methodologies and results. We will discuss in detail our unique programmed substrate and multilayer defect masks used to support the tool selection, including their actinic characterization. We will present data that quantifies the inspection capability of the MCI system.

The imaging performance of non-planar topographies in EUV masks for both partially repaired defects and non-planar attenuating phase-shifting masks made with repair treatments are evaluated using rigorous electromagnetic simulation with TEMPEST. Typical topographies produced by treatment techniques in the literature such as removal of top layers and compaction produced by electron-beam heating are considered. Isolated defects on/near the surface repaired by material removal are shown to result in an image intensity within 5% of the clear field value. Deeply buried defects within the multilayer treated by electron-beam heating can be repaired to 3% of the clear field but over repair can result in some degradation. Compaction from a 6.938 nm period to a 6.312 nm period shows a 540° phase-shift and an intensity reduced to about 6% suggesting such a treatment may be used to create attenuated phase-shifting masks for EUV. The quality of the aerial image for such a mask is studied as a function of the lateral transition distance between treated and untreated regions.

Extreme ultraviolet lithography (EUVL) is a leading next generation lithography technology. The mask blank for EUVL consists of a low thermal expansion material substrate having a square photomask form factor that is coated with Mo/Si multilayers. One of the challenges in implementing EUVL is to economically fabricate multilayer-coated mask blanks with no printable defects. The starting substrates, due to the required tight specifications of flatness and defects, might have a very high manufacturing cost and hence a method to recover these substrates for reuse without compromising the properties will enable a lower cost for the masks. This paper details a potential approach to remove the damaged multilayers from the substrates without compromising the morphology and characteristics of the starting substrate. Furthermore, the process is applicable to optical elements of the EUV projection optics system that have reflective Mo/Si mirrors of various shapes.

Using TaN as extreme ultra-violet lithography (EUVL) mask absorber has been previously explored in wafer format. Due to substrate material difference between the square mask format and Si wafer format, e.g., electrical conductivity and thermal conductivity difference, etc., the etch process does not behave the same when mask substrate switches from the Si wafer to the square quartz substrates. With low thermal conductivity on quartz material and no backside cooling, mask etch prefers low power as compared to the Si wafer etch. In the study, we found that for a given source and bias power, the cooling of the substrate plays a role in TaN etch rate and selectivity to the buffer oxide layer. In this paper, we will present detailed study and comparison of TaN EUVL mask absorber etch characteristics for both the Si substrate and the square quartz substrate cases. The effect of source power, bias power, and backside cooling will also be discussed. The etchers used in study to etch TaN film on the wafer substrate and on the square format mask substrate have the similar configuration. With the optimized etch process, we have achieved good TaN etch profile with high etch selectivity to SiO₂ buffer layer on the square quartz mask substrate.

We discussed the following topics at the panel discussion of Photomask Japan 2002. 1) Pushing the limit of ArF lithography: How far ArF lithography will extend? 2) Current status and issues for F₂ lithography, 3) Current status and issues for EPL, 4) Current status and issues for F₂ and NGL masks, 5) Lithography tool selection from 90- to 65- nm nodes. ArF lithography could extend to 65-nm node by using alternating phase shift masks. F₂ lithography and EPL are not yet established and we need to solve many issues for practical applications. The choice of lithography tools in 65-nm node depends on devices and layers. Multiple lithography tools might be used in 65-nm node.

Several significant technical issues are associated with the current anodized aluminum photomask frame. These problems will become more acute as shorter wavelengths such as 193 nm and 157 nm become standard. For example, it is difficult to purge the pellicle space, and the non-porous nature of the aluminum frame can lead to pressure-induced film breakage. In addition, the thermal expansion behavior of aluminum does not match that of the silica substrate, which can lead to pattern distortion or bending of a hard pellicle film. Proposed solutions such as a perforated silica frame or a porous stainless steel frame may address some of these issues, but a complete solution has not been forthcoming. A porous silica frame technology based on sol-gel processing may eliminate concerns associated with the lack of porosity in the stainless steel frame, as well as thermal expansion mismatch problems. Several additional advantages may also be realized, including the removal of organic contaminants from inside the pellicle space, filtration of particulate contaminants, and stability under aggressive cleaning. This approach to a porous silica frame may help enable a cost-effective route to more rapid commercialization of shorter-wavelength microlithographic processes.

The worldwide first Aerial Image Measurement System (AIMS) for 157 nm lithography has been used to measure binary chrome and attenuated phase shift masks at 157 nm wavelength. The AIMS measurements were done for line structures from 200 nm up to 400 nm and for 500 nm contacts. Through focus series have been conducted to calculate the process windows for various structures and feature sizes.

Defect formation on advanced photomasks used for DUV lithography has introduced new challenges at low k₁ processes industry wide. Especially at 193-nm scanner exposure, the mask pattern surface, pellicle film and the enclosed space between the pellicle and pattern surface can create a highly reactive environment. This environment can become susceptible to defect growth during repetitive exposure of a mask on DUV lithography systems due to the flow of high energy through the mask. Due to increased number of fields on the wafer, a reticle used at a 300-mm wafer fab receives roughly double the number of exposures without any cool down period, as compared to the reticles in a 200-mm wafer fab. Therefore, 193-nm lithography processes at a 300-mm wafer fab put lithographers and defect engineers into an area of untested mask behavior. During the scope of this investigation, an attenuated phase shift mask (attPSM) was periodically exposed on a 193-nm scanner and the relationship between the number of exposures (i.e., energy passed through the mask during exposures) versus defect growth was developed. Finally, chemical analysis of these defects was performed in order to understand the mechanism of this “growth”.

ASIC companies face consistent pressure to reduce cost, improve quality, and decrease the time to production for reticles used in integrated circuit fabrication. In order to meet these objectives, the Reticle Engineering group at LSI Logic has developed an efficient and accurate defect control methodology. Three case studies in this paper highlight a unique defect management strategy. The scenarios describe rejecting a reticle to the vendor, releasing a reticle to the fab while deeming a defect innocuous, and tracking a reticle through production with a known yield impacting defect. The defect management solutions highlighted in this paper include a web based defect classification and disposition system to supplement the Lasertec MD2000 die to die inspection tool, virtual inking of affected die, and a production process flow for defect verification on silicon wafer prints. Quantitative results are shown, illustrating the elimination of vendor induced repeaters, improvements in baseline defect density, and improved cycle time for defect analysis and inspection flows.

For sub-0.13um lithography, attenuated phase shifting mask (AttPSM) with optical proximity correction (OPC) is reported as one of the potential methods to achieve manufacturable process by using 248nm exposure wavelength. Unfortunately, the low-k1 imaging process in 130nm lithography imposes much more stringent requirements on defect repair, especially on AttPSM reticle. Therefore, the imperfect repairs will have a significant impact on wafer process window due to quartz damage and phase distortion caused by Ga+ ion stain removal and added carbon material, respectively. In this paper, we have prepared AttPSM test masks having programmed defects with various opaque defects. Each defect area was inspected with KLA-Tencor's SLF27 inspection system to acquire defect coordinates and image, simulated with AIMS to assess the intensity and transmission loss induced by repair process. All of masks were made by DuPont Photomasks Taiwan (DPT) by using the Jbx9000MV2 E-beam writer and dry Chrome etch process. All lithographic experiments were performed on 300mm wafer using high NA ASML AT750S scanner and high contrast CAR resist. In this study, we have focused on the impact of quartz damage and phase error on wafer process window by comparing the wafer CD and pattern profile through focus. In order to establish a efficient way to perform effective judgement on repair defect between mask shop and wafer fab, both AIMS and wafer results will be compared and correlated.

This paper reports on reticle defect printability for the 100nm design rule using 193nm lithography, off-axis illumination and a binary reticle with optical proximity correction (OPC). It is part of a systematic assessment of the impact of reticle defects on the printed image. In previous work [1, 2] we concentrated on the printability of both hard and soft defects additive to the Cr pattern. Here we widen the scope to missing Cr defects, such as a divot in the main line. The printing experiments are performed on 193nm-exposure tools using a numerical aperture (NA) of 0.63 and 0.75. In a simulation study based on aerial image assessment, the printability of defects of various area, phase, transmission and shape is evaluated for the two different NA-settings. A quantitative comparison between predicted (by aerial image simulations) and printed linewidths is made. It is shown that the correlation can be further improved by implementing the actual reticle feature contours in the simulation analysis instead of the design. Furthermore, we present a comprehensive table classifying the various defects based on their printability impact.

A systematic method for the model-based optical proximity correction in presented. This is called optical proximity effect reducing algorithm (OPERA) and has been implemented to TOPO, an in-house program for optical lithography simulations. Comparing simulational results as well as experimental results, we found that OPERA is not only suitable for shape restoration but also for resolution enhancement. However, the resulting optimized patterns have a high degree of complexity and this brought up a number of issues for mask manufacturing. First, data volume and exposure time were dramatically increased for conventional e-beam file formats. This was solved by using the MODE6 format that preserves data hierarchy. Second, due to excessive shot divisions, a variable-shaped beam machine could not finish the exposure process. A raster-scan beam machine successfully finished the exposure. Finally, a die-to-die inspection was performed but many false defects that do not affect wafer printing were defected. This will be solved by a new type of tool that inspects a mask by evaluating its aerial image.

Test structures for measuring polarization effects in the illumination, high-NA imaging, and resist coupling are introduced. Specifically, polarization bars are used to transform the mask into a precision instrument capable of monitoring polarization imbalances in the illumination system and to enable studies of both high-NA and polarization dependent resist coupling effects. Critical issues dealing with mask fabrication are addressed. Bar and gap tolerances are investigated to understand uniformity effects on polarization. While the total relative open areas between two polarization bar regions should be kept to within 1% of each other for good polarization uniformity, polarization bars are quite robust to average mask writing errors when the gap widths are kept small (<50nm). Major improvements in the polarization ratio of chrome masks are possible by using materials with a real part of the refractive index near 2.

193nm lithography is very likely to be the pattern transfer method of choice for 65nm technology. This means lithography with a k1 factor in the range of 0.3, so strong resolution enhancement techniques (RET) are necessary. Until recently, alternating Phase Shift Masks (alt.PSM) seemed to be the only viable option. Rather stringent layout restrictions, complex mask manufacturing, and the throughput loss due to the required double exposure make this option rather costly. Double exposure of chromium masks or halftone (embedded) PSM with dipole illumination (DDL), or single exposure of chrome-less PSM (CPL) are evaluated as alternatives with proven resolution for the minimum feature size. Both techniques need sub-resolution features to compensate for their sub-optimum performance on either isolated lines or on lines of about twice the minimum width (in case of CPL). To linearize such highly non-linear pattern transfer processes, model-based Optical Proximity effect Correction (OPC) is mandatory for both options. This paper demonstrates the automated generation of the basic mask writing data for both DDL and CPL for arbitrary layouts, followed by model-based OPC, using Calibre for both steps. Sufficient pattern fidelity and pattern robustness (over a 300nm defocus range) has been shown for a gate/polysilicon layer of a 65nm layout. The results were obtained using masks with reasonable mask specifications.

During the development of process generations with critical dimensions (CDs) around or even far below the wavelength used for printing, the wafer exposure step has become more and more complicated due to the non-linearities that occur within this sub-wavelength regime. These non-linearities give rise to a variety of optical-proximity effects (OPE) that must then be corrected for (optical-proximity correction, OPC). At the same time, the reticle errors are consuming a larger part of the total error budget on the wafer than we have seen in the past. As a consequence, detailed assessments of the reticle quality are gaining more importance and the average number of measurements for qualification of a high-end reticle is rapidly increasing. Within-die CD measurements are becoming common practice for such reticles. Quite often these measurement points are selected randomly. However, regions within the design with relatively low aerial-image contrast during imaging will be subject to the largest amplification of the mask-errors (highest Mask-Error-Enhancement Factor, MEEF). In this work a solution is presented in which measurement points with high MEEF-values can be selected from any given layout data. The method is embedded into the standard mask data preparation flow using CATS. Focus is on the automation necessary to generate set-up files for CD metrology tools, such as the Leica-MueTec M5k. The methodology has been applied in a CMOS volume production site.

A new methodology for completely phase-shifting a poly layout without creating local phase conflicts was proposed for lithographic techniques combining one phase-shifting mask and one binary mask exposure. Critical and non-critical areas of the layout are identified and phase conflicts are avoided by splitting the shifter regions from non-critical areas to non-critical areas without crossing critical areas. The out-of-phase splits of the shifter regions are removed using the binary exposure. Simulation results and experimental data collected for 90nm technology node show no sign of process latitude loss around the areas where the shifters are split. The overlay latitude is commensurate with 90nm technology scanner requirements (tool to itself). For 65nm node, we have identified certain types of cuts that will be forbidden (or at least highly undesirable) during the generation of the phase-shifting layout; this is primarily the case for cuts in “elbow” structures which exhibit limited process latitude. Other cuts like line-end cuts will have to be modified. Mask corner rounding effects were evaluated. Up to 80nm rounding does not create any significant change (below 2nm CD change at 1X) in the aerial image simulation as compared to the case where no rounding is assumed.

Chrome Less phase lithography (CPL) may be the crucial technology to print 100nm node and below. CPL can apply to various design layers without causing phase conflicts, while phase edge phase shift mask (PEPSM) is beneficial for specific pattern configurations and pitches. Therefore, we tested the feasibility of CPL including phase grating and hybrid CPL. And we tested the two types of CPL such as mesa and trench structures to decide the proper shifter forming method. We evaluated pattern fidelity of CPL using simulation, aerial image measurement system (AIMS) and wafer printing. Finally, we will compare the optical performance between CPL and PEPSM for 100nm node SRAM gate.

The application of Chromeless Phase Lithography, or 100% transmission attenuated PSM, has been used to demonstrate the potential for achieving quarter-wavelength optical lithography (0.2k₁). As the demand to image sub-100nm features reaches to the semiconductor fabrication lines, the need for a robust lithography process capable of meeting high volume requirements is becoming more and more critical. The requirements for high-volume, low-k₁ semiconductor manufacturing go beyond wafer imaging technology capable of the process latitude needed for lithography, but also includes data prep software that is capable of applying the details of the imaging technology to the design data, correcting for optical proximity effects, and outputting the necessary mask pattern data. It is also necessary to have a reticle manufacturing infrastructure capable of supporting large volume production with reliability and reasonable turn around time. CPL technology has, by its nature, many elements that make it a strong candidate to meet mass production requirements for 65nm semiconductor technology products. Most important, CPL achieves the resolution enhancement by using a single reticle and does not require a second exposure with a trim mask. The CPL reticle is a variation of the attenuated phase shifting mask, and data preparation for the reticle manufacturing is very similar to what is needed for high-transmission attenuated PSM. It will be shown that as a result of the 100% transmission, the MEEF for CPL masks is very small and in some cases approaches zero. This allows for much larger CD tolerances for the reticle but results in significant limitations on correcting optical proximity effects by using CD bias alone. Methods for correcting through-pitch CD variations with the use of novel CPL pattern designs, bias, and scattering bars will be presented and correlated to wafer imaging results. These results will demonstrate the ability to control through-pitch CD's while maintaining the beneficial MEEF characteristics of CPL. Experimental results using a CPL reticle designed and manufactured for 65nm lithography exposed on an advanced 193nm ASML /1100 wafer scanner will be presented and discussed.

A simple method for minimizing the glass etch non-uniformity in the Etec Systems' Tetra etch tool will be presented along with etch rate performance stability results. In this triple etch process, the final phase uniformity was improved from ± 5 ° to ± 1.3 ° phase shift at 248 nm without changing either processing chemistry or any other process parameters. The procedure used to obtain this improved uniformity as well as maps illustrating the depth distribution over the plate after each step will be given.

CD uniformity and MTT (Mean to Target) control are very important in mask production for the 90nm node and beyond. Although it is well known that baking temperatures influence CD control in the CAR (chemically amplified resist) process for mask patterning, we found that 2 other process factors, which are related to acid diffusion and CA- reaction, greatly affect CD performance. We used a commercially available, negative CAR material and a 50kV exposure tool. We focused on the baking process for both PB (Pre Baking) and PEB (Post Exposure Bake). Film densification strength was evaluated from film thickness loss during PB. Plate temperature distribution was monitored with a thermocouple plate and IR camera. CA-reactions were also monitored with in-situ FTIR during PEB. CD uniformity was used to define the process influence. In conclusion, we found that airflow control and ramping temperature control in the baking process are very important factors to control CD in addition to conventional temperature control. These improvements contributed to a 30 % of reduction in CD variation.

KRS-XE, a high performance chemically amplified photoresist designed specifically for e-beam mask making applications, has been enhanced to achieve reduced “footing” on chrome oxide surfaces while still maintaining the original lithographic characteristics that make KRS-XE a promising mask making candidate. These attributes include high resolution, superior bake latitudes, high vacuum stability, coated shelf life of greater than 2 months, and, most notably, the absence of a post exposure bake. In conjunction with the footing reduction the requisite sensitivity requirement of <10uC/cm2 with 50 keV exposure tools has been achieved while retaining the robust process latitude previously reported for this resist. Through a careful study of the photoresist formulation components a route to the ultra-high sensitivity of <2.5uC/cm2 at 50 keV has been elucidated which will further enhance throughput, decrease heating effects, and potentially be a suitable resist for e-beam projection lithography (EPL).

The advanced photomask dry etching system using neutral loop discharge (NLD) has been thought as a promising candidate for the next generation technology, because the NLD plasma has a capability to control the plasma distribution and density. In previous work, we improved CD uniformity for 130nm node technology using the neutral loop modulation etching technique. However, 100nm node lithography requires tighter specification, thus we set a target to achieve CD accuracy of 6nm (3 sigma) by improving CD uniformity and loading effect of the NLD dry etching system. First, we changed the system configuration: exhaust place, reactor size, and electrode shape. Especially, by optimizing the antenna configuration, we improved the unevenly distributed plasma. Additionally, we introduced a new etching technique to reduce CD shift from resist profiles by enhancing Cr/Resist sensitivity. Consequently, the NLD dry etching system for 100nm node technology was confirmed the effectiveness to improve CD performance using the above techniques.

Chemically amplified resist (CAR) provides superior lithographic performance compared to traditional e-beam resists in production maskmaking. Parameters benefiting the most are contrast, resolution, and sensitivity. In spite of CAR's advantages, defect control and tighter 50KeV e-beam CAR process restrictions are significantly more critical thanks to smaller geometries, tighter CD specifications, and optical proximity correction (OPC) for 90nm node mask technology. Among defect root causes, resist development is considered to be the one of the most important steps because post-development residue can generate printable defects on finished masks. We investigated the CAR development process across different resist development methods, such as binary and fan-type nozzle spin spray, and puddle development. Several high density binary and embedded-attenuated phase shift masks (EAPSMs) with 70% clear area in the main pattern field were evaluated in an effort to identify and contain post-develop defects in a typical mask production flow. Development step process residue was examined at the after-develop inspection (ADI) step and scanning electron microscopy (SEM) was used for individual defect review. The KLA-Tencor SLF77 TeraStar inspection tool was used to inspect patterns after the development, Cr/MoSiON layer dry etch, and clean steps. The effectiveness of the various CAR development methods has been also studied following development, dry etch, and cleaning inspection by using identical binary and EAPSM masks from production. The mechanism and defect source during the stepwise process and inspections were scrutinized and discussed. Experimental results showed that stepwise process inspection was effective in identifying defects and their sources to prevent defects, and in optimizing each process step. It was found that CAR development and dry etch processes are the most important process steps to control defects in CAR-based mask production. Suggested optimized develop process parameters for 90nm-node mask

Writing fogging effect in chemically amplified resist process makes critical effect on global CD distribution in the advanced 90nm node photomask with higher pattern density and smaller geometries. High contrast feature of chemically amplified resist makes difficult to correct the global CD uniformity in resist develop process compared with conventional ZEP resist. In this paper we examine the fogging effect in the combination chemically amplified resist with 50KeV writing tool and the consequential problem for production mask with higher pattern density. We will present the feasibility of the global CD uniformity correction technique in post exposure baking process using gradient temperature hotplate.

Demands on critical dimension specifications increase with the continuous shrinking of design rules. In order to meet sub-0.13μm specifications with precise process control, a better understanding of the etching chemistry and surface reactions need to be achieved. Optical emission spectroscopy (OES) is frequently used in the photomask community as a diagnostic for calling endpoint, but is often underutilized in process development. In-situ measurements, like OES, need to be utilized and correlated to post-etch metrology measurements in order to provide a larger picture of the etch process. In this paper, OES is used to characterize and monitor chrome etch processes on the Etec Systems Tetra photomask etch chamber. Changes in process conditions, such as source power, He percentage, pressure, and Cl₂:O₂ flow ratios have been captured by time-averaged optical emission traces. The OES data of the plasma, along with SEM pictures of line profiles, are used to gain insight in process optimization for the etching of chrome.

There are an increasing number of microlithography applications such as advanced packaging, nanotechnology and thin film head production that require the use of thick photoresist materials. The exposure dose requirements for these applications dramatically increase as the photoresist thickness increases. For example, some positive acting novolak photoresists require exposures in excess of 5000 mJoules/cm² for 100 μm thick films. When a single reticle is used to pattern many wafers, a significant amount of light and heat energy is transferred from the lithography tool illumination source to the pellicle protecting the reticle image. In high volume production environments, a pellicle can be subjected to accumulated dosages exceeding 500 kJoules/cm² within a matter of weeks. Because thick photoresist applications benefit from using 1X broadband steppers with high wafer plane irradiance, life-testing results were reviewed for broadband pellicles designed for maximum transmission at g, h and i-line wavelengths of Hg. Historically, pellicle lifetime testing was typically carried out only to approximately 500 kJoules/cm² . While this test limit may have been sufficient for thin photoresist applications used in semiconductor applications, longer lifetime studies are required to determine pellicle durability for thick photoresist applications. In this study, life testing was performed on multiple pellicle films designed for broadband illumination, including nitrocellulose, cellulose acetate, cellulose ester and fluoropolymer films. Spectroscopic transmission at g, h and i-line was first measured on unexposed pellicles. The pellicles were attached to test reticles and exposed to high-energy doses on an Ultratech broadband stepper, accumulating up to 3000 kJoules/cm² . Transmission was periodically re-measured and the pellicle films were visually inspected for color change and any apparent physical damage. Results were compared to the expected optical properties for each film type, and recommendations are provided for the most appropriate fil type for high-energy applications. Of the six pellicles tested, the two fluoropolymer films showed substantially better transmission stability than the cellulose based films. Discoloration occurred on the cellulose films over the chrome to glass transition area of the test reticle field suggesting that heat in the chrome surface affects the chemical structure of the pellicle films, thereby changing their transmission properties.

Mathematical prediction of dry etch results have been difficult, if not impossible, over the years due to the complexity inherent in plasma processing. With device requirements tightening combined with the high cost of running test masks, it becomes even more important for process engineers to have some means by which to model accurately this increasingly complex activity. In this paper, a correlation between a novel, plasma chrome etch model and empirical data will be presented. Practical effects of chrome loading are also discussed. From the empirical data side, studies on the photomask chrome etch process using e-beam resists were carried out following strict design of experiments (DOE) format. Photomask chrome etch processes with different resists (ZEP and positive CAR) were investigated using a Unaxis VLR 770 ICP etcher and an AMAT Tetra etcher. A Toshiba EBM-3500B (50KeV) was used for the pattern writing on positive CAR resist. A KLA-Tencor P12-EX profiler, Leica LWM 250 UV CD optical measurement system, and a KLA-Tencor 8250XP-R CD SEM were used for metrology and product characterization. Significant etch performance differences were shown on these etchers irrespective of the resist type used. A special measurable number was defined and found to have a linear relationship with etch movement on both AMAT and VLR etchers.

Alternating Aperture Phase Shift Photomask (AAPSM) technology becomes more critical as the industry approaches 90nm design rules. AAPSM enables the lithographic process to extend the viability of deep ultraviolet (DUV) photolithography systems. However, manufacturing high quality AAPS masks is difficult due to the stringent requirements placed on the etch process. Dry etch processes for alternating aperture masks must have good intra-mask phase uniformity, high Quartz/Cr selectivity, and vertical side-wall profile. While maintaining these parameters, it is also necessary for the process to achieve etch depth linearity across a range of feature sizes. Using a next generation Inductively Coupled Plasma (ICP), a series of experiments were performed to optimize the quartz etch process to improve feature size etch depth linearity and selectivity to resist. Etch results from an optimized solution are presented.

Utilizing the balance of capillary forces and adhesion, a liquid material, e.g. photo resist, can be applied to the surface of a face down mounted substrate. STEAG HamaTech's Advanced single Substrate Resist coater, ASR5000, is combining patented capillary apply technology, and a patented face-down spin process, to enable fringe free uniform coatings on rectangular substrates. CAP COATing technology reduces resist consumption by a factor of at least 10 over conventional coating methods. Face down spin, provides highly uniform resist spread without risk of backside contamination. The principle equipment concept and capability is presented. Coating and bake performance is discussed for IP3600 and ZEP7000A. Coating uniformities, of smaller ±0.7% at a 4500Å thick IP3600 film and smaller ±0.4% at a 3000Å thick ZEP7000A resist film were achieved, respectively. The repeatability of the coating performance and the post coat bake process (PCB) are demonstrated.

Embedded-attenuated phase shift masks (EAPSMs) have been an indispensable enabling technology for <130 nm node device fabrication. The precise etching of MoSiON is a key process in high quality phase shift mask manufacturing. Fluorine-based plasma chemistry has been used widely to date, but it is difficult to control CD (Critical Dimension) and phase uniformity. This stems mainly from the large Cr undercut and surface roughness due to the reaction of fluorine radicals with the phase shifting layer. In this paper, etch characteristics of the MoSiON layer using CF₄, O₂, and He in an inductively coupled plasma (ICP) were examined for the manufacturing of phase shift masks for 90-nm node design rules. The dependency of etch parameters such as ICP power, bias power (DC bias voltage), pressure, CF₄ concentration, and O₂ concentration on the etch properties of MoSiON were tested. We have investigated vertical slope, surface morphology, and minimum CD bias. This optimized process condition showed that intra-mask phase uniformity was below 1% (3-sigma) over a 135 mm × 135 mm mask area and transmittance uniformity was 8.68% ± 0.09%. CD uniformity was 5.5nm (3-sigma), CD linearity was 5.0nm over 300nm to 1300nm, and Cr-to-MoSiON CD bias was 2.0nm. The MoSiON profile was nearly vertical and the surface morphology was very clean.

The etch characteristics of MoSiON were investigated when chlorine was utilized as the main etch gas in an ICP dry etch system. MoSiON and glass are easily etched with fluorine-based plasmas such as: CF_4, SF_6, and CHF_3. These plasma chemistries generate carbon-containing and fluorine-containing polymers as byproducts, which can be responsible for generating particles or hard defects on the mask during the MoSiON etch step. They also cause damage to the glass surface, manifesting themselves as a phase or transmission errors. In this paper, new plasma chemistry was applied to etch MoSiON, and its characteristics were examined focusing on the effects of each parameter. These parameters included: ICP power, bias power, pressure, and gas concentration. It is difficult to etch MoSiON with good selectivity to Cr because MoSiON and Cr can be etched simultaneously after the photoresist layer has been removed. It will be shown how to increase the selectivity to Cr using an optimized process leveraging a new hardware modification. The etch characteristics of the chlorine plasma will also be compared to that of fluorine plasmas. It was found that using a chlorine plasma to etch MoSiON instead of a fluorine plasma yields good etch properties and good morphology.

The cleaning of embedded-attenuated phase shift masks (EAPSMs) is one of the most important enabling capabilities in the production of high-quality masks. Particles are commonly generated during Cr and MoSiON etching using inductively coupled plasma (ICP) tools. The cleaning process of EAPSMs requires not only the removal of particles on the phase shifting layer (MoSiON) and glass, but also the ability to leave the phase and transmission properties intact. Megasonic cleaning is a technique commonly used for removing particles on the surfaces of photomasks. However, megasonic processes employing SC-1 chemistry (specifically ammonium hydroxide) cannot be applied to a MoSiON PSM. Chemical erosion of the alkali-soluble phase shifting layer will drive phase and transmission performance outside of customer specifications. Therefore, EAPSM cleaning must balance simultaneously the complete removal of particles with the prevention physical damage. For these reasons, the cleaning process requires a high degree of control. In this paper, a new cleaning method was applied to MoSiON-based masks utilizing megasonic cleaning because it had a little change on phase and transmission. Traditional SC-1 chemistry was not used at all. Results obtained through this method showed a little change on phase and transmission. The particles on glass also can be sufficiently removed using megasonic process with the dilute SC-1 chemistry. The cleaning technique for the fabrication of EAPSMs with no variation in phase and transmission after the cleaning process will be presented.

The new capillary spin (CAP-Spin) coating principle, realized in the STEAG HamaTech ASR5000, was evaluated for mask making using chemically amplified resists. Basic correlations between coating parameters, resist thickness and film uniformity were figured out. We achieved a film thickness uniformity of close to 2% total range after a process optimization based on our investigation results with the positive tone resist JSR KRS-XE. Finally, the performance of ASR coated blanks was assessed on the basis of a binary mask making process using the Fuji FEP171 resist. The ASR5000 was integrated in an advanced tool set and the patterned reticles have met the requirements of the 100nm Technology Node in terms of resolution and CD-uniformity. No correlation between thickness and CD distribution could be observed. The evaluated post coating and post exposure delay influence of FEP171 also confirms the usability of the ASR5000 coated substrates for advanced mask making.

The loading effect is becoming a great issue in mask fabrication. To reduce CD error due to resist load, we have developed a developer based on a new concept, Proximity Gap Suction Development (PGSD), involving the use of a nozzle to spout developer and suck in dirty developer. In this paper, the performance of PGSD is reported.

CDs of photomasks include errors caused by photomask-making processes, namely, writing process, baking process in chemically amplified resist, resist development process, and etching process. Recently, the conventional resist develop methods, such as spray development, have raised issues concerning uneven pattern density on photomasks. Dependency of resist coverage is caused by low solubility of developer containing dissolved resist. In the ideal development process, only fresh developer would be on the resist surface at all times. To realize this ideal development process, we propose a development method, Proximity Gap Suction Development (PGSD), based on a new concept. PGSD involves the use of a scanning nozzle having five slits located in its surface facing the resist surface, a scanning mechanism keeping proximity gap between resist surface and the nozzle surface with slits, and a photomask holder. The nozzle is scanned from end to end of photomask on the holder. Developer spouts from a center slit of the nozzle. Slits at both sides of the center slit suck developer on resist surface with rinse fluid spouting from slits located outside of suction slits on the nozzle. Because proximity gap is kept between resist surface and the nozzle surface, spouted fresh developer reaches resist surface directly and it runs over resist surface at high speed. Then, developer on resist surface is excluded immediately with rinse fluid by suction slits. PGSD can produce CDs of resist pattern controlled precisely on photomask having uneven pattern density. We report details of the PGSD system, and compare the results for CDs obtained by PGSD with those obtained using the conventional method.

We present a comparison of line edge roughness on wet and dry etched reticles manufactured at the same mask shop. These measurements were taken on a Leica LWM250, and compare identical features on both masks. A 30% improvement in line edge quality was seen on the dry etched plates. Data supporting these results is presented.

The recently installed Sigma7100 laser pattern generator brings a new concept into photomask manufacturing. The spatial light modulator (SLM) technology enables 2D patterning using commercially available 248 nm lasers. This wavelength shift from the 413 nm wavelength of the Omega6000 scanning laser pattern generators facilitates the high resolution needed for 100 nm mask production. In addition, the partially coherence of the 2D patterning further enhances CD linearity and edge acuity. The rapidly increasing mask costs are partially attributed to increasing photomask writing times. These tend to increase as feature density increases with the roadmap, which is a challenge for any pattern generator with a limited number of writing beams. Instead, the SLM technology relies on the massive parallelism of one million micromirrors in combination with gray-scale control for fine addressing. A real-time FPGA-based data-rendering engine matches the speed. The result is pattern generation with high resolution at manageable mask writing times

We have developed a novel EB lithography simulator, which can analyze pattern profiles and CDs for an unlimited area. The simulator has a parallel Monte Carlo calculation mode with unequal mesh dividing, works on PC cluster hardware, and the new convolution algorithm. The simulation pattern profiles well-reproduced, observable chemically amplified resist pattern profiles. Simulated CD errors also well agree with measured PEC errors, when we compare the CDs for isolated line, line in lines/spaces and isolated space. Finally, the simulator also predicts the CD error difference between low-density and high-density global areas, which is caused by the fogging effect. The developed simulator demonstrates that the simulator can be applied for all CD performance analyses and has the potential to be a mainstream device for EB lithography simulation.

Electron beam (e-beam) proximity effect correction (PEC) has become a critical consideration with the reduction of feature sizes and the increasing use of optical proximity effect correction (OPC). PEC is accomplished on the 50kV MEBES eXara system with the embedded PEC (emPEC) technique, which is an automated version of GHOST. This method equalizes the background exposure by writing a fifth pass in the reverse tone of the four primary exposure passes. This compensates for the dose differences in the background due to backscattered electrons. The result is feature size control independent of the proximity and density of surrounding features, and independent of feature size. The method is simple and does not require additional computations for raster scan systems. A description of the method and its results for both coverage proximity effect correction (feature size deviation as a function of the surrounding exposure density) and CD linearity (deviation of different feature sizes) is presented.

To achieve higher resolution and critical dimension (CD) accuracy in mask fabrication, 50KeV E-beam systems are used widely. However, as a high acceleration system is adapted, the degree of fogging effect caused by multi-scattering electrons becomes more serious. Although considerable efforts have been made, fogging effect cannot be removed perfectly, therefore several compensation techniques are applied instead. Fogging effect not only deteriorates CD uniformity but also makes mean to target (MTT) control difficult. Moreover, Fogging effect causes proximity effect correction (PEC) error according to PEC methods such as dose modulation type usually used in variable shaped beam (VSB) system and GHOST type commonly used in Gaussian beam system. In this paper, we investigated the fogging effect under the various exposure conditions at raster scan Gaussian beam system and VSB system experimentally and analytically.

For high-voltage vector e-beam writing systems, solving the resist heating effect problem is one of the highest priorities because it is a major factor affecting localized critical dimension (CD) uniformity. In order to write patterns for 90nm node devices, the utilization of proximity effect correction (PEC) is essential for e-beam mask writers to achieve high CD performance. In this study, the dependence of CD variation on e-beam write conditions was investigated under optimum PEC parameter conditions. Writing conditions such as current density, shot size, number of writing passes, and settling time were tested to see their affects on resist heating. Industry-standard Nippon Zeon ZEP 7000 resist was written by a Toshiba EBM-3500B 50KeV vector e-beam writer using patterns found in sub-130nm node devices. Results indicated that the main factor affecting resist heating CD variation for ZEP 7000 was in fact the e-beam writer shot size selected. Multi-pass writing was effective in reducing the CD variation, and the settling time of each shot in the EBM-3500B had very little influence.

The continuous shrinking of design rules results in tighter specifications for linearity in advanced mask processing. Specifically, the increasing need for multiple devices on a single reticle set, e.g., multiproject wafers (MPWs) and systems on a chip (SoC), drives development in this area. Advanced masks were prepared with positive and negative chemically amplified resist (CAR) written on the Hitachi HL-950M. Post-exposure bake was performed in a double-sided proximity baking system; development was done using a spray-puddle method. Etch experiments were performed in the Etec Systems Tetra photomask etch chamber. Linearity measurements were performed using the Hitachi S-7840 CD SEM and the Leica LWM 250 DUV. Both clear and dark isolated and dense features were measured. The current work examines the impact of various etch process parameters (Cl₂/O₂ ratio, gas flow, pressure, source power) on CD linearity between 400 nm and 1.25 μm. A full factorial-designed orthogonal experiment was performed to determine the main effects and any interactions that might impact the linearity performance. Pressure and total flow showed a strong influence on linearity.

It is intended to clarify the feasibility of 0.15μm generation mask fabrication with the photomask repeater that is based on a KrF stepper(step-and-repeat exposure system). In a photomask repeater patterning, a daughter mask is exposed to KrF light through a mother mask. Inter-field registration accuracy(3sigma) is 14.9nm in X direction and 29.1nm in Y direction within a 100mm×100mm area on a daughter mask and intra-field registration accuracy(3sigma) is 21nm in X direction and 26nm in Y direction within a 18.4mm×23.0mm field on a daughter mask. The registration error within the field on a daughter mask can be reduced to about 13.5nm(range) by compensating for the registration error to a mother mask. Inter-field CD uniformity(3sigma) is 8nm in 100mm×100mm area on a daughter mask and intra-field CD uniformity (3sigma) is 24nm within a 18.4mm×23.0mm field on a daughter mask. The intra-field CD uniformity (3sigma) can be improved into 15nm by compensating for the CD error to a mother mask . In order to satisfy the 30nm registration and 15nm CD uniformity specification of a 0.15μm generation mask, we need to reduce the inter-field registration error with removing the backside defect of a daughter mask and improve the intra-field CD uniformity by changing the dose distribution of the photomask repeater.

As the feature size of integrated circuits shrinks, the demands for the critical dimension (CD) uniformity on wafers are becoming tighter. In the era of low k1, moreover, mask CD uniformity should be controlled even more stringently due to the higher mask error enhancement factor (MEEF). Mask CD non-uniformity can originate from several sources which include photomask blanks and mask-making processes (exposure, post-exposure bake (PEB), development, and etch processes). Analyzing the CD error sources and eliminating the origins are very important tasks in optimization of mask-manufacturing processes. In this paper, we focus on the side error in mask CD uniformity and present a simple method for separating and evaluating the origins. Especially, quantitative analysis of the side errors induced by photomask blanks and mask-making processes, respectively, is given. Photomask blanks are found to be one of the main sources of the side error and it is shown that the temperature distribution of the PEB process during the ramp-up as well as the stable period should be maintained uniformly for chemically amplified resist (CAR) blanks in order to reduce the process-induced side error.

A new mask methodology of mask defect specifications by fail-bit-map (FBM) analysis of LSI devices was proposed. In this paper, concept of new mask defect specifications based on the FBM analysis is shown and impacts on LSI devices of mask defects are studied and the new methodology for next generation is applied. The new mask defect specifications were implemented in a gate-level mask with defects programmed into a 0.175μm-rule DRAM fabrication process, as follows, Firstly, the programmed defects varied in terms of the types, locations and sizes were designed into the memory cell area on the 0.175μm-rule DRAM gate-level mask. Secondly, the gate-level mask with programmed defects was fabricated with conventional mask process flow and the actual mask defect sizes were measured. Thirdly, exposures of the gate-level mask were carried out with conventional 0.175μm-rule DRAM process. Finally, the large impacts on CDs caused by mask defect printability on wafers were clarified and FBM analysis was performed to characterize the relationship among the actual mask defect variations, the CD variations and electrical function of 0.175μm-rule DRAM. This relationship can facilitate determination of the mask defect specifications on 0.175μm-rule DRAM and also likely contribute to estimate next-generation defect specifications. According to the results of the above procedure, the mask defect specifications for opaque defects should be generally tighter than those for clear defects in view of the printability on the wafers and the FBM analysis. Nevertheless, the FBM results suggested that current mask inspection sensitivity for clear defects was too high. With the new methodology, in regard to the impacts of mask defects not only on wafer CDs but also on LSI devices, we have succeeded in obtaining useful results for the mask defect specifications.

Many photomask customers require process capability reporting on a regular basis. One of their main purposes is to evaluate product quality based on process variability from period to period. The problem occurs when process improvement is based on a single reported index. There are a variety of methods used today to calculate process capability, and any one method has proven insufficient (see figure below). Process 'A' looks good with respect to the average-range divided by a constant (R-bar/d₂), but the standard deviation looks too wide. Conversely, Process 'B' looks good with respect to standard deviation, but its R-bar/d₂ is skewed too far. An explanation for this phenomenon is that the use of the standard deviation method to calculate capability (actually the performance index) ignores within-sample variation, and using the R-bar/d₂ method omits sample-to-sample variation. Therefore, both methods should be employed to better evaluate process performance and capability. This paper presents a means by which to employ the merits of both sigma estimators to achieve a better representation of continual improvement. Utilizing a method of pooling within and between-sample variation (Cvk) indicates that the two processes below actually exhibit almost identical capability.

To accurately control critical dimension (CD) metrology in a standard real-time solution across a multi-site operation there is a need to collect measure-to-measure and day-to-day variation across all sites. Each individual site's needs, technologies, and resources can affect the final solution. A preferred statistical process control (SPC) solution for testing measure-to-measure and day-to-day variation is the traditional Mean and Range chart. However, replicating the full measurement process needed for the Mean and Range chart in real-time can strain resources. To solve this problem, an initially proposed measurement methodology was to isolate a point of interest, measure the CD feature n number of times, and continue to the next feature; however, the interdependencies in measure-to-measure variation caused by this methodology resulted in exceedingly narrow control limits. This paper explains how traditional solutions to narrow control limits are statistically problematic and explores the approach of computing control limits for the Mean chart utilizing the moving range of sample means to estimate sigma instead of the traditional range method. Tool monitoring data from multiple CD metrology tools are reported and compared against control limits calculated by the traditional approach, engineering limits, and the suggested approach. The data indicate that the suggested approach is the most accurate of the three solutions.

In the paper given by these authors this spring at Photomask Japan, investigations into the advances in the CATS tool that combine hierarchical fracturing and distributed processing were begun. In addition to the beneficial reduction in processing times, various shortcomings of the software were detailed. For this study, the next version of the CATS software tool has been made available and those shortcomings are remedied. Difficult model OPC (MOPC) fractures and complicated de-slivering fractures for variable shaped beam machines are analyzed. Timing results, exclusive-OR operations, and the implications of Amdahl’s Law are also considered. Further intricacies of Linux cluster computing are also addressed.

Within the past decades data file sizes and the related computing power for mask data preparation grew linearly following Moore’s law. However, within the last two years the balance between rising data complexity and computing equipment became unstable due to the massive introduction of OPC and the broad rollout of complex variable shaped beam (VSB) data formats. The disturbance of the former linear coherence led to exploding data conversion times (exceeding 100 hours for a single layer) accompanied by heavily escalating data volumes. A very promising way out of that dilemma is the recently announced introduction of distributed job processing within the mask data processing flow. This way was initially introduced to fracture flat jobs. Building on our first promising results last year we now implemented a fully automated design flow with an integrated Linux based cluster for distributed processing. The cluster solution is built in an automated environment in coexistence with our conventional SUN servers. We implemented a highly reliable DP flow on a large scale base which became as stable as our former Solaris SUN system. In the meanwhile we reached a job first time success rate exceeding 99%. After reaching a very stable state we recently started to extend our flat processing conversion steps by investigating hierarchical distributed processing in CATS version 23. We also report on benchmark results comparing new promising hardware configurations to further improve the cluster performance.

A prototype system is proposed for incorporating fast process models with EDA management of layout to identify and help arbitrate locations in a chip that are likely subject to less than ideal process effects. The approach uses pattern matching to find those locations in a layout that have the greatest impact from residual imperfections in manufacturing. For each process under study, the maximal lateral test pattern that maximizes the spillover from the surrounding pattern is first determined. The quantitative impact of the spillover for an actual layout is then assessed through comparing the degree of similarity of the actual pattern in a neighborhood about a critical point to the maximal lateral test pattern and scaling the impact accordingly. This fast-CAD pattern-matching approach is shown to be applicable for analysis of yield reduction due to combined effects of defects and alignment tolerances among mask levels as well as for identifying layout areas affected by reflective notching, CMP dishing and, with less accuracy, heating in laser assisted processing.

The shape of a printed feature on a wafer is generally different from the corresponding pattern on the layout. T-less model is an effective method of predicting the contour line of a printed feature on a wafer. A calibration model is first established by using data from certain test patterns, and then applied to real layout to predict contour lines of features on a wafer. It would be computationally inaccessible to compute every point of a contour line. We only compute a number of points on a contour line and then extend these points to a curve by interpolation. Error occurs from many sources in this computation process and may give inaccurate interpolation. In this paper we present a computation scheme that filters noises from the calibrated data. This scheme is of two folds, removing outliers and interpolation. Our simulation results match the real data well. Inspired by natural cubic splines and nu- splines, we developed a new technique of spline interpolation, which has both the simplicity of the usual natural cubic spline interpolation and the flexibility of nu-splines.

Simulation-based techniques assisted mask and wafer metrology and inspection have become increasingly important with the growth of the sub-wavelength gap in optical photolithography. This paper describes a method for full-chip layout verification based on fast calculation of the mask error enhancement factor (MEEF). Because of the significant amount of MEEF computations necessary for large layouts, we discuss a methodology that takes advantage of distributed computing environment to significantly shorten the total run time. Additionally, MEEF calculations can be selectively reduced to layout locations that meet specific criteria, which allows to not only reduce the overall simulation time, but also to decrease the output data volume transferred to the mask inspection equipment. After MEEF is calculated, a SQL database is used to generate a summary report and to efficiently locate high-MEEF areas, which could be sent in a form marker files to metrology tools.

Nanomachining has recently been introduced as a new technology for subtractive repair of 130-nanometer masks. The RAVE LLC nm1300 utilizes this innovative strategy, facilitating repairs of all materials currently used in mask production. This technology has allowed 130-nanometer mask repair specifications to be met. This paper introduces nanomachining as a method of repairing next generation 100-nanometer masks. Emphasis will be given to materials and designs that provide significant challenges to current industry repair techniques; specifically quartz bumps on alternating phase shift masks and repairs within tight lines and spaces. Several advantages will be demonstrated, including the ability to machine within high aspect ratio features, the capability to duplicate edge slope, superior edge placement control, quartz bump repair, and transmission values approaching defect-free areas. This paper will compare performance to the SIA roadmap requirements for 100-nanometer mask repair using RAVE LLC’S next generation system, the nm1000.

For alternating aperture phase shift masks (AAPSM), phase-defect detection and disposition is more difficult for 193 nm (ArF) lithography than for 248 nm (KrF) lithography, as pattern geometry is tighter and quartz etching is shallower. For ArF lithography, we designed and fabricated a new test mask to confirm detectability and printability of phase defects, extending our previous work for KrF lithography. This test mask has precise defect sizes and phase-error angles of 25, 50, and 75 degrees. Detectability was demonstrated on KLA-Tencor’s SLF27 and investigated by acquiring defect images on SLF27 and LaserTec’s MD3000 inspection systems. Printability was compared between actual wafer prints, and simulations from Carl Zeiss’ Aerial Image Measurement System (AIMS). Wafer prints were also simulated using Numerical Technologies’ software-based Virtual Stepper System, which takes inspection images as input and models the optical aspects of lithography. Virtual Stepper critical-dimension measurements show good general agreement with those from AIMS images and wafer-print SEM images. Compared to AIMS, which is a hardware-based simulator that uses the actual mask as input, the software-based Virtual Stepper System is easier to adapt to different processes and to integrate into the production flow.

With growing implementation of low k1 lithography on DUV scanners for wafer production, detecting and analyzing photomask critical dimension (CD) errors and semitransparent defects is vital for qualifying photomasks to enable high IC wafer yields for 130nm and 100nm nodes. Using the TeraStar pattern inspection system's image computer platform, a new die-to-database algorithm, TeraFlux, has been implemented and tested for the inspection of small "closed" features. The algorithm is run in die-to-database mode comparing the energy flux difference between reticle and the database reference for small closed features, such as, contacts, trenches, and cells on chrome and half-tone reticles. The algorithm is applicable to both clear and dark field reticles. Tests show the new algorithm provides CD error detection to 6% energy flux variation with low false defect counts. We have characterized the sensitivity and false defect performance of the die-to-database energy flux algorithm with production masks and programmed defect test masks. A sampling of inspection results will be presented. Wafer printability results using the programmed defects on a programmed defect test reticle will be presented and compared to the inspection defect sensitivity results.

For alternating aperture phase shift masks (AAPSM) and 193 nm (ArF) lithography, we have simulated defect printability using inspection images and software-based modeling. Masks were fabricated by DuPont Photomasks with programmed defects of known size, phase, and location. Three phase layers were used to generate defect angles 60, 120 and 180 degrees. Simulated wafer prints were performed using Numerical Technologies’ Virtual Stepper System, which takes inspection images as input and models the lithographic process. With inspection images from KLA-Tencor’s SLF27 system, our critical-dimension measurements show good agreement with those from wafers printed on an ASML PAS 5500/900 scanner.

HT-PSMs (Half Tone Phase Shifting Masks) are well known as one of the key technologies to obtain high resolution and expand process window of lithography. And furthermore, high transmission HT-PSMs are expected to show better DOF and MEEF than conventional transmission, such as 6%, HT-PSM. We have already developed and reported TaSiOx shifter as a high transmission HT material for ArF lithography. And also we have reported its process performance such as good phase controllability, vertical side-wall angle, no damage on quartz surface during shifter dry etching and good CD uniformity. The key point to obtain these performances is the characteristics of etching stop function of its bi-layered structure. This bi-layered structure also enabled transmission at the inspection wavelength to keep enough low to inspect by current inspection systems. In this report, in order to confirm the feasibility of mass-manufacturing of the TaSiOx high transmission HT-PSM, we fabricated programmed defect test mask and performed following experiments. Defect detectability was evaluated by KLA-Tencor SLF27 and compared to printability results that were confirmed by ZEISS MSM193. We will also show some preliminarily results of repairing tests on this TaSiOx material.

As the design rule of lithography becomes smaller, printability of reticle defect to wafer is crucial for the photomask manufacturing technology. In order to improve the controllability of reticle defects, inspection and repair systems are expanding their capability by continuously modifying hardware and software. This is a good solution to detect and review the defect but it is indirect approaching to reduce the defect in the photomask process. To produce the photomask of defect free or low defect density, effort is needed to improve the capability of defect control in the mask-making process and to evaluate the source of hard defect as well as soft defect. In this paper, we concern the defect source and the feature of printed defects in photomask manufacturing steps. We also discuss the efforts to eliminate the defect source and to control the mask-making process with low defect density. In order to eliminate the source of defects, we partition the mask-making process with defect inspection system, SLF27 TeraStar and Lasertec MD2000, and review a defect shape with CD SEM and AFM. And we compare printed defects, which exist in each process steps, after dry etching process.

As our chip producing industry rapidly ramps to mass production of the 130nm device technology node and wrapping up the final stages of 90nm node process technology development, the ability to inspect all types of 130nm node masks and early identification of shortcomings in 90nm node mask inspection are extremely important. In this paper, we share our experience of mask inspection for the 90nm and 130nm nodes, using the advanced TeraStar mask inspection system (KLA-Tencor) with the SEMI programmed defect standard masks, comprising three substrate types (binary, 248nm-KrF MoSi and 193nm-ArF MoSiON). Both Die-to-Die (D2D) and Die-to-Database (DDB) inspections were carried out and the results are presented with our assessments of benefits and shortcomings of those methods. To verify the resulting defects actually impact device functionality, we also carried out systematic printability experiments with our proprietary 130nm and 90nm nodes lithography processes. The wafer results were then compared with mask inspection results and mask measurement data to draw our final conclusions. In addition, we will also present inspection performance of the TeraStar system on our 130nm production masks and very challenging 90nm node (ArF EAPSM/AAPSM) development masks.

High quality reticles are critical to the success of the 90 nm wafer node. Even though many wafer fabs are planning to use 193nm exposure tools, the k₁ factor (minimum feature size x NA/λ) will be pushed to very low levels. With low k₁ lithography, very small mask errors propagate to the wafer. This is especially true for contact and via layers. New generation mask writing tools have been developed to meet these needs. 50 kV electron beam tools can produce high quality masks , but their high costs and low throughputs result in high mask costs. On the other hand, DUV laser writers, with inherently high throughput, can produce high quality masks at a significantly lower cost than e-beam writers. The fundamental technical distinction between laser and e-beam mask writers is resolution, manifest primarily as a corner rounding difference. While corner rounding has essentially no impact in wafer lithography (low NA at the mask renders wafer lithography a low pass filter), it cannot be ignored in mask pattern inspection, which uses high NA optics. In this study, it is demonstrated that reticles patterned on laser and e-beam tools can be inspected in database mode with full sensitivity at design rules beyond 130 nm. Further, a new energy measurement algorithm is used to evaluate contact patterns on both e-beam and laser-written masks, and it is shown that currently available laser mask writers should be extensible to the 90 nm node, even for these high MEEF features.

Today, many IC manufacturers use OPC (Optical Proximity effect Correction) technique to obtain finer circuit geometries by adding serifs and jogs to conventional binary mask. Moreover, for endless device shrink in the absent of alternative lithography solution, successful below-half-wavelength lithography requires “much stronger OPC” which consisted of complicate patterns generated from the finer grid size of OPC software or many assist patterns to the main patterns. The mask industry, therefore, is now facing significant problems induced by both increasing write time and defect-like-small complicated OPC patterns. It is questionable that current inspection system could detect all the defect-sources as the aggressiveness of OPC is accelerated. It is not everything to detect small defect only. The direction of development of new reticle inspection tool should be directed by a smart strategy under such an aggressive environment. This paper details the lithographic effects under the 193nm wavelength and inspection sensitivity using newly developed DUV inspection system for various defects on OPC reticle. The relationship between lithographic effects and reticle inspection sensitivity was investigated according to the defect type, defect size, defect position and the aggressiveness of OPC. From this study the requirements of next generation inspection system would be clarified to necessitate good OPC mask manufacturing.

Reticle defects are one leading source of yield loss. This paper is a continuation of work begun to track defect sources to the process steps that generate them. Prior work was done on a common electron beam resist. This study will examine a DUV optical chemically amplified resist.