Mask CD resolution and uniformity requirements for back end of line (BEOL) layers for the 90nm Technology Node push the capability of I-line mask writers; yet, do not require the capability offered by more expensive 50KeV ebeam mask writers. This suite of mask layers seems to be a perfect match for the capabilities of the DUV mask writing tools, which offer a lower cost option to the 50KeV platforms. This paper will evaluate both the mask and wafer results from all three platforms of mask writers (50KeV VSB,ETEC Alta 4300TM DUV laser and ETEC Alta 3500TM I-line laser) for a Cypress 90nm node Metal 1 layer, and demonstrate the benefits of the DUV platform with no change to OPC for this layer.

The ALTA 4300 system has been used to successfully write many advanced design layers previously only feasible with 50kV vector shaped beam tools. In order to further enlarge the application space of this high productivity an aerial image enhancement technique has been developed to deliver mask patterns that more closely match pattern data for corners and jogs. This image enhancement is done in real time in the ALTA system’s rasterizer by modifying the gray level mapping of pixels near the corner vertexes. SEM measurements of corner rounding with standard rasterization and the enhanced rasterization show an improvement of corner rounding radius from ~205 to ~132 nm. A direct comparison of SEM micrographs show no qualitative difference between vector scan mask features and those written with aerial image enhancement. This convincingly demonstrates that the ALTA 4300 system with the new image enhancement can write many layers requiring vector scan corner acuity.

In the recent past significant work has been done to isolate and characterize suitable single layer Chemically Amplified Resist (CAR) systems for DUV printing applicable to photomask fabrication. This work is complicated by the inherent instability of most DUV CAR systems, particularly in air, showing unacceptable CD degradation over the normal photomask write time in today's DUV mask pattern generators. The high reflectivity of most photomask substrates at DUV wavelengths, creating unacceptable standing waves in the photo resist profile, further compounds this problem. A single layer CAR system suitable for 90nm technology node mask fabrication with DUV printing has been characterized and optimized. Results of this optimization in terms of relevant mask making parameters will be detailed. Furthermore, comparison of the properties of this resist system to other commercially available systems, including FEP-171, will be shown. The pattern fidelity of DUV laser generated masks has been studied in considerable detail. A demonstration of the capabilities of the Etec Systems ALTA^TM 4300 and Micronic Laser Systems Sigma 7100 DUV mask writing systems will be shown. The pattern fidelity achieved will be compared/contrasted to that achieved with today's leading edge 50KeV vector scan e-beam systems. Advanced methods for modulating the DUV printed patterns' fidelity will be detailed. Finally, the cost and cycle time implications of inserting the DUV laser pattern generator into the mask manufacturing flow will be discussed.

We have developed a new method to make cell projection aperture with high degree of accuracy which provides stable and accurate pattern fidelity on wafer and could be adaptable to mask process. As an electron beam mask, deep and vertical silicon pattern is made by MERIE poly etcher. Trench pattern profile can be optimized by etching chemistry. And to obtain fine pattern with cell projection exposure, various techniques are used such as pattern fracturing, modified cell aperture layout and shot shift. As a feasibility of cell projection EB exposure, 0.2μm feature were defined with VSB (variable shaped beam) and CPB (cell projection beam) on wafer and evaluated.

E-beam lithography simulation is one of the effective tools for understanding the complex e-beam lithography process. In-house E-beam Lithography Simulator, ELIS, has been developed in order to analyze the mask CD errors. ELIS adopts the Monte Carlo method to accurately describe the electron scattering and energy deposition on the resist, and fits this result with more than two Gaussians to convolute with pattern shape efficiently and rapidly. This simulator provides the function of the proximity effect correction (PEC) and fogging effect correction. ELIS, moreover, can simulate the post exposure bake step (PEB), therefore, latent image and resist profile is given for chemically amplified resists (CAR). From the exposure simulation with ELIS, the amoung of CD variation regarding different density patterns in various conditions can be predicted. The simulation results are matched with experimented values within 5% error. Even though PEC corrects perfectly, the non-zero mean-to-target (MTT) induces the CD error. The CD errors with dose modulation and GHOST along with the MTT variation have been studied with ELIS. Also, we show these errors increasing after applying fogging effect correction.

In photomask manufacturing, etch loading effect is one of the most serious problems. The equal size of isolated clear patterns, each of which is surrounded by different pattern density, can show different CD (critical dimension) results after Cr etching process. Furthermore, as the feature size decreases and pattern density increase, the burden of Cr loading effect in mask fabrication is more enlarged than ever. In this paper, we will present the new method for approaching to the loading free process in photomask Cr dry etch.

As mask features advance to the 65 nm technology node, the ability to develop advanced phase shifting masks with reliable and repeatable processes is becoming increasingly important. Changes in process conditions (i.e. power, pressure, gases, etc.), play an important role in the reduction of RIE lag, micro-trenching, loading and the improvement of sidewall profiles. In this study, the effects of changing process conditions on the Tetra^TM II Photomask Etch System were investigated. Process development was conducted to screen for a quartz etch process regime with enhanced performance.

The phase shift effect in Alternating Phase Shift Masks (AAPSMs) and chrome-less phase shift masks is created by etching trenches directly into the quartz substrate. Since the phase shift is critically dependent on the etch depth, the quartz etch process must be tightly controlled. In the absence of an etch stop for the process, an integrated metrology solution is desirable on the mask tech tool. Traditional methods for measuring etch depth or phase shift, such as interferometry, profilometry, AFM, and SEM, are expensive, slow, and/or destructive. In addition, traditional methods cannot measure quartz etch depth without removing the resist and in some cases the chrome mask, making them unsuitable for integration into the etch process. This paper will present measurements of trench depth and phase shift on quartz phase shift mask using the n&k Analyzer 1512-RT. The n&k Analyzer measures reflectance (R) and transmittance (T) from 190-1000nm, which is analyzed according to the Forouhi-Bloomer dispersion relations to simultaneously determine n, k, film thicknesses, trench depth, and phase shift. The measurement is non-destructive and fast, typically taking 2-3 seconds per measurement point. No special test structures are required for the measurement. In addition, the n&k Analyzer can measure quartz etch depth with the chrome mask, ARC layers, and resist still intact. The n&k Analyzer measurements show good correlation with 193nm interferometer measurements, and good repeatability. The small footprint, ease of use, measurement speed, and the ability to measure quartz depth in the presence of chrome and resist make the n&k Analyzer an ideal candidate for integrated metrology applications on mask etch tools for advanced proces control (APC). The Applied Materials' Tetra II phootmask etch system has the unique capability to accommodate integrated metrology modules through the factory interface. Applications of APC with integrated phase shift measurements will be discussed.

In reticle production for 90-nm node generation and beyond, quite strict chrome CD control is strongly demanded. For chrome dry-etching process, esetablishment of reliable system for chrome endpoint detection is one of critical issues. In this paper, the effectiveness of radio frequency (RF) sensor as a process monitor for chrome dry-etching was examined. As general endpoint detection system, such as Laser endpoint detection (Laser EPD) and optical emission spectroscopy (OES), the system based on RF sensor shows the ability to get chrome endpoint. Experimental data implied its competence as an endpoint detector for the plates of various chrome loads with enough stability and reliability. Moreover, this sensor has an advantage that plasma impedance observed with the sensor has a correlation with etching performance, such as etching bias and its uniformity. This property is useful, because feedback of the variation of sensor output to process condition is able to play important role in control of reticle CD. As a consequence, the concept of advanced process control based on the RF sensor is proposed.

The first vortex masks composed of rectangles with phases of 0°, 90°, 180° and 270° - as proposed at Photomask 2002 - have been fabricated and shown to print sub-100nm contacts. The walls of the phase trenches are very nearly vertical, with all four phase regions meeting at sharp corners which define the phase singularities. Arrays with pitches down to 210nm have been printed in negative DUV resist using KrF illumination with NA=0.73 and sigma=0.15. The developed contacts are somewhat elliptical, but their shapes can be corrected (if necessary) by OPC techniques. The depth of focus for +/-10% CD variation is >400nm for 85nm CD vias at 210nm pitch and >700nm for 100nm vias at 250nm pitch. The exposure latitude is ~15% at best focus. At constant exposure dose, the via CDs vary with pitch as predicted by simulations. Increasing exposure dose makes the openings smaller, more uniform and more circular. No significant surface development has appeared due to phase-edge printing. However, the spacewidth alternation phenomenon familiar from linear chromeless phase-edge lithography does cause small positional errors for vortex vias, and each of the four vortices in the repeating pattern behaves somewhat differently through focus, potentially limiting the common process window.

Each new technology node tests the limits of optical lithography. As exposure wavelength is reduced, new imaging techniques are needed to maximize resolution capabilities. The phase shift mask (PSM) is one such technique that is utilized to push the limits of optical lithography. Altering the optical phase of the light that transmits through a photo mask can increase the resolution of a lithographic image significantly. There are several types of phase shift mask and each has a general charateristic in which some transparent area of the mask are given 180° shift in optical phase relative to other nearby transparent areas. The interaction of the aerial images between two features with a relative phase difference of 180° create interference regions that can be used to printed images much closer together and with an increased depth of focus than that of a standard chrome-on-glass mask. An AAPSM is fabricated using a subtractive process in which the quartz substrate is etched to a given depth to produce the desired phase shift. However, intensity imbalances between the etched and non-etched regions due to sidewall scattering can cause resolution, phase and placement errors on the wafer. One method to balance the transmission is 40 nm undercut with 16 nm shifter width bias. Based on our previous study, 40 nm undercut with 16 nm shifter width bias showed an improved balance of intensities between the etched and non-etched regions. The object of this experiment is to implement the AAPSM with 40 nm undercut and 16 nm shifter width bias in SRAM product and the exposure wavelength is 193 nm. The main purpose is to proof the technology of AAPSM with 40 nm undercut and 16 nm shifter width bias in real product. Also verifying all issue of AAPSM in production. In this study, the image imbalance has been corrected via 40 nm undercut and 16 nm shifter width bias, and the DOF of AAPSM for wafer print performance is larger than binary mask. The DOF of AAPSM is about 0.5 μm and the conventional binary mask is 0.3μm.

High speed circuit usually requires additional gate scaling regardless of its developed technology node. In this paper, we demonstrate the full-chip-level wafer result for 100nm node SRAM gate and the possibility of future gate scaling. Test reticle is manufactured using chromeless phase lithography(CPL). CPL technology uses a COG that consists of p -phased-etched quartz and chrome shield for various gate CD formation. Critical transistor area is 100% transmission PSM. However, less-critical area should be a chrome for adequate CD control. Because light interference is weakened in phase area according to the separation of paired phase edges increase. The optical performance and manufacturing issues of CPL are evaluated compared to other PSM technologies. Finally, we describe how to optimize the CPL mask using simulation and wafer analysis to obtain the acceptable OCV and DOF margin for volume production.

Step and FLash Imprint Lithography (S-FIL) is one of several new methods of imprint lithography being actively developed. Since S-FIL is a 1X printing technique, fabrication of templates is especially critical. The requirement to produce defect-free pillars (needed for imprinting contacts on wafers) in a reliable and manufacturable manner only serves to compound this challenge. In this study, the feasibilty and methodology of fabricating templates having arrays of sub-80 nm pillars is demonstrated. This process involves the use of a Leica VB6 100 keV e-beam system to pattern ZEP 520A resist, followed by a series of chrome and quartz etches to arrive at the final all-quartz template. Wafer printing was done on 200 mm wafers using Molecular Imprints Inc., Imprio-100 system. Critical dimension of template contacts and pillars is shown as a function of e-beam dose. Results of the study have demonstrated that S-FIL templates made with sub-80 nm pillars can be used to reliably replicate 1:1 pitch contact hole arrays on wafers. Sidewall profiles of both template pillars and printed contacts were sloped somewhat, and resulted in an approximately a 20-30 nm bias between contact bottom (smaller) and top opening. Critical dimension uniformity of printed contact arrays within-field and from field-to-field was also explored. Within-field CD uniformity of contacts was found to be less than field-to-field CD uniformity, which was excellent. The feasibility of printing pillar array using S-FIL was also demonstrated. Arrays of pillars measuring 54 nm with a pitch of 1:3 were reliably printed.

The performance of the LEEPL production tool is discussed from the framework of the litho-and-mask concurrent development schemes to establish the feasibility of proximity electron lithography (PEL) especially for contact and via layers in the 65-nm technology node. The critical-dimension (CD) uniformity of 4.7 nm has been achieved for 90-nm contact holes over the 1x stencil mask. Thus, the mask patterns can be transferred onto the resist layer with CD errors of less than 10%, even if the mask-error enhancement factor (MEEF) of 1.6 is taken into account. The mask manufacturability is improved if the MEEF further decreases via the use of thinner resists. Meanwhile, the overlay accuracy of 21.1 nm has been achieved in mix-and-match with the ArF scanner, with the intra-field error of only 5.1 nm owing to the real-time correction for the mask distortion. Also, the conditions for splitting dense lines into two complementary portions have been determined to avoid the pattern collapse in wet-cleaning and drying processes. The critical length of 2 mm is fairly safe for 70-nm lines if the low-damage drying is employed. The inspection tool based on transmission electron images cannot detect all printable defects without further optimization, hence a future challenge.

To cope with sub-100nm technology in the mask making industry, a variable shaped e-beam(VSB) writing system is one of the solutions through its high-electron voltage. The VSB writing system, however, requires a different mask data preparation comparing to the traditional raster scan writing system. Due to the differences, mask making industries are confronted with difficult problems, such as explosively increasing data volume and unpredictably growing mask making time especially for memory devices. VSB system's writing time is determined by the conversion from CAD data to VSB data. The conversion time, especially for the critical layers of memory devices, mostly depends on to what extent optimize CAD data to enhance writing system throughput. For this reason, to shorten the unpredictably growing mask making time, a data conversion tool must consider the throughput of data conversion and mask writing at the same time. To reduce the data conversion time while retaining the optimal writing time, we propose the mixed-mode data processing method, in which the hierarchical data operation is applied on memory cells and the flat data operation is applied on peripheral circuits. For each area, different fracturing strategies are applied, too. The polygon-aware fracturing method is applied to improve the CD control within memory cells, and the selective one-directional fracturing method is applied to reduce the writing time within peripheral circuits.

The continuous integration trend in design and broad deployment of resolution enhancement techniques (RET) have a tremendous impact on circuit file size and pattern complexity. Increasing design cycle time has drawn attention to the data manipulation steps that follow the physical layout of the design. The contributions to the total turn-around time for a design are twofold: the time to get the data ready for the hand-off to the mask writer is growing, but also the time it takes to write the mask is heavily influenced by the size and complexity of the data. In order to reduce the time that is required for the application of RET and the export of the data to mask writer formats, massively parallel processing approaches have been described. This paper presents such computing algorithms for the hierarchical implementation of RET and mask data preparation (MDP). We focus on the parallel and flexible deployment of a new hybrid multithreaded and distributed processing scheme in homogeneous and heterogeneous computer networks called MTFlex. We describe the new methodology and discuss corresponding hardware and software configurations. The application of this “MTFlex” computing scheme to different tasks in post-tapeout data preparation is shown in examples.

The OASIS format was designed to be a replacement for the GDSII stream format. Previous papers have reported that OASIS files can be 5-20X smaller than comparable GDSII files. This paper examines the storage capabilities of OASIS, as well as other benefits, in more detail. The primary focus of this study is on OASIS integers, deltas, point-lists, and its explicit support for rectangles & squares. We also show how the two OASIS integer types and four delta types can be implemented using a single core procedure.

Technology complexity has led inevitably to specialization. As a result, most people know their own area well and have only limited access to or knowledge of what goes on in the other areas. Designers and chip customers often have limited understanding of the details of the manufacturing process, and wafer fab engineers seldom have direct access to designers for improvements which would maximize productivity and yield. Masks are often overly expensive because decisions made in design have unintended manufacturing consequences, and mask yields are unnecessarily low because too little information defining the image quality actually needed is available to the mask supplier. These limitations and others can be overcome by integrating the relevant manufacturing parameters, for both mask shops and wafer fabs, into the database and tools used by the designer. This paper discusses the design-to-manufacturing flow and the interfaces currently in use. It then discusses the creation of a Universal Data Model (UDM) and its relationship with standard interchange formats. Specific data items to be included in the UDM database are listed, and a phased approach to initiate implementation is discussed. The emphasis is on specific, practical extensions of existing technologies, and the specific benefits to be derived. Particular attention is focused on the benefits as perceived differently by different users.

A shuttle mask has different chips on the same mask. The chips are not electrically connected. Alliance and foundry customers can utilize shuttle masks to share the rising cost of mask and wafer manufacturing. This paper studies the shuttle mask floorplan problem, which is formulated as a rectangle-packing problem with constraints of final die sawing strategy and die-to-die mask inspection. For our formulation, we offer a "merging" method that reduces the problem to an unconstrained slicing floorplan problem. Excellent results are obtained from the experiment with real industry data. We also study a "general" method and discuss the reason why it does not work very well.

The polymeric 157 nm pellicle was passivated on both sides to isolate it from environmental contamination. TAF pellicles were sputter deposited with 5 nm thick films of CaF₂, MgF₂, Al, Mg, TiN, SiN_x, Si, and PTFE, separately. The light transmission and life expectancy of the coated and uncoated pellicles were investigated. The coated pellicles were also analyzed with ESCA for surface structure changes. The coating process changed the pellicle's deterioration mechanism and life expectancy.

The next suite of optical lithography tools beyond 193nm will use 157nm irradiation to illuminate the mask pattern onto a semiconductor wafer. As the illumination wavelength decreases, the number of materials that can be used to create attenuated phase shift masks decreases dramatically. Especially the number of materials that maintain constant transmission after prolonged irradiation. The Ta-based and Cr-based materials have been recognized as two such sets of materials that remain optically unchanged due to prolonged VUV irradiation. Optical characterization of these materials by spectroscopic ellipsometry has been used to simulate several material systems to achieve proper transmission and phase shift while simultaneously improving the inspection contrast of the patterned mask. Both simulation and experimental results will be presented for Ta-based and/or Cr-based material systems that maintain relatively constant transmission for more than 50 million pulses under 157nm irradiation.

A new attenuated phase shifting film system for 157 nm lithography is presented. The system is designed for 6% transmission but is tunable to higher values. Tests for laser stability and chemical durability show excellent performance. First results of defect density and phase and transmission homogeneity are presented. The phase shifting film achieves a high etch selectivity to the substrate. The film system is extensible to be used as a high transmission phase shifter for 193 nm lithography. Further it is feasible to repair the film system using electron beam repair technology.

Two main issues with current pellicle frames are: (1) thermal expansion mismatch between the anodized aluminum frame and the photomask, and (2) the lack of porosity for purging and contamination control. Both issues can be addressed by using a sol-gel-derived porous silica frame. The silica frame has essentially the same thermal expansion coefficient as the fused silica photomask substrate. The porous nature of the silica frame provides contamination control by N₂ purging and scavenging capability. The porosity characteristics and mechanical properties of the frame material were determined. Porous silica frame was successfully mounted onto quartz plate by a commercial process, suggesting the suitability of using porous silica as pellicle frame material. The sol-gel derived porous silica represents the first proof-of-concept for an alternative frame material with a potentially significant impact on the photomask industry.

With advanced CMOS technologies, model-based optical proximity correction (OPC) has become the most important aspect of post-tape-out data preparation for critical mask levels. While fabrication processes certainly remain the foundation of a qualified technology, the quality of OPC is increasingly moving into the focus of efforts to further improve yield. For a typical model-based OPC tool, the full OPC model consists of two distinct parts: (1) An aerial image part, based on a few, well-defined optical parameters of the lithography tool to describe the light intensity distribution in air at the wafer level and (2) an empirical part to model all other aspects of the pattern transfer, based on different black box modeling techniques such as kernel convolution or variable threshold modeling. Most importantly, the parameters for the empirical part are usually determined by fitting the model to proximity data measured from test structures. As a consequence, the robustness of the full OPC model for productive usage correlates directly with the extent to which these test structures provide a representative sampling of the circumstances encountered in an actual product layout. In order to determine the quality of this sampling, full-chip aerial image analyses are performed for various mask levels of a product design. A comparison of the characteristics of the light intensity distributions of this design with the corresponding information obtained from the test structures reveals configurations that are not well covered by the latter. This insight allows the definition of suitable additional test structures in order to improve the robustness of subsequent empirical OPC models.

Variations in manufacturing process introduce uncertainties optical proximity correction. Discrepancies may arise between model extraction and the actual manufacturing conditions. An optimally constructed mask should minimize the sensitivity of line width variation in lithography and prevent pattern failure such a line pinch-off. In this paper, the effect of defocus on OPC mask and wafer patterning is investigated using a physical pattern transfer simulator, LithoScope. We evaluate the impact of defocus on a set of special test patterns and on a real circuit layout. We propose to control defocus effect by a combination of proper design centering and physical model-based data verification.

One of the best methods to increase correction accuracy in model based OPC is to decrease the correction segment length. As design rules shrink, this methodology is becoming more prevalent in model based OPC corrections. Unfortunately, it increases general mask feature complexity, which leads to reticles that are difficult to manufacture and inspect. With current OPC segmentation methodologies, the smallest correction segment length is generally applied uniformly across an entire correction set. A more targeted segmentation approach using the process model to determine sampling rates and locations could be used to confine complex correction features only to regions where they are absolutely necessary. For example, the choice between a hammerhead or dog-ear serif can be made using process model data so that dog-ear serifs are only used when flat aerial images are generated by the layout. This would lead to a more frugal correction that maintains correction accuracy while reducing mask construction complexity. OPC complexity is a key factor driving mask costs higher as design rules are pushed smaller. Methods for effectively reducing OPC complexity, without compromising OPC effectiveness, are being leveraged to help reduce the rate of NRE cost growth. In previous papers we have discussed methods for identifying features in which OPC accuracy can be sacrificed safely to reduce mask complexity. In addition, we have outlined methods for handling process variation effects for simple OPC shapes in complex regions. In this paper we will discuss another method for reducing OPC complexity while optimally preserving OPC accuracy on every feature. The method leverages pre-correction process simulation to predict the most “cost effective” shape for a feature. With simulated pattern characteristics and with consideration of potential mask rule violations, the method establishes an optimum correction shape “template.” For example, the choice between various line end-treatments can be determined up front, thus focusing the OPC computation on the most effective and least complex shape, and removing the need to perform post-OPC mask constraint shape adjustments. The implementation of this methodology leads to a more frugal correction that maintains correction accuracy while reducing mask construction complexity.

The challenge of delivering acceptable semiconductor products to customers in timely fashion becomes more difficult as design complexity increases. The requirements of current generation designs tax OPC engineers greater than ever before since the readiness of high-quality OPC models can delay new process qualifications or lead to respins, which add to the upward-spiraling costs of new reticle sets, extend time-to-market, and disappoint customers. In their efforts to extend the printability of new designs, OPC engineers generally focus on the data-to-wafer path, ignoring data-to-mask effects almost entirely. However, it is unknown whether reticle makers' disparate processes truly yield comparable reticles, even with identical tools. This approach raises the question of whether a single OPC model is applicable to all reticle vendors. LSI Logic has developed a methodology for quantifying vendor-to-vendor reticle manufacturing differences and adapting OPC models for use at several reticle vendors. This approach allows LSI Logic to easily adapt existing OPC models for use with several reticle vendors and obviates the generation of unnecessary models, allowing OPC engineers to focus their efforts on the most critical layers.

We report in this work experimental and theoretical results showing the effects of absorber reflectivity on standard flare measurements, image formation and how this may contribute to various image metrics used in lithography. Our study shows that under typical conditions the reflectance from the absorber film has only a small effect on the image produced by the exposure system.

In this paper, a quantitative evaluation of mask quality in the domain of 2D pattern fidelity and a method of assessing the OPC model effectiveness are investigated. The spirit of our algorithm is to characterize the wafer lithographic performances of both the real physical mask and the ideal OPCed layout mask that the physical mask is based on. To acquire these performances, we adopted a CD-SEM image process technique for transforming an actual SEM mask image into a simulation-friendly format like GDSII together with the methods to correctly handle the image transformation and interpret the simulation results. Finally, the images, such as the simulated aerial images, the simulated or observed resist top views, are superposed for comparison using logic operation.

Due to limitations in practical resolution of mask writers and mask fabrication processes, ideally square corners in a design become rounded on the actual mask (loss of pattern fidelity). This paper will show that the 2D quality of the mask does affect the printed image in state-of-the-art lithography, although it is not a major contributor and its effect is typically inferior to that of the design, the exposure conditions and the wafer stack. The influence of corner area loss on the mask has been illustrated before for line-ends. More recently it was demonstrated by simulation that for contact holes (CH) the location of area does matter when comparing the printability of a CH area obtained by a global bias or by serif addition. The purpose of the present study is to evaluate this influence towards wafer printing, i.e., to assess 2D mask features by their printability. The test layout includes CHs of various CDs with a range of global offsets and/or with square serifs on the corners, thereby varying width and placement. It is shown experimentally that the shape of the CH, or specifically the presence of serifs, influences the printed CH width. The deviation between the printing experiment and the simulation (starting from the design) is an indication of the fidelity of the serifs, which can be verified by mask quality assessment, for example by SEM. The work supports the determination of the MEEF (Mask Error Enhancement Factor) based on the square root of the CH area, but besides the area also the shape of the CH should be considered in the MEEF, as will become evident from the results.

Manufacturability and economical viability of etched quartz solutions for 65nm node critical layer lithography is assessed through evaluation of mask technology conversion complexity, mask process complexity, wafer processing cost and SRAM cell critical layer lithography performance. The etched quartz technologies under consideration are the full-layout alternating phase shift mask solution (FullPhase altPSM) and chromeless hard shifter phase shift mask solution (crlPSM). Using 0.63 NA exposures, we achieve k1 =0.29 (DOF=0.6um) and k1 =0.33 (DOF=0.8um) for altPSM and crlPSM, respectively. 60nm isolated feature DOF is more than 0.8um for altPSM. The crlPSM isolated feature DOF without sub resolution assist features is about 0.3um. Simulations results of crlPSM isolated features with sub resolution assist features using NA=0.75 show that DOF of 0.3um is attainable for crlPSM. Experimental results are used to calibrate wafer volume cross over model for these competing technologies with specific focus on die size, k1 and DOF related yield as wafer processing cost drivers. Results show that altPSM has lower wafer processing cost due to better lithography yield at smaller die sizes. Thus, though the mask set of altPSM solution is more expensive than crlPSM, the altPSM solution is more economical for high volume production of 65nm node technologies. The wafer volume crossover model allows for the most cost effective mask solution to be employed for a given logic device and wafer volume expectation.

Resolution Enhancement Techniques (RET), or low k1 imaging, has been deployed successfully to extend the resolution limits of optical lithography significantly below half-λ for today's poly gate mask in the state-of-the-art manufacturing processes. However, achieving satisfactory contact hole patterning through the full pitch range required for the 90nm and 65nm technology nodes has greatly challenged the leading process development effort. Currently, attenuated PSM's with transmission between 5% and 9% are used to enhance the resolution of dark field contact hole patterns. Using conventional illumination with a low sigma, which is the common method employed for att-PSM, limits the minimum pitch that can be resolved on the wafer. By using off-axis illumination (OAI) it is possible to image smaller pitches. However, the same attributes that enhance imaging for dense patterns severely degrade the imaging of isolated patterns. Using Chromeless Phase Lithography (CPL), sub-wavelength isolated contact patterns can be imaged using strong off-axis illumination, such as Quasar, dipole and double dipole, etc. By applying modeled sub-resolution and non-printing features, we found it is possible to achieve very high-resolution contact imaging with exceptional process latitude. Both phase shifted and non-phase shifted patterns can be much larger than sub-resolution assist features (or anti-Scattering Bars) used on dark field binary reticles (~three times larger), making the reticle pattern easier to manufacture. Using this method, sub-wavelength bright patterns on a dark field can be imaged through the full pitch range. We have shown that it is feasible to push the contact resolution limit to 0.33 k1 or smaller.

Printed resist images of pattern and probe-based aberration monitors at 248 nm wavelength on an AIMS tool and a projection printer at several NA's will be presented. The results will demonstrate the measurement operation of these monitors compared to their performance as designed through simulation. Initial experiments indicate that the focus monitor has sufficient sensitivity to see systematic focus trends across the die. The focus monitor is estimated to measure focus to 25nm accuracy of 1/8 of the Rayleigh depth of focus, indicating a 2-8x improvement over determination of best focus via the point spread function. This work also shows that the optimum conditions for reading the targets is when the intensity of the probe is just at the exposure threshold of the resist. The target designed to detect coma abberation did not work as expected and this is likely due to the electromagnetic performance of the mask and high-NA vector imaging effects.

There has been a proliferation of examples of mask cost projections for future ITRS nodes and various technologies. This paper reviews the methodology developed at SEMATECH to insure that projected mask costs reflect the geometries being planned. A detailed description provides the development of the mask manufacturing process and develops a projected cost.

Improvements in mask making techniques and metrology strategies have been required to satisfy the requirements of the 90nm technology node. With decreasing k1 and increasing MEF, critical dimension uniformity and defect specifications have faced severely tightened requirements. Many of the mask making process enhancements inspired by the 90nm node can be retrofitted into the 130nm node which improves mask quality as well as wafer-level performance. Mask critical dimension uniformity improvements directly impact wafer across chip linewidth variation which results in significantly improved chip performance. Specific examples of 130nm chip performance improvement will be discussed. Mask critical dimension and defect density improvements also result in improved mask yield and reduced mask costs. Driving 90nm mask process learning back into 130nm mask production significantly improves 130nm performance. Close interaction with the wafer lithography team allows focus on critical process window improvements for both the mask maker and wafer lithographer and allows rapid implementation of high-end process learning into older technologies.

Microelectronics industry leaders routinely name mask technology and mask supply issues of cost and cycle time as top issues of concern. A survey was initiated in 2002 with support from International SEMATECH (ISMT) and administered by SEMI North America to gather information about the mask industry as an objective assessment of its overall condition.1 This paper presents the results of the second annual survey which is an enhanced version of the inaugural survey building upon its strengths and improving the weak points. The original survey was designed with the input of member company mask technologists, merchant mask suppliers, and industry equipment makers. The assessment is intended to be used as a baseline for the mask industry and the microelectronics industry to gain a perspective on the technical and business status of the critical mask industry. An objective is to create a valuable reference to identify strengths and opportunities and to guide investments on critical-path issues. As subsequent years are added, historical profiles can also be created. This assessment includes inputs from ten major global merchant and captive mask manufacturers representing approximately 80% of the global mask market (using revenue as the measure) and making this the most comprehensive mask industry survey ever. The participating companies are: Compugraphics, Dai Nippon Printing, Dupont Photomask, Hoya, IBM, Infineon, Intel, Taiwan Mask Company, Toppan, and TSMC. Questions are grouped into five categories: General Business Profile Information; Data Processing; Yields and Yield loss Mechanisms; Delivery Time; and Returns and Services. Within each category are a multitude of questions that create a detailed profile of both the business and technical status of the mask industry.

A mask patterning technology for the 90nm technology node has been developed using the FujifilmARCH resist FEP171 and the state-of-the-art mask making tools SteagHamaTech mask coater ASR5000, Leica 50kV variable shaped e-beam writer SB350, SteagHamaTech developer ASR5000 and UNAXIS Mask Etcher III. A resist resolution of below 100nm dense lines and 150nm contact holes was demonstrated. The line width shrinking due to chrome etching varies between 25nm and 50nm per feature and a corresponding resolution of 125nm dense lines in a 105nm thick chrome absorber has been achieved. The global CD-uniformity with a 3σ of 7.7nm and a total range of 10.8nm met the requirements of the ITRS roadmap. The local uniformity with a 3σ of 3.8nm and a range of 5.6nm offers potential for future application of the Leica SB350. Applying of a new correction method taking electron scattering and process characeristics into account provides a linearity of 6.1nm. In addition, the line width of different featurees was kept in a range up to 12nm when the local pattern density was changed. The composite placement accuracy of 12nm fulfills already the requirements of the 65nm node. A special investigation proved the excellent fogging depression of the SB350.

For many years, laser pattern generation has been printing on i-line resists. As features sizes continue to shrink, laser pattern generation is moving to DUV laser wavelengths, and a production worthy resist process is needed. Characteristics such as standing waves, resist foot and CD drift under and after exposure have previously challenged efforts to migrate 248nm stepper chemically amplified resists (CARs) to mask making applications. In this study the performance of a commercially available 248nm laser/e-beam resist solution is examined in the Sigma7000 series laser pattern generators. To achieve virtually no resist foot as well as tight CD control the optimum process conditions for DUV laser applications were determined. Cross-sectional and top-down scanning electron microscopy analysis was performed to evaluate the resist and dry etch processes. A comparison is made with the resist DX1100P, used in initial stages for DUV pattern generators development. The new resist also benefits from being well established in mask making e-beam mask writers.

Improvements in the final uniformity of masks can be shrouded by error contributions from many sources. The final Global CD Uniformity (GCDU) of a mask is degraded by individual contributions of the writing tool, the Post Applied Bake (PAB), the Post Exposure Bake (PEB), the Develop sequence and the Etch step. Final global uniformity will improve by isolating and minimizing the variability of the PEB and Develop. We achieved this de-coupling of the PEB and Develop process from the whole process stream by using “dark loss” which is the loss of unexposed resist during the develop process. We confirmed a correspondence between Angstroms of dark loss and nanometer sized deviations in the chrome CD. A plate with a distinctive dark loss pattern was related to a nearly identical pattern in the chrome CD. This pattern was verified to have originated during the PEB process and displayed a [Δ(Final CD)/Δ(Dark Loss)] ratio of 6 for TOK REAP200 resist. Previous papers have reported a sensitive linkage between Angstroms of dark loss and nanometers in the final uniformity of the written plate. These initial studies reported using this method to improve the PAB of resists for greater uniformity of sensitivity and contrast. Similarly, this paper demonstrates an outstanding optimization of PEB and Develop processes.

Negative-tone chemically amplified resists (nCARs), like NEB22 are promising candidates for next-generation lithography, e.g. 90 nm and 65 nm technology node and next-generation lithography. For these resists, e-beam exposure and post-exposure bake (PEB) are most critical processes, since these resists show a strong sensitivity to post-exposure delay (PED) in vacuum during e-beam writing of about 0.5 nm/h, and in air while waiting for PEB. Further, such resists show a strong PEB temperature sensitivity of up to 8 nm/K. The multi-zone hotplate approach of the APB AFB 5500 bake system with its use prior temperature uniformity results in excellent global CD-uniformity already. However, all kinds of systematic large area effects of processes, e.g. blank coat/bake, exposure, PED, the PEB itself, etch loading, etc. may transfer in additional systematic CD-errors. Such systematic, repeatable errors can be reduced during PEB by superimposing an appropriate non-uniform temperature profile onto the regular, optimized uniform bake temperature profile, thereby compensating for such CD-non-uniformities. The required temperature profile can automatically be calculated from a suitable gobal CD measurement, determined in a typical process flow. The compensation of CD-errors resulting from vacuum PED and hotplate temperature characteristics is demonstrated here, by using automated temperature profile calculation. The global CD uniformity was improved significantly, the achieved results show a typical reduction of about 20-30%, from a total global range of about 9nm to about 6-7nm on leading-edge production photomasks.

As feature sizes of phase shift mask (PSM) have dropped below half-micron, resist adhesion have become a more critical issue, especially during second level lithography. Second writing process requires special consideration, because the resist's mechanical strength of resists on patterned chrome and patterned glass is smaller in comparison to that on the un-patterned chrome blank. If the adhesion strength is not sufficient to withstand the stress during subsequent processes, patterns will be damaged during second level lithography. Resists stress at pattern edges that subsequent processes, pattern will be damaged during second level lithography. Resist stress at pattern edges that weaken its adhesive property, together with the low mechanical strength of resists on glass, creates ample probability for the unwanted phenomenon in PSM process. In this paper, we investigate the effects of property and adhesive strength of resists on surfaces at different treatment before resist coating process, and observe the defects generation after different treatment.

New types of analog gray-scale laser direct-write masks have been created using bimetallic thermal resists and a direct- write laser process. Bimetallic resists consist of two layers of thin films, eg. Bi over In or Sn over In, which react to form a low temperature alloy when a laser raises the films above the eutectic temperature. Depending on the exposure energy, resulting alloyed layers appear to become oxides, causing a change of absorption at 365nm from >3OD to <0.3OD. The thermal resists show near wavelength invariance from IR to UV. The Sn/In films, each layer ~40 nm thick, were DC-sputtered onto glass slides or quartz substrates. To make gray-scale photomasks the samples were placed on a computer-controlled high accuracy X-Y table. A bitmap gray-scale pattern was raster-scanned with a CW Argon laser (514 nm) beam. An optical shutter controlled the actual laser power applied onto the thermal resist film according to the gray-scale value. When exposed to a laser beam greater than 0.6 W, the Sn/In film became nearly transparent (0.22OD) at I-line (365nm) wavelength. Sn/In and Bi/In photomasks have been used together with a standard mask aligner to successfully pattern Shipley SPR2FX-1.3 photoresist. CF₄/O₂ plasma etching has been used to transfer the three-dimensional pattern to SiO₂ and Si substrates. Also a 160 beam laser diode thermal imaging tool was used to create BiIn direct-write binary masks.

One of the major challenges in alternating aperture phase shift mask (AAPSM) production is the variability of the glass etch rate as a function of exposed area (pattern loading) on the mask. The lack of an endpoint system means that the etch is entirely based on time, and the result is increased variability in the mean etch depth as well as decreased yields against ever tightening phase specifications. If a transmissive etch stop layer were placed underneath an appropriate thickness of glass to obtain a 180-degree phase shift, the result is a forced endpoint at exactly 180 degrees every time. Such a film system also leads to many process advantages over conventional AAPSM processes. This paper discusses the film stack deposition and maskmaking at Photronics, Inc. and details the process advantages of using AAPSM blanks with etch stop layers.

Sub-pellicle particle formation continues to be a significant problem in semiconductor fabs. We have previously reported on the identification of various defects detected on reticles after extended use. This paper provides a comprehensive evaluation of various molecular contaminants found on the backside surface of a reticle used in high-volume production. Previously all or most of the photo-induced contaminants were detected under the pellicle. This particular contamination is a white "haze" detected by pre-exposure inspection using KLA-Tencor TeraStar STARlight with Un-patterned Reticle Surface Analysis, (URSA). Chemical analysis was done using Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS) and Raman spectroscopy.

The integration of 193nm Lithography is close to full production for the 90nm node technology. With the potential of emerging 193nm lithographic resolution down to 65nm, the quality of 193nm reticles including binary, EAPSM and AAPSM must be outstanding so that low K1 factor reticles may be used in production. One area of concern in the IC industry is haze contamination on the mask once the reticle has been exposed to ArF radiation. In this study, haze was found outside of the pellicle and on the quartz side of the mask. Standard through-pell inspections will typically miss the contamination, yet its severity can ultimately affect mask transmission. For this reason, DuPont Photomasks and Cypress joined forces to quickly decipher how it develops. In this investigation, tests were devised which altered conditions such as mask environment, exposure, traditional and advanced cleaning chemistry. This paper describes the relationship between surface and environmental photochemical reactions, the resultant growth, analysis, and how it is controlled.

Yield Mask, the first commercial Yield Management tool specifically developed for a Mask House, has been introduced and the necessity for such Yield Management system, given the current demands on high-end mask production, ascertained. In particular, Yield Mask has been shown to be a highly effective, defect-data analysis tool, with fully automated data collection and a database structure facilitating fast and flexible data retrieval and correlation, for process, inspection, SEM-review and repair data. The latest features of Yield Mask are now reported, including macros, user-definable sampling, user-definable grouping and defect tracking. These features are shown to enhance the efficiency of Yield Mask in a production environment. Macros are shown to significantly decrease the manpower required to run standard analysis routines, accommodating continuous monitoring and analysis of the data. User-definable sampling is shown to allow users to select defects of particular interest, within a given inspection report for subsequent SEM review. This significantly increases the efficiency of review carried out using basic sampling criteria. Lastly, user-definable grouping, along with defect tracking are shown to be advantageous in the selection of any, desired combination of data, for comparison and/or correlation.

As the semiconductor industry continues to scale down critical dimensions (CD), proximity effects get more and more severe. As such, aggressive Optical Proximity Correction (OPC) features like hammerheads, serifs and assist bars inevitably appear on fabricated masks. The great challenge, however -- to reliably assure the quality of these advanced masks -- is to be able to directly judge a controversial defect under such complex features. It is necessary to find a more effective way to accurately disposition the defects found on these masks. Simulation-based defect disposition strategies have now become much more important for judging defect printability. In this paper, we will study and characterize the printability prediction of various defects on high-end masks by Virtual Stepper® System with its improved Automated Defect Severity Scoring (ADSSTM) function. Both line-space masks with aggressive OPC features like assist bars and attenuated PSM with contact features with small sizes were used to verify the simulation engine and ADSS algorithm in this study. The Virtual Stepper simulation and defect impact analysis results (the automatically calculated Defect Severity Score) will be compared to the SEM images and measurements of wafer prints using 248nm lithography. In addition, production reticles are also used to compare the accuracy and efficiency of ADSS with human review. A new defect disposition flow is also tentatively proposed here to demonstrate that the Virtual Stepper System with its ADSS feature can provide its user with an automated, fast and accurate way of analyzing the impact of a defect. The Virtual Stepper System with ADSS function has been shown to be a suitable tool for photomask defect criticality assessment in mask shops and wafer fabs.

A new DUV high-resolution reticle defect inspection platform has been developed to meet the sub-90nm node 248/193nm lithography reticle qualification requirements of the IC industry. This advanced lithography process typically includes COG layers, EPSM layers, and AltPSM layers; aggressive OPC is typically used which includes jogs, serifs, and SRAF (sub-resolution assist features). The architecture and performance of the new reticle defect inspection platform is described. Die-to-die inspection results on standard programmed defect test reticles are presented showing typically 50nm edge placement defect sensitivity, 80nm point defect sensitivity, 5.5% flux defect sensitivity, and 100nm quartz phase defect sensitivity. Low false detection results are also shown on 90nm node and below product reticles. Direct comparisons with UV wavelength inspections show measurable sensitivity improvement and a reduction in false detections. New lithography oriented defect detectors are discussed and data shown.

With expected implementation of low k1 lithography on 193nm scanners for 65nm node wafer production, high resolution defect inspection will be needed to insure reticle quality and reticle manufacture process monitoring. Reticle cost and reticle defectivity are both increasing with each shrink to the next node. Simultaneously, system on chip (SoC) designs are increasing in which a large area of the exposure field typically contains dummy patterns and other features which are not electrically active. Knowing which defects will electrically impact device yield and performance can improve reticle manufacturing yield and cycle time -- resulting in lower reticle costs. This investigation examines the feasibility of using additional design data layers for die-to-database reticle inspection to determine in real time the relevance of a reticle defect by its location in the device (Smart InspectionTM). The impact to data preparation and inspection throughput is evaluated. The current prototype algorithm is built on the XPA and XPE die-to-database algorithms for chrome-on-glass and EPSM reticles, respectively. The algorithms implement variable sensitivity based on the additional design data regions. During defect review the defects are intelligently binned into the different predetermined design regions. Tests show the new Smart Inspection algorithm provides the capability of using higher than normal sensitivity in critical regions while reducing sensitivity in less critical regions to filter total defect counts and allow for the review of just defects that matter. Performance characterization of a variable sensitivity Smart Inspection algorithm is discussed in addition to the filtering of the total defect count during review to show the defects that matter to device performance. Using seven critical layer production reticles from a system on chip device we examine the applications of Smart Inspection by layer including active, poly, contact, metal and via layers. Data volume for additional data layers show little impact to inspection data prep time. The total area of the reticle where defects do not matter is as high as 70% on some layers. Review capabilities will be examined for various applications such as reviewing defects in the various regions such as SRAM, dummy pattern, and redundant contact/via specified regions. Lastly, the economics of Smart Inspection will be modeled using the collected knowledge of the applications from the production reticle characterized in this investigation.

The industry roadmap for IC manufacturing at design rules of 90nm and below foresees low k1-factor optical lithography at 193nm exposure wavelength. Aggressive model-based OPC are being used more and more frequently in order to achieve the extremely tight mask CD specifications required by 90nm technology node. State-of-the-art mask inspection is challenged to detect CD defects close to metrology resolution. Inspection of OPC is critical; OPC feature dimensions are usually near or below the resolution limits of mask exposure. In addition, chrome defects can be semitransparent and change the intensity of light on the wafer. In this paper aerial-image based mask inspection is investigated and presented. The concept inspects a given mask based on its aerial image with selected wafer exposure conditions, thus “finds only defect which will print”. This paradigm shift in mask inspection philosophy provides the unique opportunities of verifying and controlling the entire aerial image generated by the inspected mask. As reticle enhancement techniques like OPC are designed to enhance the aerial image of a mask, this concept offers a comprehensive way of inspecting these techniques. The inspection is shifted from detecting every single minor change on mask to detecting what on mask could possibly impact the printing image quality on the wafer. In this paper an advanced application of aerial-image based mask inspection is discussed in more detail. As a standard, the Aera193 uses the best-focus aerial image for defect detection. From HNA mask inspection it is a well-known fact, that shifting the inspection off-focus, can provide a more sensitive detection. In the csase of aerial-image based inspection, going off-focus can be compared with lithography exposure out of focus. In other words, the lithography process window will be taken into account for defect detection. This methodology provides additional important information ·Understand process window printability of defects detected at best-focus ·Detect additional defects, which may print at the borders of the process window. This information is of extreme value for wafer lithography and may help by decisions about lithography process and mask usage. Focus of the paper is to analyze the application of aerial image-based off-focus inspection. Advanced OPC test plates are used to analyze detection at best and off-focus. The inspection results are compared to actual wafer results. Wafer lithography benefit is discussed.

Cleaning is one of the most important processes in photomask manufacturing, because the smallest particles may be printable on wafers. Moreover, mask cleaning requirements are stricter than that for wafers because masks are the master image from which all wafers prints will be made. We now face difficult challenges as we enter the 90nm era with 193nm DUV lithography and more prominent use of phase shifting applications. As defect sizes to be controlled in the cleaning process decrease, cleaning performance depends not only on conventional chemical treatments and megasonic hardware, but also on new cleaning methods such as UV/Ozone treatment. We investigated and compared the cleaning performance of UV/Ozone treatment + traditional chemical cleaning methods with standalone conventional wet chemical cleaning methods on glass, chrome, and MoSiON blank surfaces over pattern densities at 70% and 30% clear in the pattern area. Contact angle measurements and wettability tests were performed as well to evaluate cleaning performance results. The cleaning effectiveness with different drying methods on EAPSMs has been also investigated by controlling phase and transmission of KrF EAPSMs to within ±3'and ±0.3% respectively. Overall, it was found that the UV/Ozone pre-treatment combined with the traditional chemical cleaning process results in a better particle removal rate compared to conventional cleaning methods when it comes to removing the smallest mask particles., and it did not adversely affect EAPSM optical properties.

The SIR5000 mask repair system was developed with an FIB system featuring new ion optics, modified SED detectors, new platform software and optimized repair processes to repair 130nm/ArF generation masks. Thereafter we have continuously improved it for 90nm/ArF lithography and evaluated its performance such as edge placement repeatability, lithography simulation and printing tests. The transmittance of FIB imaging area is more than 95% over 70 times scans, and the printing result data also shows that the imaging damage by FIB scans little affect CD until around 70 times. The ED windows of both repaired clear and opaque defects almost overlap non repaired reference ones, and they show that the printing performance of repaired mask does not have any printing issues. Consequently, we demonstrated that the improved SIR5000 capability has reached the 90nm node mask technology requirement.

For Chrome binary masks, FIB defect repair has become increasingly challenging as feature sizes and exposure wavelengths are reduced. Chrome opaque defects are typically the most difficult to remove due to the lack of a highly effective gas chemistry for enhancing the FIB removal process. Repair artifacts such as gallium staining from ion beam exposure, quartz damage and re-depsoited material are all important factors to be considered. New processes continue to be developed to extend FIB mask repair to the 100nm lithography node using a 193nm exposure wavelength. FEI, under an International Sematech funded program has developed processes to target the following criteria: Edge Placement: 15nm, 3σ; Transmission: >95%, λ=193nm; Maximum Quartz Damage: <10nm before post processing. Ideally, these specifications should be met simultaneously. However, in the case of quartz damage, it is of greater importance to consider the volume of damage after post-processing. Chrome opaque defects on previous generations of mask have typically been removed by a first step using a combination of etching gases which enable the removal of chrome and a second repair step which, in combination with a focused gallium ion beam, removes the gallium implanted quartz resulting from the initial chrome removal. The primary issue becomes a transmission loss mainly due to excessive quartz damage resulting from the gallium removal and also a trench (commonly referred to as 'riverbed') that was created during the initial chrome removal step. An edge bias into the chrome line is commonly used to restore transmission at best focus, typically measured at the exposure wavelength on AIMS (Aerial Image Measurement System). However when repairs are evaluated against the emerging specification of AIMS through focus variation, it becomes apparent that it is mroe desirable to use a process that provides les CD variation through focus.

One of the key challenges for the successful implementation of EUV Lithography (EUVL) is the supply of defect free mask blanks. Obviously a reliable defect inspection is a prerequisite to achieve this goal. We report results from a EUVL blank inspection tool developed by Lasertec. The inspection principle of this tool is based on confocal microscopy at 488nm inspection wavelength. On quartz substrates a sensitivity of 60nm is demonstrated. On buried defects in the multilayer stack a reasonable capture rate down to approximately 25nm defect height has been measured. We compare these results to previously reported data on the wafer version (M350) of the current M1350.

Extreme Ultraviolet Lithography (EUVL) is the leading candidate for manufacturing integrated circuits beyond the 45-nm technology node. The masks for EUVL are reflective and significantly different from current transmission masks for deep UV lithography. Many authors have demonstrated the patterning of EUVL masks using different types of absorber stacks that were deposited on top of the multilayer reflector. More recently, a new approach based on the etching of the multilayer reflector in order to define the mask pattern was proposed [2]. Using rigorous electro-magnetic simulations, it was shown that this subtractive approach could provide better process latitude, less H-V bias and smaller image-placement errors compared to the traditional masks based on the additive method. Even though the mask processing shows interesting challenges, this approach might offer immediate advantages over the more traditional patterning technique using the absorber stack, beyond those predicted for lithography imaging. These include the possibility to use optical inspection in transmission mode, which can provide the high-contrast images that are essential for high-sensitivity detection of small defects. In this paper, we present the first results on the patterning of EUVL masks using the direct etching the EUVL multilayer reflector (Mo/Si type) to produce EUV binary masks. In particular, we show how the process parameters can be adjusted to control the pattern sidewall angle. We also present an analysis of the influence of this sidewall angle on lithography imaging, based on lithography simulations. Finally, we show results from the optical inspection of these etched-multilayer binary masks (EMBM).

Extreme ultraviolet lithography (EUVL) is one of the leading candidates for next-generation lithography in the sub-65 nm regime. The International Technology Roadmap for Semiconductors proposes overlay error budgets of 18 nm and 13 nm for the 45 nm and 32 nm nodes, respectively. Full three-dimensional finite element (FE) models were developed to identify the optimal mask thickness to minimize image placement (IP) errors. Five thicknesses of the EUVL reticle have been investigated ranging from 2.3 mm to 9.0 mm. The mask fabrication process was simulated, as well as the e-beam mounting, pattern transfer, and exposure mounting, utilizing FE structural models. Out-of-plane distortions and in-plane distortions were tracked for each process step. Both electrostatic and 3-point mounts were considered for the e-beam tool and exposure tool. In this case, increasing the thickness of the reticle will reduce the magnitude of the distortions. The effect of varying the reticle thickness on chucking was also studied. FE models were utilized to predict how changing the reticle thickness would affect the overall clamping response. By decreasing the reticle thickness (and therefore the effective bending stiffness), the deformed reticle is easier to flatten during chucking. In addition, the thermomechanical response of the reticle during exposure was investigated for different reticle thicknesses. Since conduction to the chuck is the main heat dissipation mechanism, decreasing the reticle thickness results in more energy being conducted away from the reticle, which reduces the maximum temperature rise and the corresponding thermal distortion. The FE simulations illustrate the optimal thickness to keep IP errors within the allotted error budget as well as provide the necessary flatness during typical chucking procedures.

Conventional lithography techniques have been losing their ability to easily support continuous shrinking of feature sizes, especially when the pattern half-pitch is <60 nm. EUV lithography is one of the leading contenders to replace these conventional techniques. Because the EUV mask structure is many times thicker than the illumination wavelength, scalar Fraunhofer diffraction calculations cannot describe the scattering of light from the EUV masks with enough accuracy. In this paper, we present a rigorous 3-D electromagnetic field simulator for EUV masks. The simulator is based on a 3-D waveguide method developed to calculate the characteristics of the light scattered from nonplanar EUV masks. A typical EUV mask contains as many as 80 reflective layers in addition to the absorbing layers, and we have developed a fast method to calculate the scattering matrix of the reflective layers. Also, based on the existing numerical techniques, we can describe the light scattering in the absorbing layers with complex index of refraction. The simulator has been recently modified to handle oblique illumination conditions, and this is the focus of our paper. Aerial images are calculated in the image plane of a typical EUV stepper, and a threshold resist model is used to predict the printed pattern size. We will first compare our work with published results on dense and isolated lines. Then, we will describe the results of our calculations for two-dimensional patterns (e.g., contacts and islands) under oblique illumination. The typical simulation time is less than 10 hours on a desktop workstation for two-dimensional patterns.

A fine pixel CD-SEM system is developed. The convnetional CD-SEM Topcon MI-3080UR system consists of main body, 512 pixel SEM image acquisition system and 1D pattern size measurement system. The fine pixel CD-SEM system is added the conventional CD-SEM TOPCON MI-3080UR system. The fine pixel CD-SEM system consists of 2048pixel SEM image acquisition system is used by adjusting a novel measurement algorithm for the SEM image of 2D patterns. Firstly, the necessity of the fine pixel CD-SEM is discussed from the viewpoint of getting good repeatability of pattern size measurements. Effective factors causing the good repeatability for pattern size measurements are studied. The effective factors are mainly SEM image quality and pattern measurement algorithm. Secondly, repeatability of 2D pattern measurements by using the developed fine pixel CD-SEM image and the novel algorithm are evaluated. The evaluated 2D patterns are used for hammer head type OPC patterns for DRAM cell pattern. Finally, we investigate the usefulness of the fine pixel CD-SEM by usign the same novel algorithm for comparison of the conventional and the fine pixel CD-SEM.

SEM Metrology becomes the standard metrology for the mask industry, as the precision and accuracy requirements tighten continuously. In this paper we consider the basic requirements for performing 2D measurements of the reticle, such as contact area and corner roundness as well as the algorithmic development to generalize a solution for these requirements. We consider three main requirements from such algorithm: a) To be generic and deal with general shape features. b) To measure new geometric metrics - such as contact area and corner roundness. c) TO measure new geometric patterns suhc as OPC features and small CDs. These challenges require the development of new algorithms for CD metrology. These algorithsm perform detection and measurement of new geoemtric objects, and provide the repeatability and robustness for reticle production process control. In the first part of the paper we will describe the novel algorithm for detection of general shape features - "Region Connectivity Extraction". In the second part of the paper, we will provide mathematical tools that we have implemented for analyzis of corner roundness of noisy contours and demonstrate the performance of these algorithms for synthetic contours of different shapes with different noise levels. We will conclude with the application of our algorithm and analysis of real SEM images of the reticle features.

Direct phase-shift measurement is one of the key technologies to realize Phase-Shift-Mask (PSM) application. Most mask makers are developing practical PSMs for 157nm lithography. Final tuning of the optical parameters and quality assurance of them require accurate measurement tool of phase-shift and transmittance with 157nm light illumination. In this paper, we will report the development of the system, which measures the phase-shift and transmittance of 157nm PSM at wavelength. This system has a 157nm F₂ laser as a light source of the illumination and CaF₂ optics with a CCD camera for the imaging. Key component is the interferometer, which has a function of lateral image shearing and phase modulation. The same technology is used in the current UV and DUV tools already exist. N₂ purge and vacuum environments are newly introduced for the optical path to minimize attenuation of 157nm light by O₂ and H₂O. A fluctuation of the attenuation in the optical path significantly affects the short-term measurement repeatability. A new measurement algorithm, which uses two measurement spots on a PSM image, gives better repeatability than using single measurement spot under such unstable condition. Because most fluctuations are common elements to both of the two spots, they can be canceled out by the new calculation algorithms for phase-shift and transmittance measurements. The system with new techniques shows enough performance for the requirement of 157nm PSM measurements with new techniques.

Optical Critical Dimension (OCD) measurements using Normal-Incidence Spectroscopic Ellipsometry (polarized reflectance) allow for the separation of transverse electric and transverse magnetic modes of light reflected from an anisotropic sample as found in a periodic grating structure. This can provide the means for determining linewidths and analyzing complex profiles for a variety of structures found in mask fabrication. The normal-incidence spectroscopic ellipsometer maintains much of the simplicity in mechanical design found in a standard reflectometer and the additional polarizing element has no effect on the footprint making the system amenable for integration, inline monitoring and advanced process control. The rigourous coupled wave analysis (RCWA) method provides an exact method for calculating the diffraction of electromagnetic waves by periodic grating structures. We have extended OCD technology to critical measurement points in the mask fabrication process: After development inspection (ADI), where OCD evaluates mask writer performance and after etch inspection (AEI) for monitoring and control of etched quartz structures for phase shift applications. The determination of important, critical dimensions via optical techniques is appealing for several reasons: the method is non-destructive to photoresist and the sample is not subject to charging effects; the technique is capable of measuring the critical dimensions of grating structures down to approximately 40 nm; minimal facilities are required for installation (no high vacuum, cooling or shielding of electromagnetic fields); like optical thin film metrology, OCD technology can be integrated into process tools enabling Advanced Process Control (APC) of the etch process. Results will be presented showing the capabilities of OCD metrology for ADI and AEI applications. Comparisons will be made with both CD-SEM and X-SEM and the application to monitoring/controlling the quartz etch process will be discussed.

HL-7000M electron beam (EB) lithography system has been developed as a leading edge mask writer for the generation of 90 nm node production and 65 nm node development. It is capable of handling large volume data files such as full Optical Proximity Correction (OPC) patterns and angled patterns for System on Chip (SoC). Aiming at the technological requirements of the International Technology Roadmap for Semiconductors (ITRS) 2002 Update, a newly designed electron optics column generating a vector-scan variable shaped beam and a digital disposition system with a storage area network technology have been implemented into HL-7000M. This new high-resolution column and other mechanical components have restrained the beam drift and fluctuation factors. The improved octapole electrostatic deflectors with new dynamic focus correction and gain alignment methods have been built into the object lens system of the column. These enhanced features are worth mentioning due to the achievement of HL-7000M's Image Placement (IP) performance. Its accuracy in 3σ of a 14 x 14 global grid matching result over an area of 135 mm x 135 mm measured by Leica LMS IPRO are X: 6.09 nm and Y: 7.85 nm. In addition, the shot astigmatism correction has been in the development and testing process and is expected to improve the local image placement accuracy dramatically.

It is intended to evaluate the feasibility of 0.15μm generation mask fabrication with a KrF photomask repeater. Inter-field registration accuracy(3sigma) is 28nm in X direction and 45nm in Y direction on a daughter mask in the KrF photomask repeater process and that is out of the registration specification(3sigma 30nm) of 0.15μm generation mask. The intra-field registration accuracy(3sigma) within a 18.4mm × 23.0mm field on a daughter mask is about 9nm with compensation of mis-registration to a mother mask. Inter-field CD uniformity(3sigma) is 8nm on a daughter mask and intra-field CD uniformity(3sigma) can be improved into 15nm with the compensation of CD error to a mother mask. Pattern fidelity in the KrF photomask repeater is inferior to that of the e-beam process. Hence it is necessary to apply OPC pattern to a mother mask in order to fabricate the 0.15μm generation mask.

In order to analyze a simultaneous correction of fogging and loading effect, the e-beam lithographic simulation was performed with dose modulation method. The in-house e-beam simulator which adopts Monte-Carlo method for electron scattering is used for performing Proximity Effect Correction (PEC) and fogging correction during the e-beam lithographic processes. Various values of theta, representative parameter which describes the deposited energy by fogging, are used for simulation. Fogging effect is well known phenomenon which is the additional energy deposition into large exposed area by second electron scattering, and this fogging correction is successfully achieved by dose modulation method. However, etch loading cannot be compensated properly by modulating dose due to its unique property. From the simulation results, it is obviously necessary to correct etch loading effect and fogging effect simultaneously in order to cure global and local CD errors. The bigger loading effect is, the bigger local CD error induced by dose modulation method is to be generated. This global error is reducible but irremovable perfectly owing the discrepancy between the property of etch loading effect and dose modulation. However, the proper selection of eta, the ratio of the energy deposition into resist from the back scattering electrons verse the forward scattering electrons, can remarkably reduce the global and local CD errors. As a consequence, the method of the dose modulation is not the perfect way to correct the CD errors induced by etch loading or positional induced error. Nevertheless, the dose modulation method with variable eta can be an alternative way to control the designed CD because of its precision and rapidity.

The specifications of mask critical dimension (CD) have become much tighter for sub-100nm nodes to satisfy wafer CD uniformity requirements. The small patterns produced by aggressive optical proximity correction compound the difficulty, thereby necessitating the use of e-beam writers in combination with chemical amplified resists (CARs). Challenges of resists include post coating delay (PCD), post exposure delay (PED) in vacuum, and strong post exposure bake (PEB) sensitivity. CD errors are classified into localized area and global ones; machines causing each type of errors are then identified. Focus variation and fogging effect have to be emphasized for the 65-nm requirements. Although the DOF of e-beam systems is larger than that of the optical systems, high current density and/or plate-to-plate deviation may cause focus variation to result in poor CD uniformity. Therefore, dosage optimization is necessary for getting the best focus. The fogging effective level is around 3~10 nm at various pattern loadings. The paper presents, quantitative results and the methodology leading to them.

Studies on Cr etch and its kinetics were carried out using a 50KeV photomask e-beam writing system, an ICP plasma etcher, chemically amplified resist (CAR), and a scanning electron microscope (SEM) metrology tool. A Cr etch rate equation was developed, showing good agreement with experimental data. Both the theoretical rate equation and experimental results showed that the main Cr etch rate effect parameters were oxygen mass flow rate, oxygen partial pressure, and ICP power. It was found that pressure plays a very important role in critical dimension (CD) uniformity etch contribution, loading effects, isolated/dense (I/D) etch CD bias, and etch CD movement. Etch kinetic information was found to be very helpful for improving CD uniformity, reducing pattern (local loading) effects, and controlling CD movement at the etch step. Some obsolete-pattern photomasks were used in the kinetic study. The main advantages of using obsolete photomasks include reducing resist effects on Cr etch rate investigation, obtaining much more etch kinetics data, and significantly lowering process development costs normally incurred from lithography tool time and raw photomask material consumption.

The uniformity of critical dimensions is an important aspect of photomask fabrication, and the etch process can be improved by optimizing the geometry of the focus ring that surrounds the mask. Previous experimental results have shown that the focus ring can have a dramatic impact on the variability of critical dimensions on the photomask. Simulations were performed with the Hybrid Plasma Equipment Model (HPEM) software to examine the impact of different focus ring geometries on the plasma characteristics and improve the understanding of the experimental data.

In order to meet the needs of multiple customers with varying design specifications, merchant photomask suppliers need to provide photomasks for a wide range of design patterns. Some masks require etching less than 1% of the total mask film, while others require etching over 80% of the mask. Etching masks with these extremes in pattern loads can often require upgrading existing tool sets, particularly as the mask specifications become tighter. One alternative to upgrading tools is to develop new load-specific processes on existing lower-end tools, which requires a substantial amount of development work. Dry etching MoSi Embedded Attenuating Phase Shift Material using sulfur hexafluoride and helium under all etch loads presents challenges in the Unaxis Generation II mask etch platform. Etch processes developed for low load masks cannot always be used for high load masks due to problems in maintaining a stable process with good performance. In order to improve the etch performance for high MoSi loads (> 70% clear), a Gen II specific hardware design which can adversely affect uniformity at high loads was identified and eliminated as a dominant source of non-uniformity. A DOE studying total gas flow, He/SF6 ratio, pressure, ICP, and RIE power was then used to identify a stable process window for high MoSi loads. Another DOE studying the effects of pressure, ICP power, and RIE power on process uniformity was then carried out within the stable process window. Process conditions were identified which produced highly loaded 248nm and 193nm EAPSM masks with phase uniformity below 3°. Sidewall profiles were vertical for 193nm MoSi films but were slightly tapered for 248nm MoSi films, both with less than 5nm of CD bias.

The ITRS roadmap indicates that significant improvements in photomask dry etching will be necessary to achieve the design goals of 90nm and 65nm technology node masks. Although some existing dry etch systems are capable of R&D work on these masks, a new dry etch system is needed to achieve production worthy results. To this end, a new 4th generation mask etch system was designed and built by Unaxis USA, Inc. In early testing, the Unaxis Mask Etcher 4 has demonstrated significant improvements in CD uniformity and linearity compared to earlier systems. A designed experiment (DoE) was performed on this new system to more fully characterize its performance window. The results of these experiments are presented and compared to a standard process performed on a Unaxis Mask Etcher 3.

Accurate determination of endpoint is important for creating a repeatable process that maximizes sidewall profile angle and resist selectivity while maintaining a low etch bias. An Applied Materials EyeD (TM) spectrometer on the Tetra(TM) II photomask etch system is used to examine several endpoint methods to maximize flexibility and productivity. These methods include: slope changes to a single line, slope changes via a ratio of product and etchant species and slope changes of a linear combination of all slope changes. Endpoint identification is typically performed with a single spectral line. In addition, a method using neural networks, or principal component analysis (PCA) has also been created in order to fully optimize and characterize exact endpoint definition. Comparison between these methods will be discussed.

As the industry is targeting the sub-100nm nodes, the pressure on the data path and tapeout flow is growing. Design complexity and increased deployment of resolution enhancement techniques (RET) result in rapidly growing file sizes, which turns what used to be the relatively simple task of mask data preparation into a real bottleneck. Previous work indicated that the properties of the incoming layout - hierarchy, grid, aggressiveness of the RET solution have a major impact on the performance of fracturing and mask writing The tuning of OPC can reduce it's impact on subsequent fracturing. This study investigates the impact of OPC setup- various fragmentation parameters like fragment length, density, interaction radius and, various line-end correction schemes on the performance parameters for the mask data preparation and mask writing. Parameters like run-time, file size, shot count and small figures will be reported in dependence on the input layout preparation history. Approaches to optimize the integrated RET and MDP flow while maintaining manufacturability and the required CD control are introduced and evaluated.

Much has been said of the impact that advanced RET and OPC are having on the mask manufacturing process. However, increasingly, the limitations of mask manufacturing are impacting the quality and effectiveness of advanced RET and OPC, and they do this often in unpredictable ways. Detection of when these constraints limit the success of RET/OPC before the mask is made is critical to achieving cost and schedule control. An understanding of the conditions under which sub-optimal solutions result is also a key aspect of early RET/OPC recipe development, since this is the time when more options exist for satisfactory resolution. It is therefore a requirement in both production and development to analyze, in both a qualitative and quantitative manner, the effectiveness of the RET/OPC procedures using the actual layout, where it has been applied. The paper will present a methodology for accomplishing this analysis at the full chip level, and demonstrate the results.

Mask data preparation is a complicated process because many kinds of EB data files and jobdeck data files are used in mask manufacturers and EB data files continue to become bigger. Therefore we have started to develop new mask data format with efficient data compaction and unification among Variable-Shaped-Beam (VSB) EB mask writers. We have proposed the unified mask pattern data format for EB writers named "NEO"¹ in the 22nd annual BACUS symposium. We have proposed the unified mask layout format named "MALY" 2 and the high-compression data processing system3 for NEO in Photomask Japan 2003, too. Then we have decided to develop an enhanced mask data preparation system using NEO⁴ and MALY⁵. This system has common MDP functions not to be related to each EB writer. That would be effective in reducing mask data handling cost. In this paper we introduce the abstract of NEO and MALY and new mask data preparation system using NEO and MALY.

As designs grow more complex, process technologies become smaller, and geometry counts increase, the work required to achieve acceptable yeild becomes increasingly demanding and difficult. Underlying this state of affairs is the need to maximize yield without increasing manufacturing costs. This paper addresses techniques for increasing yield as well as suggestions for determining whether yield enhancement techniques are cost effective.

The chromeless phase lithography is a potential technology for low k1 optical image. Since the image quality is controlled by the phase interference, the phase error that results from mask processing becomes an issue. In the previous study, we have investigated the phase error effect and optimized the etching recipe by using the orthogonal DOE method. However, the 3D pattern profile is another critical factor, which affect the image intensity and needs to be clarified. In this paper, the through pitch L/S pattern with various profile angles were studied. Test patterns were measured, and verified by AFM, SEM, and metrology tools to get profile angles, phase values, and CD dimension. Simulation was used to predict the trend of process performance and analyze the impact on process control. The process windows for specific pattern profiles were also verified by wafer printing result. An optimized etching process and a set of spec recommendations for the CPL PSM was obtained.

The minimum gate pitch for the 65nm device node will push 193nm lithography toward k1 ~ 0.35 with NA = 0.85. Previous work has analyzed the challenges expected for this generation. However, in the simplest terms, optical lithography for the 65nm node will be difficult. Lithographers are, therefore, looking into high-transmission attenuated phase shift mask (high-T attPSM), where T > 14%, to improve process margins. The benefits of a high-t attPSM are substantial, but drawbacks like inspection difficulty, defect free blanks manufacture, and sidelobe printing may make the use of such masks impractical. One possible solution to this problem is to employ medium transmission (med-T) attPSM, such as T = 9%, to image critical levels of the 65nm node with 193nm lithography. Earlier work shows that the problems High-T attPSMs face are manageable for med-T attPSM. Sidelobe printing in particular will be treated in this work with simulation and experiment. A primary goal of this effort is to determine if the lithographic benefit of moving from industry-standard 6% attPSM to 9% attPSM is worth the risks associated with such a transition. This goal will be met through a direct comparison of experimental 0.75NA 193nm λ results for 6% versus 9% attPSM on gate, contact/via, and metal layers at 65nm generation target dimensions with leading edge resists. Additional information on the inspectability and reticle blank manufacture of % AttPSM will also be given to provide a cohesive analysis of the transition tradeoffs.

200-mm electron-beam projection lithography (EPL) masks were fabricated starting from stress-controlled silicon-on-insulator (SOI) substrates. The internal stress of the SOI layer is controlled to be ca. 10 MPa by B doping. The blank fabrication process has been established by the Bosch deep trench etch process. EB patterning was done on a JEOL JBX9000MVII with a positive-tone chemically amplified resist of 400-nm thickness. Resist image of 200-nm wide lines-and-spaces pattern was transferred to 2-um thick SOI layer by a shallow trench etching. A dual-mode critical dimension (CD)-SEM was implemented, and used for mask characterization. Preliminary results on uniformity of CD-shift in the dry etching and final CD were reported. 200-mm EPL masks with a gate layer of a system-on-chip device pattern were fabricated.

As we approach the 65nm node, the impact of the image imbalance phenomenon in phase shift mask lithography is proving to have a serious impact on the robustness of the phase shift mask solution. In this work we describe a new concept for the phase shift imbalance correction. The method is based on an interference concept that allows the manipulation of the image intensity by placing sub resolution features within the zero phase regions. Rigorous 3D simulations illustrate the reduction in the intensity of the 0 degree phase regions to match the intensity of the 180 degree phase intensity, effectively correcting for the image imbalance. We show that the phase shift mask low sigma illumination conditions reduce the risk of printing these sub-resolution binary features increasing the flexibility to vary the size of the feature based on circumstances to fine tune the correction locally.

Maskless lithography imaging based on SLM tilt mirror architecture requires illumination of light on a non-planar reflective topography. While the actual mirror dimensions can be much larger than the wavelength of light, the spacing between mirrors and the tilt range of interest are on the order of the wavelength. Thus, rigorous electromagnetic solution is required to capture light scattering effects due to the non-planar topography. We combine high NA imaging simulation with rigorous simulation of light scattering from the mirrors to study its effects on 65nm maskless lithography imaging. We vary mirror size, mirror tilt arrangemetn, feature type and illumination settings and compare the rigorous light scattering imagign resutls wtih standard imaging simulations using Kirchoff approximation. While electromagnetic scattering effects are present in the form of lateral standing waves and edge streamers in reflected light near-field intensity, they have negligible effects on SLM imaging for mirror sizes more than 1μm². The effects of mirror tilt arrangement on diffraction orders aer used to study the through-focus behavior of alternating rows arrangement used in the SIGMA maskwriters as well as alternative arrangements. The good imaging properties of the alternating rows arrangement used in the SIGMA maskwriters as well as alternative arrangements. The good imaging properties of the alternating rows arrangement are confirmed and a multipass overlay scheme giving further image fidelity improvements is suggested.

The purpose of this paper is to extend the Fourier optic imaging equations to the case of immersion lithography. Specifically, the paper will derive the equation describing the complex amplitude at the wafer plane for both the immersion case and the non immersion case. By comparing the two equations, a parameter transformation will be explicitly derived that allows the equation for the non immersion case to describe the immersion case. With these transformations, lithography simulators such as SOLID-C can be used to accurately model immersion lithography.

Optical lithography with 157-nm light is expected to bridge the gap between 193-nm technology and next-generation lithography. One important practical difficulty facing the implementation of 157-nm technology is gas absorption of 157-nm light. The exposure process for 193-nm technology is carried out in air. However, oxygen and water vapor attenuate 157-nm radiation. Alternatively, the exposure can be carried out in a nitrogen-purged environment. The purification of the volume trapped between the reticle and the hard pellicle is challenging because of the delicate pellicle geometry. In this paper, experimental results are presented that support the design and development of pellicle purge processes for 157-nm optical lithography. Specifically, a hard pellicle was installed in the Pressure Bulge Tool (at the UW Computational Mechanics Center) and experimental measurements of the pressure-induced pellicle distortion were obtained. The pressure loads imposed on the pellicle are representative of those expected during in-tool purge processes. Separate testing quantified the pellicle fracture stress and the flow characteristics of the pellicle/reticle geometry for a particular vent configuration (i.e., frame vent hole size and number, and filter system). These flow characteristics are important, as they ultimately dictate the pressure difference imposed on the pellicle during any purging process. These various experimental measurements, when taken together, facilitate the assessment of the feasibility and requirements associated with alternative pellicle purging strategies for 157-nm lithography.

This report is the second series of 157nm alternating phase shifting mask done at ISMT. In this report, we present a comprehensive study of balancing aerial image through various feature sizes and pitches. New resutls of resist imagse are analyzed from a 157-nm alternating PSM with a 0.85 NA lens. The mask is made by dual trench technique with a phase-etch of 115nm and an isotropic under-etch of 90nm based on optimized simulation results. With this dual trenched mask, the wafer printing images show tremendous improvement on 'line paring' phenomena. We also investigate some abnormal CD variation across line array observed during this study. The results from this work give an initial assessment of 157-nm capability of alternating PSM and 157-nm resist imaging quality.

Modified fused silica is a strong candidate material for photomask substrates in 157-nm lithography. Such a material must possess improved transmission and birefringence characteristics compared to conventional photomask substrates. Although there has been some success in producing modified silica using chemical vapor deposition, substantial improvements in quality and cost are desirable. A novel sol-gel based technique to inexpensively produce high quality 157-nm photomask substrates is being developed to address these issues. The complex relationships between glass properties and glass forming parameters were determined. Methods to improve the ultraviolet transmission at 157-nm were established, and modified silica without striae or optical defects were developed. Glasses produced using the sol-gel process displayed low birefringence and good homogeneity. With further improvement in transmission at 157 nm this glass may demonstrate technical and cost superiority to commercially available 157-nm photomask substrates.

The slow progress of the 157nm-F₂ laser exposure tool development results in broad adaptation of high numerical aperture (NA>0.8) 193nm-ArF lithography for the 65nm-node production solution. This decision, however, forces lithographers to increase dependency on very aggressive RET technologies. This in turn demands mask making capabilities the industry has never faced before such as 100nm (@4X on mask scale) size Sub Resolution Assist Features (SRAF). This report covers our early work on our mask making capability development for the 65nm-node process technology development cycle for production in 2005. Our report includes the 65nm node mask technology capability development status for mask CD and registration dimensions control, current inspection capability/issues and development efforts for critical layer masks with aggressive RET (especially of EAPSM with SRAF).

OPC (Optical Proximity Correction) improves the feature CD (critical dimension) uniformity and pattern fidelity in general. However, since model calibration only takes CD measurements at optimum exposure dose and best focus condition, the correction result may not be desirable at non-optimum conditions due to significant sub-resolution process distortion. Certain specific patterns are prone to bridging or pinching (we refer this type of location as hotspot in this paper) when process drifts a little from optimum condition. Simulation based full-chip verification became the method of choice for capturing hotspots on post-OPC layouts prior to mask tape-out to save development time and cost. In this paper, a complete simulation and analysis flow using SiVL was experimented to capture hotspots for a 100nm node process. Calibrated process model and multiple optical models with different focus/threshold conditions were applied for simulation. The method and effectiveness of filtering and analyzing fatal errors from output error database was discussed. The analysis results were then correlated to actual wafer printing. A good match between prediction and experiment was found.

In times of continuing aggressive shrinking of chip layouts a thorough understanding of the pattern transfer process from layout to silicon is indispensable. We analyzed the most prominent effects limiting the control of this process for a contact layer like process, printing 140nm features of variable length and different proximity using 248nm lithography. Deviations of the photo mask from the ideal layout, in particular mask off-target and corner rounding have been identified as clearly contributing to the printing behavior. In the next step, these deviations from ideal behavior have been incorporated into the optical proximity correction (OPC) modeling process. The degree of accuracy for describing experimental data by simulation, using an OPC model modified in that manner could be increased significantly. Further improvement in modeling the optical imaging process could be accomplished by taking into account lens aberrations of the exposure tool. This suggests a high potential to improve OPC by considering the effects mentioned, delivering a significant contribution to extending the application of OPC techniques beyond current limits.

As device technology shrinks beyond 0.13um, extensive resolution enhancement techniques such as PSM and OPC are employed in an attempt to gain usable photo process windows. Pattern fidelity on a mask measured in terms of corner rounding and line end shortening significantly influences the expected wafer performance. In this work, we report the effects of mask making parameters on the mask pattern fidelity and the resulting wafer pattern fidelity.

The complexity of current semiconductor technology due to shrinking feature sizes causes more and more engineering efforts and expenses to deliver the final product to customers. One of the largest expense in the entire budget is the reticle manufacturing. With the need to perform mask correction in order to account for optical proximity effects on the wafer level, the reticle expenses have become even more critical. For 0.13um technology one can not avoid optical proximity correction (OPC) procedure for modifying original designs to comply with design rules as required by Front End (FE) and Back End (BE) processes. Once an OPC model is generated one needs to confirm and verify the said model with additional test reticles for every critical layer of the technology. Such a verification procedure would include the most critical layers (two FE layers and four BE layers for the 0.13 technology node). This allows us to evaluate model performance under real production conditions encountered on customer designs. At LSI we have developed and verified the low volume reticle (LVR) approach for verification of different OPC models. The proposed approach allows performing die-to-die reticle defect inspection in addition to checking the printed image on the wafer. It helps finalizing litho and etch process parameters. Processing wafers with overlaying masks for two consecutive BE layer (via and metal2 masks) allowed us to evaluate robustness of OPC models for a wafer stack against both reticle and wafer induced misalignments.

In this paper, we will investigate methods for adapting model-based OPC tools to do layout correction (biasing) for mask makgin proximity effects. (Mask Proximity Correction). We will discuss three aspects of this problem: (1) typical models to use for mask making; (2) calibration of the model using mask measurement data; (3) one-pass versus two-pass flows for correction of mask making proximity effects.

In this paper, characteristics of an autofocus system on a grating with period smaller than the focus beam wavelength are investigated. The through-the-lens autofocus system, which has a visible light source of 670nm wavelength and light radiation mechanism for causing light to be obliquely incident on a sample surface, has been prepared for experiments. It is shown in experiments that the focusing error for a grating with 0.6-micrometer period is larger than 0.2 micrometer, and polarization of reflected light is changed from circular to elliptic. By performing RCWA simulations, the qualitative correspondence of theoretical expectations with experimental results is obtained. Based on the result of experiments and simulations, methods of reducing the focusing error are proposed. One of the methods is to use the polarization information to correct the focusing error. The method is evaluated experimentally and is shown to achieve autofocus accuracy of ± 0.1 micrometer.

Predictions have been made from exposure tool manufacturers as to the dense line lithographic capabilities of present and future tools. In particular, the predictions specify which dense line pitch will be achievable as a function of wavelength, mask type, NA and illumination conditions. Tremendous insight can be gained into these predictions by investigating the location of the first diffraction order with respect to the edge of the objective aperture for each case. Simple rules for dense line/spaces will be developed regarding scanner capabilities from the perspective of diffraction order location. These rules will then be used to predict line/space capabilities for hyper-NA systems. For reference, the diffraction order patterns of dense contacts and a representative DRAM brick wall structure will be presented. Also included in the paper will be a detailed derivation of the diffraction equations for dense lines and spaces for 180 degree alternating aperture phase shift masks. This derivation shows explicitly how the n=0 order is suppressed. It is the extension of previous work that derived the diffraction equations for a non phase shifted array of slits.

The extendibility of optical lithography using KrF and ArF exposure tools is still being investigated, even, being demanded strongly now, due to the unforeseen issues, high cost, and general difficulty of NGLs - including F₂ and immersion lithography. In spite of these challenges Moore's Law requires continued shrinks and the ITRS roadmap still keeps its aggressive timetable. In order to follow the ITRS roadmap, the resolution must keep improving by increasing the lens NA for optical exposure tools. However, the conventional limit of optical resolution (kpitch=0.5) is very close for the current technologies, perhaps limiting progress unless NGL becomes available quickly. Therefore we need to find a way to overcome this seemingly fundamental limit of optical resolution. In this paper, we propose two practical two-mask /double-exposure schemes for doubling resolution in future lithography. One method uses a Si-containing bi-layer resist, and the other method uses Applied Materials' APF (a removable hard mask). The basic ideas of both methods are similar: The first exposure forms 1:3 ratio L/S patterns in one resist/hard mask layer, then the second exposure images another 1:3 ratio L/S pattern in-between the two lines (or two spaces) formed by the first exposure. The combination of these two exposures can form, in theory, kpitch=0.25 patterns. In this paper, we will demonstrate 70nm L/S pattern (140nm pitch) or smaller by using a NA0.68 KrF Scanner and a strong-RET reticle, which corresponds to kpitch = 0.38 (k1=0.19). We will also investigate the critical alignment and CD control issues for these two-mask/dual-exposure schemes.

The impact of wafer and reticle anti-reflection coatings (ARCs) on the aerial image of ArF lithography scanners is measured using contrast curves and critical dimension (CD) analysis. The importance of a good ARC layer on the wafer appears to be greater than that of the reticle-ARC. In fact, for state-of-the-art lithography scanners, the influence of the reticle-ARC is practically undetectable. Numerical simulations are used to understand the relative contributions of the lens, the wafer and the reticle to the overall loss of contrast associated with non-optimized ARCs.

For logic design, Chrome-less Phase Shift Mask is one of the possible solutions for defining small geometry with low MEF (mask enhancement factor) for the 65nm node. There have been lots of dedicated studies on the PCO (Phase Chrome Off-axis) mask technology and several design approaches have been proposed including grating background, chrome patches (or chrome shield) for applying PCO on line/space and contact pattern. In this paper, we studied the feasibility of grating design for line and contact pattern. The design of the grating pattern was provided from the EM simulation software (TEMPEST) and the aerial image simulation software. AIMS measurements with high NA annular illumination were done. Resist images were taken on designed pattern in different focus. Simulations, AIMS are compared to verify the consistency of the process with wafer printed performance.

A binary mask with a 2D contact array pattern was simulated for the purpose of determining optimum amounts of bias for various pitches. The objective was to center the elliptical process windows for a given set of pitches about a nominal dose. The nominal dose was set by the center of the process window for smallest pitch case with a fixed bias of 15nm. Calculating the optimal bias values required calculation of process windows, which in turn required the calculation of CD through defocus and dose (or threhsold). CDs for the procss windows were calculated in three ways: 1. From aerial image (simplest, fastest, no 3D resist simulation required). 2. From resist image (fast, no 3D resist simulation required). 3. From resist profile (slow, 3D resist simulation required). Straightforward, brute-force "batching" is employed in the first two methods. To minimize the number of 3D resist simulations in the 3rd method, special "scripted" algorithms were employed. The algorithm run times for each of the three methods were compared. The three methods are observe to yield different values of bias. It is shown that, under the assumption that the resist model is accurate, the resulting biases obtained from the faster (1st and 2nd) methods are incorrect, that relying on CD measurements from aerial or resist images is insufficient for the task at hand, and that 3D resist simulation is required.

Resist heating has been known to be one of the main contributors to local CD variation in mask patterning using variable shape e-beam tools. Increasingly complex mask patterns require increased number of shapes which drives the need for higher electron beam current densities to maintain reasonable write times. As beam current density is increased, CD error resulting from resist heating may become a dominating contributor to local CD variations. In this experimental study, the IBM EL4+ mask writer with high voltage and high current density has been used to quantitatively investigate the effect of resist heating on the local CD uniformity. ZEP 7000 and several chemically amplified resists have been evaluated under various exposure conditions (single-pass, multi-pass, variable spot size) and pattern densities. Patterns were designed specifically to allow easy measurement of local CD variations with write strategies designed to maximize the effect of resist heating. Local CD variations as high as 15 nm in 18.75 × 18.75 μm sub-field size have been observed for ZEP 7000 in a single-pass writing with full 1000 nm spots at 50% pattern density. This number can be reduced by increasing the number of passes or by decreasing the maximum spot size. The local CD variation has been reduced to as low as 2 nm for ZEP 7000 for the same pattern under modified exposure conditions. The effectiveness of various writing strategies is discussed as well as their possible deficiencies. Minimal or no resist heating effects have been observed for the chemically amplified resists studied. The results suggest that the resist heating effect can be well controlled by careful selection of the resist/process system and/or writing strategy and that resist heating does not have to pose a problem for high throughput e-beam mask making that requires high voltage and high current densities.

When e-beam lithography is applied for second level imaging of Alternating Phase Shift Masks charging effects on the cleared chrome absorber induces placement, overlay and pattern distortion of the second layer. The water soluble conductive to coat Showa Denko ESPACER 300Z has been evaluated in combination with the chemically amplified resist FEP171 for a charging eliminating patterning solution. Application of ESPACER on top of FEP171 kept the resist performance unchanged. Sensitivity, profile, resolution, CD-uniformity and post exposure delay of FEP171 have been investigated and no influence of ESPACER was detected. The bilayer system ESPACER and FEP171 was used for the second patterning of an altPSM test design and the technology performance was characterized. No difference has been figured out between placement of the second level and placement on a non-structured chrome layer. The achieved overlay accuracy proves the ESPACER/FEP171 combination as a promising approach for future altPSM manufacturing.

Accurate contact-hole imaging depends on the relative size of the contact hole to be patterned and the resolution of the stepper. The hardbake process includes desirable thermal reflow of the resist contact-hole arrays; this effect is driven by the temperature dependence of the polymer-based resist that is densified on the silicon substrate. Thermal reflow is completely independent of current and near-term lithographic printing tools. Resist reflow is a thermomechanical phenomenon dominated by the polymer after development, during which thermal reactions of the polymer produce permanent mechanical deformations of the contact holes. Resist behavior can effectively be classified into solid and viscous, below and above the characteristic glass transition temperature, respectively. The basic states are characterized by changes in the stress states and the phases depending on the thermal behavior of the resist material. The thermal transitions of the resist in the process are strongly influenced by the temperature-dependent mechanical properties, i.e., the modulus, the yield stress, and the coefficient of thermal expansion. Other influences include the surface tension and the bake cycle parameters. This analysis assumes conventionally generated contact holes in the resist, followed by thermal cycling until the thermal reflow produces reduced size contact holes of the desired dimensions. Finite element models were utilized to identify the principal physical parameters influencing resist thermal reflow.

In this work, we analyzed resist CD uniformity on 6025 substrates in terms of resist PEB sensitivity, PEB time, temperature variation during ramp up, hotplate vacuum and the application of a chill plate. We found that the resist PEB sensitivity, PEB time and the final temperature were the most important factors. By selecting low PEB sensitive resist and optimizing the bake conditions, the CD uniformity was greatly improved. The temperature profile of the hotplate configuration used for this study will be discussed along with the CD uniformity obtained using this hotplate under various conditions.

The control of global critical dimension uniformity (GCDU) across the entire mask becomes an important factor for the high-end masks quality. Three major proceses induce GCDU error before after-developing inspection (ADI) including the E-Beam writing, baking, and developing processes. Due to the charging effect, the fogging effect, the vacuum effect and other not-well-known effects, the E-Beam writing process suffers from some consistent GCDU errors. Specifically, the chemical amplified resist (CAR) induces the GCDU error from improper baking. This phenomenon becomes worse with negative CARs. The developing process is also a source of the GCDU error usually appears radially. This paper reports the results of the study of the impact of the global CD uniformity on mask to wafer images. It also proposes solutions to achieve better masks.

In a joint-development, Rohwedder and Osmic have designed and built a low-defect dual-ion beam reactive-sputtering tool. The tool has been specifically targeted for developing low-defect lithography mask photoblank coatings intended as DUV absorbers and phase-shifting films. The Osmic/Rohwedder collaboration will continue into NGL - the present tool also serves as an R&D platform for EUVL mask blanks. The deposition tool and robotic substrate handler have been integrated and delivered to Osmic in the 2nd quarter of 2003. In this paper, we present initial capability for production of thin-film lithography coatings, including spectrophotometric performance, defect levels and film uniformity. Future reports will share results from more in-depth process development and optimization.

The interface between the customer and the mask shop is one of the most error prone stages of the mask production process. Errors introduced at this stage can often be very hard to detect at subsequent stages of the manufacturing process. To assist their customers, Compugraphics have developed an automated system, called EMPOF, to allow customers to specify their orders using the Internet. The system was designed as a replacement to the existing Mask Production Order Forms that were being used by Compugraphics, and was deliberately kept simple to encourage the use of the system by a large number of smaller customers, rather than a complementary solution based on the SEMI P10 format that is also available. The paper reviews the structure and user interfaces of the software; showing how a customer is presented with default forms that can be customized to their processes, the default forms can also be partially completed where certain aspects of the orders do not change. A comprehensive on-line help facility is also included within the software. Orders that are submitted with the EMPOF system are then automatically prepared for manufacture using the DO_EMPOF software. This strategy minimizes the need for human interaction resulting in a robust process. Future plans to extend the EMPOF system by integrating it with the SEMI P10 and 2MPOFDB applications are described.

High-speed production of semiconductor devices demands in-line wafer metrology on a minimum number of sample points. If this data does not represent the average chip feature size, then an in-line monitor may indicate that a wafer is right on target. However, at end-of-line testing, the electrical parameters, incorporating all features within the chip, may be found shifted away from target. This paper presents a solution which increases wafer critical dimension targeting efficiency while notably relaxing the traditional mean-to-target reticle specification. By embedding ART (Average Representative Targeting) Structures into the reticle scribe, Reticle Engineering at LSI Logic leverage off the ability to adjust wafer exposure dose to compensate for off target reticle CDs. The novel targeting structure described in this paper assures average wafer CDs within 2.5 nm of target while effectively doubling the acceptable range for a standard mean to target reticle specification.

Although the first version of the SEMI P10 “Specification of Data Structures for Photomask Orders” was introduced over ten years ago and is supported by all of the major photomask vendors, only a few chip suppliers currently take advantage of this automated order entry infrastructure. This is unfortunate because placing a photomask order by transmitting a P10 file reduces errors and improves throughput time. The hierarchical structure and comprehensive support for fracturing software, writing tools, defect inspection systems, and metrology equipment, allow tapeout groups to define very complex photomask orders in a P10 file. Mix and match reticle sets utilizing multiple steppers, multi-layer reticles, process development reticles with dozens of pattern files per layer, and phase shift reticles can all be defined in a P10 file. However, the extensive capabilities and the scalability of SEMI P10 come at a price. The specification is complicated -- the latest release is over 40 pages in length and defines over 500 record types. Before a software system that automates P10 file writing can be successfully implemented, the P10 spec must be studied from a number of perspectives. These include the user interface requirements, present and future photomask needs, vendor preferences for P10 file structure and content, and process file management. This paper will present a brief overview of the P10 structure and capabilities, describe how Agilent Technologies, Photomask Technology Center (PTC) made the decision to upgrade its reticle order management software with RetBuilder from CenterLink.

As the design rule is decreased rapidly, tighter critical dimension (CD) control is highly requested in photomask process