This PDF file contains the front matter associated with SPIE Proceedings Volume 6518, including the Title Page, Copyright information, Table of Contents, Introduction (if any), and the Conference Committee listing.

Double patterning has emerged as a likely lithography technology to bridge the gap between water-based ArF immersion lithography and EUV. Water immersion, single exposure lithography is limited to about 40nm half pitch with NA 1.35. Extension of immersion with high index fluids and glasses is theoretically possible, but faces severe challenges in technology, economics, and timing. In order to extend water immersion lithography further, much attention is given to reducing effective k₁ to less than 0.25 using double patterning. This paper explores the unique challenges IC metrology faces to enable double patterning, first in development, then in production.

Despite the increasing use of advanced imaging methods to pattern chip features, process windows continue to shrink with decreasing critical dimensions. Controlling the manufacturing process within these shrinking windows requires monitor structures designed to maximize both sensitivity and robustness. In particular, monitor structures must exhibit a large, measurable response to dose and focus changes over the entire range of the critical features process window. Any process variations present fundamental challenges to the effectiveness of OPC methods, since the shape compensation assumes a repeatable process. One particular process parameter which is under increasing scrutiny is focus blur, e.g. from finite laser bandwidth, which can cause such OPC instability, and thereby damage pattern fidelity. We introduce a new type of test target called the Process Monitor Grating (PMG) which is designed for extreme sensitivity to process variation. The PMG design principle is to use assist features to zero out higher diffraction orders. We show via simulation and experiment that such structures are indeed very sensitive to process variation. In addition, PMG targets have other desirable attributes such as mask manufacturability, robustness to pattern collapse, and compatibility with standard CD metrology methods such as scatterometry. PMG targets are applicable to the accurate determination of dose and focus deviations, and in combination with an isofocal grating target, allow the accurate determination of focus blur. The methods shown in this paper are broadly applicable to the characterization of process deviations using test wafers or to the control of product using kerf structures.

In this paper, results and analysis are presented from Advanced Micro Devices' (AMD) efforts at calculating lithography dose and focus parameters using scatterometry metrology and semi-physical CD models. The system takes advantage of the accurate and precise top and bottom CD data produced by scatterometry to differentiate dose and focus variation. To build the lithography process model, scatterometry data is generated for each field of a focus-exposure matrix (FEM) wafer, and the resulting top and bottom CD data is used to fit the parameters of series expansions relating CD to dose and focus. When new CD data is generated, the models can be inverted to solve for dose and focus independently. Our methodology employs a flexible modeling and inversion approach in an attempt to make the technique applicable to any production film stack and any line spacing regime. The quality of the inversion results are highly correlated to the degree of focus observability present in the system. Our results will show how a series of litho process with varied film stacks and line/space ratios respond to this technique, and we will report some best practices for a variety of use cases ranging from equipment characterization to focus monitoring on product.

Monitoring of the focus performance is recognized to be an important part of a periodic scanner health check, but can one simply apply all techniques that have been used for dry scanners to immersion scanners? And if so how do such techniques compare to scanner self-metrology tests that are used to set up the tool? In this paper we look at one specific off-line focus characterization technique, Back Side Chrome (BSC), which we then try to match with results obtained from two self-metrology focus tests, available on the scanner chosen for this work. The latter tests are also used to set up the immersion scanner. We point out a few concerns, discuss their effect and indicate that for each generation of immersion tool one should redo the entire exercise.

This paper discusses the use of scatterometry for scanner focus control in hyper-NA lithography. A variety of techniques based on phase shift technology have been traditionally used to monitor scanner focus. Recently scatterometry has offered significant promise as an alternate technique to monitor both focus and dose. In this study, we make careful comparisons of a Scatterometry-based Focus-Dose Monitoring (SFDM) technique to Phase-grating Focus Monitoring (PGFM). We discuss the operating principles of these techniques and compare the sensitivity of SFDM to PGFM. In addition, the variation observed in characterizing intra-field and across-wafer behavior of a hyper-NA immersion scanner is described when using these different techniques.

We have proposed a new inspection method of in-line focus and dose controls for semiconductor volume production. We referred to this method as the focus and dose line navigator (FDLN). Using FDLN, the deviations from the optimum focus and exposure dose can be obtained by measuring the topography of the resist pattern on a process wafer that was made under a single-exposure condition. Generally speaking, FDLN belongs to the technology of solving the inverse problem as scatterometry. The FDLN sequence involves following the two steps. Step 1:creating a focus exposure matrix (FEM) using a test wafer for building the model as supervised data. The model means the relational equation between the multi measurement results of resist patterns ( e.g. Critical dimension (CD), height, sidewall angle) and FEM's exposure conditions. Step 2: measuring the resist patterns on a production wafers and feeding the measurement data into the library to extrapolate focus and dose. To estimate the accuracy of FDLN, we performed some experiments. We developed a FEM with an ArF lithography tool and measured the resist patterns of the FEM wafer with the advanced CD-SEM (Critical Dimension-Scanning Electron Microscope). Using the MPPC (Multiple Parameters Profile Characterization) data from the advanced CD-SEM, we obtained the following results. Focus: 21.5 nm (4.1 nm) and Dose: 1.5% (2.0 nm). The numerical value in a parenthesis shows the value of the estimated accuracy with changing CD. We also show other experimental results in this paper and the application of the focus and dose controls for semiconductor exposure tool.

In this paper, we seek a systematic strategy for creation of a wafer sampling plan and to determine the relationship between this plan and the OPC model accuracy. We start our study with the traditional error components analysis of wafer data. From this, we introduce our methodology of calculating the effective sample size based on each pattern and its error components. With all the error components separated, the confidence of the estimated mean can be calculated and, hence, an error bar can be added to each mean of the wafer data. This error bar is then used to determine which patterns are over-fitting and which patterns require an improved fit. We will present a method of providing an optimized and economical solution for wafer sampling. With this calculated error bar, the ultimate metric for OPC model accuracy will also be discussed.

In this paper, we study the feasibility of using a new system to set up offline critical dimension scanning electron microscope (CDSEM) recipes for both litho and etch processes monitoring in a foundry environment before first silicon. We will automatically create CDSEM measurement recipes based on CAD design data (2) and litho illumination information. The main advantages of having recipes setup done through this method as compared to performing recipe creation on the CDSEM tool itself are the reduction in CD-SEM tool usage and more importantly, the availability of the recipes before the first wafer is being processed in lithography resulting in a faster of cycle time for new devices. To facilitate our objective, a new feature was implemented in the design to provide a universal global alignment (GA) feature under both optical and SEM view. The global alignment serves two functions: to minimize device-to-device and layer-to-layer optical variation. It synchronizes design (CAD) and wafer coordinate systems. With this universal alignment feature available across all production layers of interest, we can fully automate recipe creation process from design to production.

Model based optical proximity correction (OPC) today has become a necessity in advanced lithography for 65nm and 45nm design rules in order to achieve production-worthy pattern fidelity. The typical practice is to use a limited set of test structures to calibrate and determine the OPC model parameters. The guide for the selection of test structures for OPC model calibration has been mainly relied on experience and physical intuition. To date, there is no known quantification methodology to ensure that the calibrated model from a limited set of test structures can reliably "cover" a full-chip OPC application without any ambiguity under a known set of design rule constraints. Doubts from this ambiguity demand an extra design for manufacturing (DFM) verification step in addition to the already lengthy OPC application process. This is since semiconductor manufacturing requires that the post-OPC mask data contains no errors, or at least no catastrophic errors induced by OPC treatment, e.g., bridging or short. However, such DFM verification tools are again based on a perilous assumption that either one can use the same or yet another "calibrated" model from a limited set of test structures to check the OPC treated full-chip data for all possible trouble spots. In reality, a "calibrated" model may never be able to apply adequately to those of random two-dimensional (2-D) pattern structures on a full-chip that are lithographically unrelated to the limited set of test structures used for the model calibration. To ensure a more comprehensive coverage of the OPC model, we need a methodology that can quantify generalized 2-D test structures suitable for model calibration. In this paper, we propose a method to quantify generalized, 2-D patterns by representing them in "imaging signal space". The method that translates geometrical design rules into the boundary in "imaging signal space" is elaborated. We propose several critical quantities to characterize OPC model on a quantitative foundation to assess model from a statistical point of view.

One of the challenges associated with shrinking design dimensions is finding photomask inspection settings which achieve sufficient defect detection capabilities while supporting aggressive Optical Proximity Correction (OPC). The most recent technology nodes require very aggressive and advanced Resolution Enhancement Techniques (RETs) which involve printing small features that are challenging for mask inspection tools. We examine the problems associated with constraining Models-Based OPC with mask inspection driven rules. We give examples of a 45nm technology node contact layer design which will receive sub-optimal OPC treatment due to mask inspection constraints. We then take the mask defect specification typically used for this mask layer, and use Monte Carlo simulation methods to place minimum sized simulated defects in various locations in close proximity to these sensitive layouts. Simulations of the optimal OPC are compared to optimal OPC with defects, and to the sub-optimal constrained OPC. Using knowledge about the frequency of small defects on masks, one can compare the risks associated with small mask defects to the risks associated with sub-optimal OPC. This exercise demonstrates that there are some instances where mask rules based on inspection capabilities and defect sensitivity alone can be problematic, and that OPC requirements need to be taken into account when choosing a defect specification and an inspection strategy. We conclude by proposing a strategy for balancing these requirements in a practical manner.

For the 90nm node and beyond, smaller Critical Dimension(CD) control budget is required and the ways to control good CD uniformity are needed. Moreover Optical Proximity Correction(OPC) for the sub-90nm node demands more accurate wafer CD data in order to improve accuracy of OPC model. Scanning Electron Microscope (SEM) is the typical method for measuring CD until ArF process. However SEM can give serious attack such as shrinkage of Photo Resist(PR) by burning of weak chemical structure of ArF PR due to high energy electron beam. In fact about 5nm CD narrowing occur when we measure CD by using CD-SEM in ArF photo process. Optical CD Metrology(OCD) and Atomic Force Microscopy(AFM) has been considered to the method for measuring CD without attack of organic materials. Also the OCD and AFM measurement system have the merits of speed, easiness and accurate data. For model-based OPC, the model is generated using CD data of test patterns transferred onto the wafer. In this study we discuss to generate accurate OPC model using OCD and AFM measurement system.

As design rules shrink, there is an unavoidable increase in the complexity of OPC/RET schemes required to enable design printability. These complex OPC/RET schemes have been facilitating unprecedented yield at k₁ factors previously deemed "unmanufacturable", but they increase the mask complexity and production cost, and can introduce yield-detracting errors. The most common errors are found in OPC design itself, and in the resulting patterning robustness across the process window. Two factors in the OPC design process that contribute to these errors are a) that 2D structures used in the design are not sufficiently well-represented in the OPC model calibration test pattern suite, and b) that the OPC model calibration is done only at the nominal process settings and not across the entire focus-exposure window. This work compares two alternative methods for calibrating OPC models. The first method uses a traditional industry flow for making CD measurements on standard calibration target structures. The second method uses 2D contour profiles extracted automatically by the CD-SEM over varying focus and exposure conditions. OPC models were developed for aggressive quadrupole illumination conditions (k₁=0.35) used in 65nm- and 45nm-node logic gate patterning. Model accuracy improvement using 2D contours for calibration through the process window is demonstrated. Additionally this work addresses the issues of automating the contour extraction and calibration process, reducing the data collection burden with improved calibration cycle time.

As a consequence of the shrinking sizes of the integrated circuit structures, the overlay budget shrinks as well. Overlay is traditionally measured with relatively large test structures which are located in the scribe line of the exposure field, in the four corners. Although the performance of the overlay metrology tools has improved significantly over time it is questionable if this traditional method of overlay control will be sufficient for future technology nodes. For advanced lithography techniques like double exposure or double patterning, in-die overlay is critical and it is important to know how much of the total overlay budget is consumed by in-die components. We reported earlier that small overlay targets were included directly inside die areas and good performance was achieved. This new methodology enables a wide range of investigations. This provides insight into processes which were less important in the past or not accessible for metrology. The present work provides actual data from productive designs, instead of estimates, illustrating the differences between the scribe line and in-die registration and overlay. The influence of the pellicle on pattern placement on mask and wafer overlay is studied. Furthermore the registration overlay error of the reticles is correlated to wafer overlay residuals. The influence of scanner-induced distortions (tool to tool differences) on in-die overlay is shown. Finally, the individual contributors to in-die-overlay are discussed in the context of other overlay contributors. It is proposed to use in-die overlay and registration results to derive guidelines for future overlay and registration specifications. It will be shown that new overlay correction schemes which take advantage of the additional in-die overlay information need to be considered for production.

Patterns of lines and trenches with nominal linewidths of 50 nm have been proposed for use as an overlay target appropriate for placement inside the patterned wafer die. The National Institute of Standards and Technology (NIST) Scatterfield Targets feature groupings of eight lines and/or trenches which are not resolvable using visible-wavelength bright-field microscopy. Such repetitive patterns yield zero-order images superimposed by interference effects from these finite gratings. Zero-order imaging is defined as the collection of specular reflection from periodic structures without the collection of any possible diffracted beams. As our lines and trenches are formed in different photolithographic steps, the overlay offset can be derived from the relative displacement of these zero-order responses. Modeling this phenomenon will require a thorough characterization of the transmission of light through all points in the optical path as a function of position, angle, and polarization. Linear polarization parallel and perpendicular to these lines and trenches is investigated as a possible enhancer of overlay offset measurement repeatability. In our particular case, nominally unpolarized light proved most repeatable.

Improved overlay capability and sampling to control advanced lithography has accelerated the need for compact, multilayer/ mask/field/mark overlay metrology. The Blossom approach minimizes the size of the overlay marks associated with each layer while maximizing the density of marks within the overlay metrology tool's field of view (FOV). Here we describe our progress implementing this approach in 45nm manufacturing.

65-55nm Logic-Devices require high performance of not only the resolution, of but also the overlay accuracy (Mean+3sigmas < 20-30nm). Thus, here, overlay performance of several layers in our advanced devices is investigated with using Immersion-exposure-tool. We used the new alignment system called SMASH^TM which has the phase grating alignment sensor newly installed in our immersion-exposure-tool (XT1400Ei). SMASH supports flexible mark design in terms of size and pitch of the grating so that it can comply for our design requirement. SMASH has much smaller alignment beam size of ~ 40um for it. New mark design for our 65-55nm process will be investigated so as to obtain higher alignment accuracy than that of current marks. The alignment performance becomes more accurate proportionally to data density of the mark and it depends on the diffraction angle and efficiency from the mark. Thus, to obtain acceptable alignment accuracy with smaller mark, it should be designed such as diffraction efficiency is maximized within the required boundary condition in the pitch [diffraction angle] and segmentation of the mark. In this paper, several new marks are designed and evaluated. The evaluation shows that comparable performance could be obtained in the new design mark as in ASML's conventional marks. Finally, we select one from the new smaller marks and apply it to our 65-55nm process, especially, to the five process modules (Gate-to-Active, Contact-to-Gate, Metal1-to-Contact, Via1-to-Metal1, Metal2-to-Via1), and performance within 20nm (Mean+3sigmas) are typically obtained. The overlay accuracy needed for our 65-55nm Logic-Devices is successfully achieved with immersion-exposure-tool. SMASH* (SMart Alignment Sensor Hybrid): the name of alignment system using with phase grating alignment sensor.

In a previous publication, we introduced Blossom, a multi-layer overlay mark (Ausschnitt, et al. 2006, [1]). Through further testing carried out since that publication, Blossom has been shown to meet the requirements on current design rules (Ausschnitt, et al. 2007, [2]), while giving some unique benefits. However, as future design rules shrink, efforts must be made now to ensure the extensibility of the Blossom technology. Previous work has shown that the precision component of Total Measurement Uncertainty (TMU) can be reduced by using extra redundancy in the target design, to achieve performance beyond that of a conventional box-in-box measurement. However, improvements that single contributor to TMU would not be sufficient for future design rules; therefore we have also to consider the Tool Induced Shift (TIS) variability and tool to tool matching contributions to TMU. In this paper, we introduce a calibration artifact, based on the Blossom technology. The calibration artifact is both compact, and produced by standard lithography process, so it can be placed in a production scribe line if required, reducing the need for special sets of calibration wafers compared to other possible calibration methodologies. Calibration is currently with respect to the exposure tool / process / mask, which is arguably more pertinent to good yield, and less expensive, than calibration to an external standard; externally calibrated artifacts would be straightforward to manufacture if needed. By using this artifact, we can map out remaining optical distortions within an overlay tool, to a precision significantly better than the operational tool precision, in a way that directly relates to overlay performance. The effect of process-induced mark uncertainties on calibration can be reduced by performing measurements on a large number of targets; by taking multiple measurements of each target we can also use the artifact to evaluate the current levels of process induced mark uncertainty. The former result leads to an improvement method for TIS and matching capability. We describe the artifact and its usage, and present results from a group of operational overlay tools. We show how the use of this information also provides further insight into the layout optimizations discussed previously (Binns et al. 2006 [3]). It provides the current limits of measurement precision and mark fidelity with respect to target redundancy, enabling us to use a predictive cost-benefit term in the optimization. Finally, examining the bulk behaviour of a fleet of overlay tools, allows us to examine how future mark layouts can also contribute to minimizing TMU rather than just precision.

As Moore's Law drives CD smaller and smaller, overlay budget is shrinking rapidly. Furthermore, the cost of advanced lithography tools prohibits usage of latest and greatest scanners on non-critical layers, resulting in different layers being exposed with different tools; a practice commonly known as 'mix and match.' Since each tool has its unique signature, mix and match becomes the source of high order overlay errors. Scanner alignment performance can be degraded by a factor of 2 in mix and match, compared to single tool overlay operation. In a production environment where scanners from different vendors are mixed, errors will be even more significant. Mix and match may also be applied to a single scanner when multiple illumination modes are used to expose critical levels. This is because different illuminations will have different impact to scanner aberration fingerprint. The semiconductor technology roadmap has reached a point where such errors are no longer negligible. Mix and match overlay errors consist of scanner stage grid component, scanner field distortion component, and process induced wafer distortion. Scanner components are somewhat systematic, so they can be characterized on non product wafers using a dedicated reticle. Since these components are known to drift over time it becomes necessary to monitor them periodically, per scanner, per illumination. In this paper, we outline a methodology for automating characterization of mix and match errors, and a control system for real-time correction.

Measurements of critical dimensions (CDs), roughness, and other dimensional aspects of semiconductor electronics products rely upon secondary electron (SE) images in the scanning electron microscope (SEM). These images are subject to artifacts at the nanometer size scale that is relevant for many of these measurements. The most accurate measurements for this reason depend upon models of the probe-sample interaction in order to perform corrections. MONSEL, a Monte Carlo simulator intended primarily for CD metrology, has been providing the necessary modeling. However, restrictions on the permitted sample shapes are increasingly constraining as the industry's measurement needs evolve towards inherently 3-dimensional structures. We report here results of a collaborative project, in which the MONSEL physics has been combined with the 3D capabilities of NISTMonte, another NIST Monte Carlo simulator that was previously used principally to model higher energy electrons and x-rays. Results from the new simulator agree very closely with the original MONSEL for samples within the repertoire of both codes. The new code's predicted SE yield variation with angle of incidence agrees well with preexisting measurements for light, medium, and heavy elements. Capabilities of the new code are demonstrated on a model of a FinFET transistor.

In recent year, CD metrology is required not only precision but also accuracy for more accurate CD control. CD bias between CD-SEM and a reference tool is the most important factor for more accurate CD measurement. CD bias varies by many CD-SEM and pattern condition. Then, CD bias variation caused by CD-SEM should be evaluated in detail. However, it is difficult to estimate these factors dependence on CD bias variation experimentally. Then, we develop an electron beam simulator with charging effects. We evaluated the mechanism of CD bias variation using electron beam simulator and CD-SEM data. As the results, CD bias variation is caused by changing of secondary electron signal which depends on space width. There are several different points between the experimental results and the simulation results in grayscale line profiles. Simulation data can be more similar to experimental data with charging effects and the actual experimental conditions. Simulation has enough capability to estimate CD bias variation with the simple structure and non-charging calculation. And mechanism of space width dependence on CD bias can be analyzed by using electron beam simulator.

In the Nantero NRAM process, a carbon nanotube film is patterned using conventional photolithography and etch techniques. CD SEM metrology of the printed resist image is straightforward. However, challenges arise when SEM inspecting an etched nanotube pattern. Under conventional SEM inspection, a nanotube pattern is nearly invisible. In order to facilitate nanotube pattern characterization, metrology structures have been developed which use passive voltage contrast to cause electron emission from the nanotube pattern and associated conducting structures. These enable manual inspection of the nanotubes, along with automated pattern recognition and automated CD measurement. The voltage contrast is achieved by connecting the nanotubes to a remote "charge-sink" outside the image field consisting of a large rectangle of metal. The voltage contrast occurs with no extra electrical connection to the wafer, and without special SEM components or beam adjustment. The metrology structures are used in two general ways: 1. Nanotubes are clearly imaged, enabling inspection, CD measurement, coat-quality characterization, etc. 2. Indicator structures in associated process layers light up when contacted by nanotubes, enabling measurements of line-end shortening; etch bias; overlay; etc. Various structures have been developed: 1. CD cells for manual and automated CD measurement. 2. Vernier structures for characterization of overlay, line-end shortening and etch-bias. 3. Serpentine structures for characterization of nanotube coat quality using conduction length.

CD-SEMs fleet matching is a widely discussed subject and various approaches and procedures to determine it were described in the literature. The different approaches for matching are all based on statistical treatment of regular CD measurements that are performed on dedicated test structures. The test structures are a limited finite set of features, thus the matching results should be treated as valid only for the specific defined set of test features. The credibility of the matching should be in question for different layers and specifically production layers. Since matching is crucial for reliable process monitoring by a fleet of CD-SEMs, the current matching approaches (such as TMU) must be extended so that the matching will be only tool dependent and reproducible on all layers regardless their specific material or topographic characteristics. In this work the term "Physical Matching" is introduced and a new matching procedure based on physical parameters is described. This approach extends the conventional matching methods to enable significant improvement of the matching between CD-SEM tools in production environment. To study and demonstrate the physical matching, we focus on the limited parameters set - the image brightness and Signal/Noise ratio(SNR). We test the sensitivity of CD measurements to changes in these parameters both on different test layers - Etch and Litho. We show that sensitivity of CD based measurements is low and reasonable change of the image brightness or SNR has small effect. The advantage of the physical matching approach for case study is demonstrated. The improved matching procedures are based on new targets that are used to measure the above image parameters directly. This way it is possible to characterize correctly the physical state of the measurement tool and guarantee the same image characteristics which in turn guarantee improved matching on all layers. In the framework of the proposed matching approach a proper determination of the minimal set of physical parameters that is needed to guarantee CD-SEM tools stability and matching should be included.

Since the semiconductor manufacturing process has become more and more complicated due to the introduction of either new materials or new structures, detecting the source of a defect has become dramatically difficult. Automatic Defect Classification (ADC) is one of the most effective ways for identifying the source of a defect. However, the current ADC algorithm is insufficient in identifying a defect source, because its classification results are quite simple. Since the classification is determined by the shape or size of the defect, it is difficult to figure out the process or processing tool in which the defects are generated. To solve this problem, we propose a new ADC algorithm and have already applied it to a high-volume System-on-Chip (SoC) production line to verify its efficiency. We confirmed with the classification results that the new ADC algorithm is almost as accurate as manually classifying them, but with the reduction of the time required for identifying the defect source.

With the introduction of sub-100nm design rules, and especially 193nm photolithography, the development of new monitoring strategies is becoming increasingly important and necessary as new materials, new tools and new process challenges are introduced. Micro after-develop inspection (μADI) is a big step forward for photolithography defect monitoring as well as for integrated process learning. Resist quality and handling are essential for the whole process. The new 193nm resists exhibit an inherent defectivity, which is solely attributable to the quality of the resist. This defectivity comes from very small resist inhomogeneity, and leads to tiny bridging and stringer defects which can affect yield critically. Additionally, the entire lithography process (handling and scanning) is more critical, as process windows are decreasing to levels of common positioning accuracy and layer thicknesses. On the one hand, increased inspection sensitivity is needed to control the resist quality more tightly. With straightforward improvements to inspection technology, these sensitivity requirements can be met on test wafers, mainly because of the wafers' simplified structures and the absence of noise sources. However, on the other hand, there is a demand for a monitoring strategy which uses product wafers to enable the understanding of the interaction of material, structure, topography and shrinking process window. Test wafer monitoring is able to provide only an isolated snap shot of a specific work-step without further interaction. An integrated monitoring strategy of product wafers requires more advanced and innovative inspection technologies - providing both enhanced sensitivity and superior noise suppression - as lithography layers can show a lot of non-yield relevant etch mask defects that are very hard to suppress with common inspection techniques. This work introduces a novel after-lithography monitoring strategy based on a darkfield defect inspection technique on product wafers. Wafers can be scanned after development with superior noise suppression at resolutions approximating traditional brightfield inspection capabilities enabling lithography defect detection down to single line short levels. Thus, completely new inspection approaches for tool and line monitoring can be developed, sample plans can be optimized, and time to results and appropriate corrective actions can be significantly shortened.

Significant effort has been directed in recent years towards the realization of immersion lithography at 193nm wavelength. Immersion lithography is likely a key enabling technology for the production of critical layers for 45nm and 32nm design rule (DR) devices. In spite of the significant progress in immersion lithography technology, there remain several key technology issues, with a critical issue of immersion lithography process induced defects. The benefits of the optical resolution and depth of focus, made possible by immersion lithography, are well understood. Yet, these benefits cannot come at the expense of increased defect counts and decreased production yield. Understanding the impact of the immersion lithography process parameters on wafer defects formation and defect counts, together with the ability to monitor, control and minimize the defect counts down to acceptable levels is imperative for successful introduction of immersion lithography for production of advanced DR's. In this report, we present experimental results of immersion lithography defectivity analysis focused on topcoat layer thickness parameters and resist bake temperatures. Wafers were exposed on the 1150i-α-immersion scanner and 1200B Scanner (ASML), defect inspection was performed using a DUV inspection tool (UVision^TM, Applied Materials). Higher sensitivity was demonstrated at DUV through detection of small defects not detected at the visible wavelength, indicating on the potential high sensitivity benefits of DUV inspection for this layer. The analysis indicates that certain types of defects are associated with different immersion process parameters. This type of analysis at DUV wavelengths would enable the optimization of immersion lithography processes, thus enabling the qualification of immersion processes for volume production.

In semiconductor manufacturing, the control of defects at the edge of the wafer is a key factor to keep the number of yielding die on a wafer as high as possible. Using dry lithography, this control is typically done by an edge bead removal (EBR) process, which is understood well. Immersion lithography however changes this situation significantly. During this exposure, the wafer edge is locally in contact with water from the immersion hood, and particles can then be transported back and forth from the wafer edge area to the scanner wafer stage. Materiel in the EBR region can also potentially be damaged by the dynamic force of the immersion hood movement. In this paper, we have investigated the impact of immersion lithography on wafer edge defectivity. In the past, such work has been limited to the inspection of the flat top part of the wafer edge, due to the inspection challenges at the curved wafer edge and lack of a comprehensive defect inspection solution. This study utilized KLA-Tencor's VisEdge, a new automated edge inspection system, that provides full wafer edge imaging (top, side, bottom) using laser-based optics and multi-sensor detection, and where defects of interest can be classified with Automated Defect Classification (ADC) software. Using the VisEdge technology, the impact from the immersion lithography towards wafer edge defectivity is investigated. The work revealed several key challenges to keep the wafer edge related defectivity under control : choice of resist, optimization of EBR recipes, scanner pollution and related memory effects, wafer handling, device processing, etc... Contributing to the understanding of the mechanisms of wafer edge related immersion defects and to the optimization the die yield level, this technology is believed to be important when the immersion processes are introduced in semiconductor manufacturing.

This paper is a comprehensive summary and analysis of a SEMATECH funded project to study the limits of optical critical dimension scatterometry (OCD). The project was focused on two primary elements: 1) the comparison, stability, and validity of industry models and 2) a comprehensive analysis of process stacks to evaluate the ultimate sensitivity and limits of OCD. Modeling methods are a requirement for the interpretation and quantitative analysis of scatterometry data. The four models evaluated show good agreement over a range of targets and geometries for zero order specular reflection as well as higher order diffraction. A number of process stacks and geometries representing semiconductor manufacturing nodes from the 45 nm node to the 18 nm node were simulated using several measurement modalities including angle-resolved scatterometry and spectrally-resolved scatterometry, measuring various combinations of intensity and polarization. It is apparent in the results that large differences are observed between those methods that rely upon unpolarized and single polarization measurements. Using the three parameter fits and assuming that the sensitivity of scatterometry must meet the criterion that the 3σ uncertainty in the bottom dimension must be less than 2% of the linewidth, specular scatterometry solutions exist for all but the isolated lines at 18 nm node. Scatterometry does not have sufficient sensitivity for isolated and semi-isolated lines at the 18 nm node unless the measurement uses wavelengths as short as 200 nm or 150 nm and scans over large angle ranges.

Control of critical dimension (CD) of 65nm and beyond nodes is the hot issue now. As feature size reduces it becomes difficult to measure CD precisely. A lot of factors can influence on accuracy of measurement. Scatterometry method is applicable for both production and development purpose, and can be used for in-situ or ex-situ control. In this work we study influence of CD non-uniformity and sidewall angle as well as influence of parameters of measurement system on precision of result. TE, TM and unpolarized light with different angle of incidence on grating structure is considered to find the best conditions for CD measurements of 65 and 45nm nodes. Rigorous coupled-wave analysis (RCWA) is used for theoretical spectra calculation and least square method for results extraction. Reflected spectrum from structures containing non-uniform or uniform CDs with variation of sidewall angle is compared with the set of theoretical spectra, and CD value with layer thickness is extracted in the same way as in the real experiment. It is shown that CD non-uniformity and sidewall angle can be estimated through comparison of results obtained with different polarization state of light. Best choice of polarization, angle of light incidence, range of wavelength for spectrum measurement and parameters of library for spectrum analysis are obtained in order to provide precise and fast scatterometry measurement for 65 and 45nm nodes mask structures.

In-line process control in microelectronics manufacturing requires real-time and non-invasive monitoring techniques. Among the different metrology techniques, scatterometry, based on the analysis of ellipsometric signatures (i.e stokes coefficients vs. wavelength) of the light scattered by a patterned structures, seems to be well adapted. Traditionally, the problem of defining the shape and computing the signature is dealt with modal methods and is called direct problem. On the opposite, the inverse problem allows to find the grating shape thanks to an experimental signature acquisition, and can not be solved as easily. Different classes of algorithms have been introduced (evolutionary, simplex, etc.) to address this problem, but the method of library searching seems to be the most attractive technique for industry. This technique has many advantages that will be presented in this article, however the main limitation in real-time context comes from the short data acquisition time for different wavelengths. Indeed, the lack of data leads to the method failure and several database patterns can match the experimental data. In this article, a technique for real time reconstruction of grating shape variation using dynamic scatterometry is presented. The different tools to realize this reconstruction, such as Modal Method by Fourier Expansion, regularization technique and specific software and hardware architectures are then introduced. Results issued from dynamic experiments will finally illustrate this paper.

A new Mueller polarimeter based on liquid crystals and a microscope objective is presented, for the characterization of diffraction gratings in a conical diffraction mounting. Fast measurements of complete Mueller matrices over a range of polar angles (0-56°) and azimuthal angles (0-360°) are achieved without mechanical movements. The polarization state generator and analyzer make use of nematic variable retarders. The angular range is achieved through focalization of light over the measured sample with a microscope objective with a high numerical aperture and imaging of the objective back Fourier plane on a CCD. Results on isotropic samples and diffraction gratings are shown.

We investigate the effects that variations in profile have on specular and diffuse reflectance from a grating consisting of parallel lines. We investigate, as an example, a nominal grating consisting of photoresist or silicon lines on a silicon substrate, having a vertical sidewall angle, a width of 100 nm, a pitch of 200 nm, and a height of 200 nm. We model the effects of variations by calculating the reflectance of multiple 25-line superstructures, in which the positions of the line edges are randomly modulated about their nominal profile. We study line-edge variation, line-position variation, and random edge variation in order to test the hypothesis that the reflectance of a grating with variations in line profile can be approximated by the reflectance of a grating with uniform lines having the average line profile. We find that the reflected field can be approximated by the mean field reflected by a distribution of periodic gratings and that the field does not represent the field from the average profile. When fitting results to more than one modeled parameter, the changes that are observed can be enough to shift the deduced parameter in some cases by more than the rms variation of that parameter. We also investigate the diffuse scattering by the grating by considering the diffraction orders of the 25-line period. The intensity distribution and the polarization of the diffuse scattering are found to be different for line-width variation and line-position variation.

One of the key challenges in critical dimension (CD) metrology is finding suitable calibration standards. Over the last few years there has been some interest in using features measured with the transmission electron microscope (TEM) as primary standards for linewidth measurements. This is because some modes of TEM can produce lattice-resolved images having scale traceability to the SI (Systeme International d'Unites or International System of Units) definition of length through an atomic lattice constant. As interest in using calibration samples that are closer to the length scales being measured increases, so will the use of these TEM techniques. An area where lattice-traceable images produced by TEM has been used as a primary standard is in critical dimension atomic force microscope (CD-AFM) tip width calibration. Two modes of TEM that produce crystal lattice-traceable images are high resolution transmission electron microscope (HR-TEM) and high angle annular dark field scanning transmission electron microscope (HAADF-STEM). HR-TEM produces lattice-traceable images by interference patterns of the diffracted and transmitted beams rather than the actual atomic columns, while HAADF-STEM produces direct images of the crystal lattice. The difference in how both of these techniques work could cause subtle variations in the way feature edges are defined. In this paper, we present results from width samples measured using HR-TEM and HAADF-STEM. Next we compare the results with measurements taken from the same location by two different CD-AFMs. Both of the CD-AFM instruments used for this work have been calibrated using a single crystal critical dimension reference material (SCCDRM). These standards, developed by the National Institute of Standards and Technology (NIST) and SEMATECH, used HR-TEM for traceable tip-width calibration. Consequently, the present work and the previous SCCDRM work provide a mutual cross-check on the traceability of the width calibration. Excellent agreement was observed.

CD-AFMs (critical dimension atomic force microscopes) are instruments with servo-control of the tip in more than one direction. With appropriately "boot-shaped" or flared tips, such instruments can image vertical or even undercut features. As with any AFM, the image is a dilation of the sample shape with the tip shape. Accurate extraction of the CD requires a correction for the tip effect. Analytical methods to correct images for the tip shape have been available for some time for the traditional (vertical feedback only) AFMs, but were until recently unavailable for instruments with multi-dimensional feedback. Dahlen et al. [J. Vac. Sci. Technol. B23, pp. 2297-2303, (2005)] recently introduced a swept-volume approach, implemented for 2-dimensional (2D) feedback. It permits image simulation and sample reconstruction, techniques previously developed for the traditional instruments, to be extended for the newer tools. We have introduced [X. Qian and J. S. Villarrubia, Ultramicroscopy, in press] an alternative dexel-based method, that does the same in either 2D or 3D. This paper describes the application of this method to sample shapes of interest in semiconductor manufacturing. When the tip shape is known (e.g., by prior measurement using a tip characterizer) a 3D sample surface may be reconstructed from its 3D image. Basing the CD measurement upon such a reconstruction is shown here to remove some measurement artifacts that are not removed (or are incompletely removed) by the existing measurement procedures.

We studied a three-layer backpropagation neural network to describe nonlinear relationships between inputs (error sources/control knobs) and output CDs. The application of the neural network to modeling of optical proximity effect for a 65nm node CMOS gate layer was investigated. The prediction accuracy of the neural network was improved with the increase in the training data size, becoming higher than that of a conventional lithography simulation with a lumped parameter model. The result suggests that neural networks trained with a sufficient amount of data can provide the same or higher accuracy for the CD error prediction than physical model-based approaches. The use of information of aerial images as input parameters improved the accuracy. Also, pattern density effects, which are difficult to treat by a conventional lithography simulation, could be successfully reflected in the CD error prediction. Using lot data over a period of time, we trained a neural network in which the exposure parameters and lot mean CDs were inputs and outputs, respectively. From the network, lot mean CDs for successive periods were able to be predicted. From these results, we conclude that the application of neural networks for CD control in advanced lithography is worth developing.

Specular X-ray reflectivity (SXR) can be used, in the limit of the effective medium approximation (EMA), as a highresolution shape metrology for periodic patterns on a planar substrate. The EMA means that the density of the solid pattern and the space separating the periodic patterns are averaged together. In this limit the density profile as a function of pattern height obtained by SXR can be used to extract quantitative pattern profile information. Here we explore the limitations of SXR as a pattern shape metrology by studying a series of linear grating structures with periodicities ranging from 300 nm to 16 &mgr;m. The applicability of the EMA is related to the coherence length of the Xray source. For our slit-collimated X-ray source, the coherence length in the direction parallel to the long axis of the slit is on the order of 900 nm while the coherence along the main axis of the beam appears to be much greater than 16 &mgr;m. Limitations of the SXR pattern shape metrology are discussed and examples of determining quantitative pattern profiles provided.

Wafer exposure process simulation and optical photomask feature metrology both rely on optical image modeling for accurate results. The best way to gauge the accuracy of an imaging model is to compare the model results with an actual image. Modeling results, however, depend on several input parameters describing the object and imaging system, such as wavelength, illumination and objective NA's, magnification, focus, etc. for the optical system, and topography, complex index of refraction n and k, etc. for the object. Errors in these parameter values can lead to significant differences between the actual image and the modeled image. Because of these parametric uncertainties, one would hope and expect the models to be far more accurate than such a comparison might indicate. An alternative used here is to compare different imaging models with each other. While the parameter nominal values should be chosen to represent real objects and instruments, they will be identical for both models and contribute no uncertainty to the conclusions. Admittedly not a complete or satisfactory answer to the question of image modeling accuracy, such a differential comparison at least places a meaningful number on modeling differences and sets a limit on modeling accuracy.

Critical dimension atomic force microscopes (CD-AFMs) are rapidly gaining acceptance in semiconductor manufacturing metrology. These instruments offer non-destructive three dimensional imaging of structures and can provide a valuable complement to critical dimension scanning electron microscope (CD-SEM) and optical metrology. Accurate CD-AFM metrology, however, is critically dependent upon calibration of the tip width. In response to this need, NIST has developed prototype single crystal critical dimension reference materials (SCCDRMs). In 2004, a new generation of SCCDRMs was released to the Member Companies of SEMATECH - a result of the fruitful partnership between several organizations. These specimens, which are fabricated using a lattice-plane-selective etch on (110) silicon, exhibit near vertical sidewalls and high uniformity and can be used to calibrate CD-AFM tip width to a standard uncertainty of about ± 1 nm. Following the 2004 release, NIST began work on the "next generation" of SCCDRM standards. A major goal of this thrust was to improve upon the SCCDRM characteristics that impact user-friendliness: the linewidth uniformity and cleanliness. Toward this end, an experiment was designed to further optimize the process conditions. The first round of this experiment was recently completed, and the results show great promise for further improvement of the SCCDRM manufacturing process. Among other observations, we found that the minimum linewidth and linewidth uniformity were primarily sensitive to different factors - and can thus be independently tuned to meet our future goals - which include linewidths as small as 20 nm and a standard uncertainty due to non-uniformity at the ± 0.5 nm level. Our future work will include a new refining experiment to further optimize the important factors that we have identified, and extension of the methodology to a monolithic 200 mm implementation.

Since the advent of critical-dimension atomic force microscopes (CD-AFMs) in the 90s, these tools have enjoyed growing acceptance in semiconductor manufacturing both for process development and to support in-line critical dimension (CD) metrology. The most common application of CD-AFMs has been to support critical-dimension scanning electron microscope (CD-SEM) and scatterometer metrology as a reference for tool matching or as a nondestructive alternative to transmission electron microscopy (TEM) and scanning electron microscopy (SEM) cross sections. For many years, CD-AFM users typically developed in-house reference standards for tip width calibration - often based on SEM or TEM cross sections. But the uncertainty of such standards was often large or unknown. Tip characterizer samples - which used a sharp ridge to calibrate the tip width - are commercially available. However, scanning such samples can result in tip damage, and the uncertainty of tip calibrations based on this method is at least 5 nm. In 2004, NIST, SEMATECH, and VLSI Standards collaborated on the development and release of single crystal critical dimension reference materials (SCCDRMs) to SEMATECH member companies. These specimens, which are fabricated using a lattice-plane-selective etch on (110) silicon, exhibit near vertical sidewalls and high uniformity and can be used to calibrate CD-AFM tip width to approximately 1 nm standard uncertainty (k = 1). Also in 2004, commercial critical dimension standards (CCDS) were introduced. Using CD-AFM instruments at both NIST and SEMATECH, we have performed a comparison of nominal 45 nm and 70 nm CCDS specimens with the SCCDRM calibration. Our observations show that these two independently performed calibrations are in agreement.

An extensive test series was undertaken to validate image reconstruction algorithms used with critical dimension atomic force microscopy (CD AFM). Transmission electron microscopy (TEM) was used as the reference metrology system (RMS) with careful attention devoted to both calibration and fiducial marking of TEM sample extraction sites. Shape measurements for the CD probe tips used in the study were acquired both through the use of reentrant image reconstruction and independent (non-destructive) TEM micrographs of the probe tips. TEM images of the tips were acquired using a sample holder that provided the same projection of the tip as presented to the sample surface during AFM scanning. In order to provide meaningful validation of the CD AFM image reconstruction algorithm, widely varying sample morphologies and probe tip shapes were selected for the study. The results indicate a 1 - 2 nm bias between the TEM and CD AFM that is within the uncertainty of the measurements given the Line Width Variation (LWV) of the samples and accuracy of the measurement systems. Moreover, each TEM sample consisted of a grid with multiple features (i.e., 21 to 22 features). High density CD AFM pre-screening of the sample allowed precise locating of the TEM extraction site by correlating multiple feature profile shapes. In this way, the LWV and height of the sample were used to match measurement location for the two independent metrology systems.

The ever decreasing size of semiconductor features demands the advancement of critical dimension atomic force microscope (CD-AFM) technology, for which the fabrication and use of more ideal probes like carbon nanotubes (CNT) is of considerable interest. The recent progress in the precise control of CNT orientation, length, and end modification, using manipulation and focused ion beam processes, allowed us to implement ball-capped CNT tips and bent CNT tips for CD-AFM. Such CNT tips have been tested for the first time in a commercial CD-AFM to image a grating and line edge roughness samples. We found out that CNT tips can reasonably scan the pattern profiles including re-entrant sidewalls with the CNT tip geometries we used and with the available range of scan parameters. There still remain important issues to address - including tighter control of tip geometry and optimization of scan parameters and algorithms for using CNT tips.

The present paper shows the characterization of the shallow trench isolation (STI) profile of 65 nm node ULSI logic products done with an automated AFM system and high-density carbon tips. The combined utilisation of special tips and dedicated analysis algorithms has allowed the precise measurement of both the step height between the isolation oxide and the silicon active area, and the depth of the divot that is generally formed at the isolation oxide's sidewalls. Moreover, the robustness of this methodology has been assessed by evaluating the maximum number measurement runs before the appearance of relevant artifacts due to tips' apex modifications. Finally, TEM cross-sections were run in order to determine the accuracy of the measurements.

The performance needs of a bottom antireflection coating (BARC) used in advanced optical lithography are extremely demanding, with reflectivities as low as 0.1% and even lower often required. BARC thickness and complex refractive index values (n = n + iκ) must be highly optimized, requiring accurate knowledge of the BARC, resist and substrate optical properties. In this paper, we have performed a theoretical analysis of the BARC optimization process with respect to the propagation of BARC n and κ measurement errors. For several realistic cases, specifications on the measurement accuracy of these optical parameters will be derived and the lithographic consequences of BARC metrology errors will be explored. Approaches to improving the measurement of BARC thickness and refractive index will be suggested.

We analyzed the electron-irradiation damage induced by electron-beam inspection of MNOS capacitors with various gate-dielectric thicknesses. Damage induced in a MNOS capacitor with SiON dielectric for high-performance CMOS devices was compared with that induced on a MOS capacitor with SiO₂ dielectric. We found that there is no remarkable difference between the damage to MOS capacitors and that to MNOS capacitors. The induced damage strongly depends on the thickness of the gate dielectric. Damages were induced when a higher-energy electron-beam, whose electron range was larger than the thickness of the gate electrode, was irradiated. When the electron beam was irradiated to a MOS capacitor with gate-dielectric thickness of 10.0 nm the flat-band-voltage shifted due to the created traps. When the electron beam was scanned to a MOS or MNOS capacitor with gate-dielectric thickness of 4.0 nm, Vfb shifted by less than 6 mV. However, the leakage-current density increased to 10^-7 A/cm² at gate-electrode voltage of 3.0 V. On the other hand, when the electron beam was scanned on a MNOS capacitor with 2.5-nm-thick SiON dielectric, even the leakage current density was not increased. Accordingly, for damage-free inspection when gate-dielectric thickness is 4.0 nm or more, the electron-beam energy should be lower so that the electron range is smaller than the thickness of the gate electrode.

Optical and Process Correction in the 45nm node is requiring an ever higher level of characterization. The greater complexity drives a need for automation of the metrology process allowing more efficient, accurate and effective use of the engineering resources and metrology tool time in the fab, helping to satisfy what seems an insatiable appetite for data by lithographers and modelers charged with development of 45nm and 32nm processes. The scope of the work referenced here is a 45nm design cycle "full-loop automation", starting with gds formatted target design layout and ending with the necessary feedback of one and two dimensional printed wafer metrology. In this paper the authors consider the key elements of software, algorithmic framework and Critical Dimension Scanning Electron Microscope (CDSEM) functionality necessary to automate its recipe creation. We evaluate specific problems with the methodology of the former art, "on-tool on-wafer" recipe construction, and discuss how the implementation of the design based recipe generation improves upon the overall metrology process. Individual target-by-target construction, use of a one pattern recognition template fits all approach, a blind navigation to the desired measurement feature, lengthy sessions on tool to construct recipes and limited ability to determine measurement quality in the resultant data set are each discussed as to how the state of the art Design Based Metrology (DBM) approach is implemented. The offline created recipes have shown pattern recognition success rates of up to 100% and measurement success rates of up to 93% for line/space as well as for 2D Minimum/Maximum measurements without manual assists during measurement.

We have recently described a technique for optical line-width measurements. The system currently is capable of measuring line-width down to 60 nm with a precision of 2 nm, and potentially should be able to measure down to 10nm. The system consists of an ultra-stable interferometer and artificial neural networks (ANNs). The former is used to generate optical profiles which are input to the ANNs. The outputs of the ANNs are the desired sample parameters. Different types of samples have been tested with equally impressive results. In this paper we will discuss the factors that are essential to extend the application of the technique. Two of the factors are signal conditioning and sample classification. Methods, including principal component analysis, that are capable of performing these tasks will be considered.

Traditionally CD SEM has been positioned as a local critical dimension measurement and analysis technique. Emerging lithography techniques introduce new challenges for CD SEM such as overlay error measurements. For the sub 45 nm technology nodes, several new lithography approaches are developed that rely on multiple lithography and deposition and etch process steps. Seamless integration of these lithography and deposition and etch process steps requires specific CD and/or overlay metrology capability for optimal CD and overlay registration performance. Areas of development are focused on CD measurement algorithms and correlation after resist develop and subsequent etch steps. These new lithography processes require unprecedented accuracy and overlay resolution. Fundamental and application specific metrology challenges and solutions will be highlighted. In addition, this paper will report on unique overlay target design in combination with innovative CD SEM measurement techniques to meet those challenges.

A new measurement system analysis (MSA) methodology has been developed at Texas Instruments (TI) to evaluate the status of the 65 nm technology critical dimension (CD) metrology and its readiness for production. Elements of the methodology were used in a previously reported scatterometry evaluation [1]. At every critical process level the precision, bias, linearity and total measurement uncertainty (TMU) were evaluated for metrology fleet over extended periods of time, and with the technology representative set of samples. The samples with variations that fully covered and often exceeded process space were pre-calibrated by CD atomic force microscope (AFM). CD AFM measurement precision was determined for every analyzed process level based on repeated measurements conducted over several days. The National Institute of Standards and Technologies (NIST) traceable standards were used to verify CD AFM line CD and scale calibrations. Therefore, for the first time the NIST traceability has been established for CD metrology at every critical process level for the entire technology. The data indicates an overall healthy status of the 65 nm CD metrology. Sub-nanometer accuracy has been established for gate CD metrology. The thorough CD metrology characterization and specifically absolute CD calibration were instrumental in seamless technology transfer from 200 mm to 300 mm fabs. The qualification of CD metrology also revealed several problems. Most of these are well-known from previous studies and should soon be addressed. CD scanning electron microscopy (SEM) has a systematic problem with bias of CD measurements. The problem is common for several front-end and back-end of line process levels. For most process levels, TMU of CD SEM is noticeably affected by sample modification inflicted by electron irradiation (shrinkage, charging, buildups, etc.). This causes problems, especially in the case of fleet TMU evaluation. An improved data collection methodology should be devised to minimize the impact of sample modification on fleet TMU measurements. The reported progress in semiconductor industrial CD metrology became possible after a recent breakthrough in line CD standard technology [2,3], recognition of CD AFM as an instrument for CD traceability [4,5] and development of the concept and mathematical tools for TMU analysis [6,7].

A scanning ion microscope (SIM) is analogous to a scanning electron microscope (SEM) but utilizes a beam of helium ions, with energy of 10 to 25 keV , instead of electrons. The SIM potentially offers several advantages for device critical dimension metrology as compared to the more familiar CD-SEM. These include a high brightness source which is sub-nanometer in size, an enhanced secondary electron yield, restricted beam penetration, and superior image contrast and information content. Possible problems include pervasive positive charging, ion implantation, and a lack of detailed experimental and theoretical knowledge about low energy ion interactions with solids. Comparison of line profiles across structures made by electron induced and ion induced secondary electrons show that there are some significant differences between them which arise from the different modes of interaction in the two cases. As a result the algorithms employed for line width determination will require revision in order to produce data which is consistent with CD-SEM data.

A key responsibility of a metrology engineer is to reduce measurement uncertainty. While important, decreasing measurement uncertainty is only one of many tasks the metrology engineer needs to address. A broader view includes continually improving the productivity of the metrology toolset. This requires the appropriate skills, methods and analysis tools to identify and address the key issues efficiently. Often, limitations in recipe build experience, inadequate calibrations and monitoring of the fleet and toolset limitations, cause many productivity issues that directly affect the cycle-time, toolset throughput, and the efficient use of engineering resources. This paper explores the analysis tools needed to improve productivity by analyzing metrology toolset recipe errors. Examples of methods and an application developed and used by IBM will be shown along with how they have lead to improved productivity of the fleet. Further, a discussion is included catered towards standardizing the critical information needed from suppliers for building universal analysis tools to allow improvements in productivity.

The conventional premise that metrology is a "non-value-added necessary evil" is a misleading and dangerous assertion, which must be viewed as obsolete thinking. Many metrology applications are key enablers to traditionally labeled "value-added" processing steps in lithography and etch, such that they can be considered integral parts of the processes. Various key trends in modern, state-of-the-art processing such as optical proximity correction (OPC), design for manufacturability (DFM), and advanced process control (APC) are based, at their hearts, on the assumption of fine-tuned metrology, in terms of uncertainty and accuracy. These trends are vehicles where metrology thus has large opportunities to create value through the engineering of tight and targetable process distributions. Such distributions make possible predictability in speed-sorts and in other parameters, which results in high-end product. Additionally, significant reliance has also been placed on defect metrology to predict, improve, and reduce yield variability. The necessary quality metrology is strongly influenced by not only the choice of equipment, but also the quality application of these tools in a production environment. The ultimate value added by metrology is a result of quality tools run by a quality metrology team using quality practices. This paper will explore the relationships among present and future trends and challenges in metrology, including equipment, key applications, and metrology deployment in the manufacturing flow. Of key importance are metrology personnel, with their expertise, practices, and metrics in achieving and maintaining the required level of metrology performance, including where precision, matching, and accuracy fit into these considerations. The value of metrology will be demonstrated to have shifted to "key enabler of large revenues," debunking the out-of-date premise that metrology is "non-value-added." Examples used will be from critical dimension (CD) metrology, overlay, films, and defect metrology.

Accurate, precise, and rapid three-dimensional (3D) characterization of patterning processes in integrated circuit development and manufacturing is critical for successful volume production. As process tolerances and circuit geometries shrink with each technology node, the precision, accuracy, and capability requirements for dimension and profile metrology intensify. The present work adopts the scanning probe based technology, 3D atomic force microscopy (AFM), to address current and next-generation critical dimension (CD) metrology needs for device features at a variety of process steps. Fast, direct, and non-destructive 3D profile characterization of patterning processes is a primary benefit of CD AFM metrology. The CD AFM utilizes a deep trench (DT) mode for narrow and deep trenches, and a CD mode for linewidth and sidewall profiling. The 3D capability enables one tool for many applications where conventional scanning electron microscopy (SEM), scatterometry, and stylus profiler tools fall short: Gate etch/resist linewidth and sidewall cross-section profile, etch depth for high aspect ratio via, STI etch depth, 3D analysis for MUGFET multi-gate devices, pitch/CD/sidewall angle (SWA) verification for scatterometry targets, and post-CMP active recess. The AFM is an efficient tool for inline monitoring, rapid process improvement/development, and is a complementary addition to the dimension metrology family.

Most semiconductor manufacturers expect 193nm immersion lithography to remain the dominant patterning technology through the 32nm technology node. Conventional immersion lithography, however, is unlikely to take the industry to 32nm half-pitch. Various double patterning techniques have been proposed to address this limitation. These solutions will combine design for manufacturability (DFM) and advanced process control (APC) strategies to achieve desired yield. Each strategy requires feeding forward design and process context and feeding back process metrics. In this work, we discuss some interim solutions for control of double patterning lithography (DPL), as well as some spacer-etch alternatives. We conclude with focus-exposure data showing some potential challenges for pitch-splitting strategies implemented in the context of immersion lithography.

The Line Width Roughness (LWR) measured by lithographers usually refers to long resist lines. On the contrary, the transferred roughness in the transistor gate (Gate Length Roughness, GLR) which is one eventually affecting transistor performance is associated with short gate widths equal to only a few multiples of CD values. Given that the most basic roughness metric, r.m.s. value R_q (or sigma), depends on the sample length at which is measured, the issue of the metrological relationship between resist (or lithographic) LWR and transistor GLR arises. The LWR parameter which seems to link these two kinds of roughness is the correlation length, since it determines the form of the curve R_q(L) describing the dependence of r.m.s. value on line length L. This paper investigates three issues relating to correlation length. The first is the precision of its measurement and it is found that the relative standard deviation of the measured values can become less than 25% provided that sufficient line lengths are included in the measurement process. Further, the measurement uncertainty is reduced when lower correlation lengths are measured. Secondly, we examine the importance of the correlation length to the electrical transistor performance and show that lower correlation lengths increase noticeably the fraction of good transistors with reliable small voltage threshold shifts independent on the used technology node and gate width. Finally, the material and process origins of correlation length variations are investigated in order to locate the appropriate changes for reducing correlation length.

The need to characterize line edge and line width roughness in patterns with sub-50 nm critical dimension challenges existing platforms based on electron microscopy and optical scatterometry. The development of x-ray based metrology platforms provides a potential route to characterize a variety of parameters related to line edge roughness by analyzing the diffracted intensity from a periodic array of test patterns. In this study, data from a series of photoresist line/space patterns featuring programmed line width roughness measured by critical dimension small angle x-ray scattering (CDSAXS) is presented. For samples with periodic roughness, CD-SAXS provides the wavelength and amplitude of the periodic roughness through satellite diffraction peaks. In addition, the rate of decay of intensity, termed an effective "Debye-Waller" factor, as a function of scattering vector provides a measure of the fluctuation in line volume. CDSAXS data are compared to analogous values obtained from critical dimension scanning electron microscopy (CDSEM). Correlations between the techniques exist, however significant differences are observed for the current samples. Calibrated atomic force microscopy (C-AFM) data reveal large fluctuations in both line height and line width, providing a potential explanation for the observed disparity between CD-SEM and CD-SAXS.

To establish a method for measuring interconnect line-edge roughness (LER), low-k line patterns were observed and electric-field concentration was simulated based on the observation results. Wedges were observed on the edges, and the bottom and the top widths of the average wedge feature were 60 nm and 7 nm (or smaller), respectively. Simulation showed that the LER causes serious degradation of TDDB immunity at 100-nm-pitch Cu/low-k interconnects. The maximum electric-field intensity depends upon the conventional LER metric, 3R_q, but depends more strongly on the wedge angle, the curvature of the tip, and the minimum linewidth.

The improvement of devices performances is due to many factors such as new architectures, new materials and better lithography resolution. Resist chemical components play a key role in the final performance of a specific resist. In addition to resist characteristics such as: resolution, etching selectivity, the final resist line edge roughness (LER) and line width roughness (LWR) becomes a critical issue because it can degrade resolution and linewidth accuracy and causes fluctuations of transistors performances^1,2. LER and LWR are currently calculated with top-down view SEM images. With chemically amplified resists, we can play on photoacid generator size to partially control acid diffusion length during the post exposure bake. In this paper we propose to compare two techniques, the CD-AFM and CD SEM in order to study the impact of various acid diffusion lengths on LER and LWR. The results show that globally the two techniques agree on most of the results and show the same trends. However, when the profiles vary the linearity between the two techniques can vary drastically. In addition, as a complementary technique to the CD-SEM technique, the CD-AFM gives additional information such as height (top loss), top rounding and sidewall angle which allow us to understand more deeply the impact of PAG size. Therefore, these additional information have a non negligible impact on near term new resist development and lithography processes development. As an illustration of this work, we will present the latest resist development coming from this understanding and leading to very low LER and LWR. Finally, we will propose strengths and weakness of each technique.

With decreasing Critical Dimensions (CD), the negative influence of line edge roughness (LER) and line-width roughness (LWR) on CD uniformity and mean-to-target CD becomes more pronounced, since there is no corresponding reduction of roughness with dimension reduction. This applies to wafer metrology as well as to mask metrology. In order to better understand the types of roughness as well as the impact of the CD-SEM roughness measurement capabilities on the control of the mask process, the sensitivity and accuracy of the roughness analysis were qualified by comparing the measured mask roughness to the design for a dedicated LER test mask. This comparison is done for different LER amplitude and periodicity values and for reference structures without nominal LER using the built-in CD-SEM algorithms for LER characterization.

The need for 3D metrology is becoming more urgent to address critical gaps in metrology for both lithographic and etch processes. Current generation lithographic processing (ArF source, where λ=193 nm) sometimes results in photoresist lines with re-entrant profiles or T-topping, as do many etch processes. A re-entrant profile misleads top-down metrology into reading the critical dimension (CD) as too large. Recent advances in gate process technology also raise challenges to traditional top-down metrology. One such example is the FinFET, which is truly a 3D device with 3D metrology needs. The ability to measure the bottom width of a profile is crucial for process control. Recently, tilt-beam critical dimension-scanning electron microscopy (CD-SEM) applications have been developed to measure the bottom CD of such features, using the tilted-view to "see" the bottom, avoiding the feature's larger top. This is an important achievement, as the bottom of a profile is the main feature of interest in many processes. Estimation of sidewall angle (SWA) is also important. For several years, tilt-beam CD-SEM has been an available technique for this measurement, with limited adoption by the litho-metrology community. However, in this paper we will explore another method to use the tilt feature to measure average sidewall angle, based on edgewidth measurement and the assumption of basic trapezoidal profile and known height and combined with the ability to sample multiple-features. While it will not provide exact profile shape, this technique can be quite useful in providing average profile information and will definitely exhibit good throughput. Samples used will be photoresist and etched FinFET structures to measure sidewall angles. Correlations of the results to a traceable CD-atomic force microscopy (AFM) reference measurement system are provided. Conclusions will show preliminary findings of the readiness of tilt-beam CD-SEM for measuring profile and, by extension, the status of measuring 3D structures such as FinFETs, and using CD-SEM as a direct control of lithographic tooling for T-topped photoresist profiles.

Optical scatterometry-based metrology is now widely used in wafer fabs for lithography, etch, and CMP applications. This acceptance of a new metrology method occurred despite the abundance of wellestablished CD-SEM and AFM methods. It was driven by the desire to make measurements faster and with a lower cost of ownership. Over the last year, scatterometry has also been introduced in advanced mask shops for mask measurements. Binary and phase shift masks have been successfully measured at all desired points during photomask production before the pellicle is mounted. There is a significant benefit to measuring masks with the pellicle in place. From the wafer fab's perspective, through-pellicle metrology would verify mask effects on the same features that are characterized on wafer. On-site mask verification would enable quality control and trouble-shooting without returning the mask to a mask house. Another potential application is monitoring changes to mask films once the mask has been delivered to the fab (haze, oxide growth, etc.). Similar opportunities apply to the mask metrologist receiving line returns from a wafer fab. The ability to make line-return measurements without risking defect introduction is clearly attractive. This paper will evaluate the feasibility of collecting scatterometry data on pelliclized masks. We explore the effects of several different pellicle types on scatterometry measurements made with broadband light in the range of 320-780 nm. The complexity introduced by the pellicles' optical behavior will be studied.

The lithography potential of an ArF (193nm) laser exposure tool with high numerical aperture (NA) will expand its lithography potential to 65nm node production and even beyond. Consequently, a mask inspection system with a light source, whose wavelength is nearly equal to 193nm, is required so as to detect defects of the masks using resolution enhancement technology (RET). Wavelength consistency between exposure tool and mask inspection tool is strongly required in the field of mask fabrication to obtain high defect inspection sensitivity. Therefore, a novel high-resolution mask inspection platform using DUV wavelength has been developed, which works at 198.5nm. This system has transmission and reflection inspection mode, and throughput using 70nm pixel size were designed within 2 hours per mask. In this paper, transmitted and reflected light image acquisition system and high accuracy focus detection optics are presented.

As mask pattern feature sizes shrink the need for tighter control of factors affecting critical dimensions (CD) increases at all steps in the mask manufacturing process. To support this requirement Intel Mask Operation is expanding its process and equipment monitoring capability. We intend to better understand the factors affecting the process and enhance our ability to predict reticle health and critical dimension performance. This paper describes a methodology by which one can predict the contribution of the dry etch process equipment to overall CD performance. We describe the architecture used to collect critical process related information from various sources both internal and external to the process equipment and environment. In addition we discuss the method used to assess the significance of each parameter and to construct the statistical model used to generate the predictions. We further discuss the methodology used to turn this model into a functioning real time prediction of critical dimension performance. Further, these predictions will be used to modify the manufacturing decision support system to provide early detection for process excursion.

This paper describes a method to automatically distinguish between line and space for 1:1 line space patterns in mask metrology. As the number of measurements typically performed on a reticle is significantly higher than on a wafer, automated CAD based CD-SEM recipe creation is essential. Such recipes typically use synthetic pattern recognition targets instead of SEM based pattern recognition targets. Therefore, a possible different contrast between lines and spaces on a mask cannot be utilized for distinguishing lines from spaces. We demonstrate an algorithm solution based on the analysis of the SEM waveform profiles to identify potential L/S mix-ups and correct them automatically. The solution allows fully automated CAD based offline recipe creation with a high success rate of distinction between lines and spaces for 1:1 pitch cases without the necessity of editing recipes on the tool in advance of performing the measurements.

Measurement and control of edge profiles and edge angles is increasingly important in advanced lithography. Especially for critical dimension metrology a sophisticated multi-dimensional shape metrology is highly beneficial. Different types of dimensional metrology instrumentation are in use today for edge profile and edge angle measurement. While destructive cross section SEM measurements often serve as reference, AFM and optical scatterometry systems are commonly used for day-to-day or in-line control. Due to the limitations of these metrology systems (AFM: slow, scatterometry: only integral measurements of periodic structures), the evaluation and modelling of top down SEM images is increasingly considered, too. At the PTB both SEM and AFM as well as optical scatterometry are applied for edge angle and/or edge profile metrology, supported by optical transmission microscopy. At the PTB we have realised a new DUV hybrid scatterometer for measurements over the full range of 6025 format masks which combines essential elements of a reflectometer, an ellipsometer, and a diffractometer. In addition to scatterometric measurements this set-up allows to measure the complete Müller-matrix including transmission, polarisation and depolarisation. This new set-up will be presented in detail. Finally we study the possibilities of evaluating high resolution top down SEM images to determine edge angles. The potential of edge angle evaluation using these new analysis procedures will be discussed. We present an overview of the PTB measurement capabilities with an emphasis on newly developed metrology methods and systems.

As lithography mask process moves toward 45nm and 32nm node, phase control is becoming more important than ever. Both attenuated and alternating PSMs (Phase Shift Masks) need precise control of phase as a function of both pitch and target sizes. However conventional interferometer-based phase shift measurements are limited to large CD targets and requires custom designed target in order to function properly, which limits phase measurement. Imaging simulations, both, in a rigorous and a Kirchhoff regime, show the dependency of the phase in the image plane of a microlithography exposure tool on numerical aperture, polarization, and on the so-called balancing of the mask for features close to the size of the used wavelength. For these feature sizes, the image phase does not coincide with the etch depth equivalent phase calculated from the nominal depth and optical constants of the shifter material. Additionally, for PSMs generating phase jumps deviating from 180°, the resulting phase in the image plane of a microlithography exposure tool depends on the transmitted diffraction orders through the aperture of the imaging system. Consequently Zeiss, in collaboration with Intel, has started the development of a laterally resolving Phase Metrology Tool (Phame) for in-die phase measurements. In this paper we present this optical metrology tool capable of phase measurement on individual line/spaces down to 120nm half pitch. Alternating PSM, Attenuated PSM, Cr-less masks were measured on various target sizes and simulations were performed to further demonstrate the capability and implication of this new method to measure the scanner relevant phase in-die, taking into account NA, polarization, and rigorous effects.

Semiconductor industry has an increasing demand for improvement of the total lithographic overlay performance. To improve the level of on-product overlay control the number of alignment measurements increases. Since more mask levels will be integrated, more alignment marks need to be printed when using direct-alignment (also called layer-to-layer alignment). Accordingly, the alignment mark size needs to become smaller, to fit all marks into the scribelane. For an in-direct alignment scheme, e.g. a scheme that aligns to another layer than the layer to which overlay is being measured, the number of needed alignment marks can be reduced. Simultaneously there is a requirement to reduce the size of alignment mark sub-segmentations without compromising the alignment and overlay performance. Smaller features within alignment marks can prevent processing issues like erosion, dishing and contamination. However, when the sub-segmentation size within an alignment mark becomes comparable to the critical dimension, and thus smaller than the alignment-illuminating wavelength, polarization effects might start to occur. Polarization effects are a challenge for optical alignment systems to maintain mark detectability. Nevertheless, this paper shows how to actually utilize those effects in order to obtain enhanced alignment and overlay performance to support future technology nodes. Finally, another challenge to be met for new semiconductor product technologies is the ability to align through semi-opaque materials, like for instance new hard-mask materials. Enhancement of alignment signal strength can be reached by adapting to new alignment marks that generate a higher alignment signal. This paper provides a description of an integral alignment solution that meets with these emerging customer application requirements. Complying with these requirements will significantly enhance the flexibility in production strategies while maintaining or improving the alignment and overlay performance. This paper describes the methodology for optimization of the alignment strategy.

We have proposed a new algorithm of Lithography Advanced Process Control System for high-mix low-volume production. This algorithm works well for 1^st lot of a new device input into the production line, or 1st lot of an existing device to be exposed with a newly introduced exposure tool. The algorithm consists of 1) searching the most suitable trend of other similar devices referring to an attribute table and a look-up table for priority of searching order, and 2) correction of differences between the two devices for deciding optimum exposure conditions. The attribute table categorizes same layers across different devices and similar layers within a device. Look-up table describes the order of searching keys. To attain cost-effective process control system, information useful to compensate referred trend is compiled into the database.

K1 factor for development and mass-production of memory devices has been decreased down to below 0.30 in recent years. Process technology has responded with extreme resolution enhancement technologies (RET) and much more complex OPC technologies than before. ArF immersion lithography is expected to remain the major patterning technology through under 35 nm node, where the degree of process difficulties and the sensitivity to process variations grow even higher. So, Design for manufacturing (DFM) is proposed to lower the degree of process difficulties and advanced process control (APC) is required to reduce the process variations. However, both DFM and APC need much feed-back from the wafer side such as hot spot inspection results and total CDU measurements at the lot, wafer, field and die level. In this work, we discuss a new design based metrology which can compare SEM image with CAD data and measure the whole CD deviations from the original layouts in a full die. It can provide the full information of hot spots and the whole CD distribution diagram of various transistors in peripheral regions as well as cell layout. So, it is possible to analyze the root cause of the CD distribution of some specific transistors or cell layout, such as OPC error, mask CDU, lens aberrations or etch process variation and so on. The applications of this new inspection tool will be introduced and APC using the analysis result will be presented in detail.

Micron Technology, Inc., explores the challenges of defining specific wafer sampling scenarios for users of multiple integrated metrology modules within a Tokyo Electron Limited (TEL) CLEAN TRACK^TM LITHIUS^TM. With the introduction of integrated metrology (IM) into the photolithography coater/developer, users are faced with the challenge of determining what type of data is required to collect to adequately monitor the photolithography tools and the manufacturing process. Photolithography coaters/developers have a metrology block that is capable of integrating three metrology modules into the standard wafer flow. Taking into account the complexity of multiple metrology modules and varying across-wafer sampling plans per metrology module, users must optimize the module wafer sampling to obtain their desired goals. Users must also understand the complexity of the coater/developer handling systems to deliver wafers to each module. Coater/developer systems typically process wafers sequentially through each module to ensure consistent processing. In these systems, the first wafer must process through a module before the next wafer can process through a module, and the first wafer must return to the cassette before the second wafer can return to the cassette. IM modules within this type of system can reduce throughput and limit flexible wafer selections. Finally, users must have the ability to select specific wafer samplings for each IM module. This case study explores how to optimize wafer sampling plans and how to identify limitations with the complexity of multiple integrated modules to ensure maximum metrology throughput without impact to the productivity of processing wafers through the photolithography cell (litho cell).

As the advanced IC device process shrinks to below sub-micron dimensions (65nm, 45 nm and beyond), the overall CD error budget becomes more and more challenging. The impact of lithography process parameters other than exposure energy and defocus on final CD results cannot be ignored any more. In this paper we continue the development of an advanced control system, which can be used to detect, classify and correct up to 5 lithography parameters. Sets of focus exposure matrix (FEM) models are first set up with different DOE process conditions split. And photoresist profiles of specially designed scatterometry CD mark are then fitted to models (Neural Network Model or standard polynomial model). Based on these calibrated models, not only exposure and defocus but also PEB temperature, lens aberration, etc. can be estimated. This approach utilizes information of resist CD, height, sidewall and feature type dependent bias to classify different lithography parameters and therefore can give very accurate estimation of lithography parameters like energy, focus, PEB, spherical aberration and coma aberration. The new approach does not need phase shift mask or other specially designed mask, so it can be used by most of mass production Fabs and used for process monitoring and matching on inline production wafer.

Critical Dimension (CD) uniformity control across wafer becomes more and more statistically limited with the continuous aggressive scaling of transistor gate. In the limit due to line edges are self-affine, correlation length and fractal dimension are two parameters that affect the roughness contribution to a given spatial frequency in addition to the standard deviation value which is usually called line edge roughness (LER). In this paper, we will focus on the random contributions instead of systematic ones, particularly from the perspective of LER. The following issues are addressed: How these individual factors affect the CD uniformity from the statistical perspective; How to translate these factors into the processing terms; and finally how to balance these factors to achieve the ultimate CD control goal. Our study is based on both simulation and experimental approach. On the simulation side, the line edges are generated with power spectral density (PSD) which is a function of standard deviation, correlation length and fractal dimension. The dependence of CD uniformity on these factors can be extracted from tens of thousands of simulated edges. We found out that the relationship between the CD variation and the correlation length becomes logarithmic when the gate width is scaled to a degree comparable to the correlation length. On the experimental side, by analyzing the Scanning Electron Microscopy (SEM) images from pre- and post-etching patterns, the process-related implications of these factors on the CD uniformity can be derived. Finally by combining the modeling and experimental data, we will discuss how to trade off these parameters to control the CD variations.

The comparison of scatterometry measurements of complex spacer structures to electrical test measurements is discussed. Details of the NFET and PFET structures are presented, along with a summary of the scatterometry models used to represent the structures. Before comparison data are shown, a methodology and set of metrics are presented that assist in the analysis and interpretation of comparison data. The methodology, called Prediction Analysis, has its roots in TMU analysis, where both measurements are subject to error. But in Prediction Analysis, an "apples-to-apples" comparison of the measurements is not the goal, and the measurements may be reported in different units. The goal of Prediction Analysis is to analyze the components of error in a correlation and use this analysis to predict a measurement based on the knowledge of another measurement, such that the predicted measurement is bounded. This method is used in this work to determine how well scatterometry measurements of certain parameters correlate to electrical measurements of gate resistance, gate Lpoly, and transistor current Ion. Clear correlations are demonstrated, and physical explanations that explain these correlations are presented. Due to the correlations, the scatterometry measurements can be used as a predictor of electrical performance significantly before the electrical test occurs. Because of this, scatterometry can be a reliable measurement technique for improving spacer controls and reducing the mean time to detect (MTTD) some profile abnormalities.

Resist trimming is a technique that is often used to close the gap between line widths which can be repeatedly printed with currently available lithography tools and the desired transistor gate length. For the 65-nm node, the resist line width delivered at pattern is between 60 to 70 nm while the final transistor gate length is usually targeted between 35 to 45 nm. The 15 to 35 nm critical dimension (CD) difference can be bridged by resist trimming. Due to the stringent gate CD budget, a resist trimming process should ideally have the following characteristics: i) no degradation in CD uniformity; ii) no damage in pattern fidelity; iii) controllable CD trim rate with good linearity; and iv) no degradation in line edge roughness (LER) or line width roughness (LWR). Unfortunately, a realistic resist trimming process is never perfect. In particular, resist consumption and the resultant internal stress build-up during resist trimming can lead to resist line bending. The effect of bent resist lines is a higher post-etch CD and significantly degraded local CD uniformity (LCDU). In order to reduce resist bending CD errors (defined as the difference between the post-etch CD and the design CD due to resist bending after trimming) several useful procedures either in layout or in processes are presented. These procedures include: i) symmetrically aligning gates to contact pads and field connecting poly in the circuit layout; ii) enlarging the distance between contact pad (or field connecting poly) to active area within the limits of the design rules (DR) and silicon real estate; iii) adding assist features to the layout within the DR limits; iv) minimizing resist thickness; and v) applying special plasma cure before resist trim.

A non-destructive and fast optical solution for characterization of 3D deep trench mask open structures containing two holes per unit cell is presented. It is discussed that measurement sensitivity depends on wafer orientation. A weighted reference measurement system using data from scatterometry combined with CD-SEM and CD-AFM techniques after HF removal of the top BSG layer demonstrates adequate performance of scatterometry for high aspect ratio 3D process control implementations. For example the BCD major and minor axis scatterometry total measurement uncertainty values are about a factor 2 better than the corresponding results obtained using CD-SEM and CD-AFM. While scatterometry data exhibit close to unity slope for both TCD and BCD, corresponding CD-SEM and CD-AFM performances show significantly stronger dependence on depth. Hence, Scatterometry sensitivity to CD variation is less depth sensitive which is a preferred high volume manufacturing property.

Optical scattering techniques can provide rapid, non-destructive measurements of nanometer-scale structures for micro-fabrication process control. In general, these techniques compare measured optical characteristics of a sample to results generated from a theoretical model. The models can be computationally expensive, especially when used with iterative methods to obtain a solution to the inverse problem. However, the structures of interest are normally restricted to small changes from some nominal structure. Perturbation theories have been used to efficiently calculate the effects of small changes on the performance of photonic crystals. In this paper, we apply these perturbation techniques to the optical scatterometry problem and demonstrate a calculation of the change in the scattered signal due to edge roughness from an array of holes in a dielectric.

For many years, lithographic resolution has been the main obstacle for keeping the pace of transistor densification to meet Moore's Law. The industry standard lithographic wavelength has evolved many times, from G-line to I-line, deep ultraviolet (DUV) based on KrF, and 193nm based on ArF. At each of these steps, new photoresist materials have been used. For the 45nm node and beyond, new lithography techniques are being considered, including immersion ArF lithography and extreme ultraviolet (EUV) lithography. As in the past, these techniques will use new types of photoresists with the capability of printing 45nm node (and beyond) feature widths and pitches. This paper will show results of an evaluation of the critical dimension-scanning electron microscopy (CD-SEM)-based metrology capabilities and limitations for the 193nm immersion and EUV lithography techniques that are suggested in the International Technology Roadmap for Semiconductors. In this study, we will print wafers with these emerging technologies and evaluate the performance of SEM-based metrology on these features. We will conclude with preliminary findings on the readiness of SEM metrology for these new challenges.

Process variation on lot-to-lot and wafer-to-wafer level has been well addressed using R2R control in advanced process control, however, to tackle the ever increasing die-to-die (i.e. across-wafer) level process variation at the 65nm technology node and beyond, the process control must be extended into finer domain: across-wafer level. A novel model based process control approach [2] was proposed to reduce the critical dimension (CD) variation on across-wafer level. The central idea of the proposed approach is to compensate for upstream and downstream systematic CD variation by adjusting the across-wafer Post-Exposure Bake (PEB) temperature profile of a multi-zone bake plate. A temperature-to-offset model relating the PEB temperature profile of multi-zone bake plate to its heater zone offsets was constructed experimentally using wireless temperature sensors from OnWafer Technologies. The baseline post-etch CD signature and plasma etch bias signature were extracted to characterize the lithography and etch processes. And a post-etch CD variation reduction of 40% was realized in the verification experiment, which validated the efficacy of the proposed approach.

Decreasing of node size significantly increases requirement to overlay precision. Complex structure of target demands using of compound structures of overlay mark, which usually contain features with acute sidewall angles, coated by several layers. In this paper the possibility and limitations of image-based overlay with compound structures with overlay mark and coating layers are analyzed in detail. Dependence of overlay signal shape on overlay offset is considered. Structures with asymmetric sidewall angle, non-uniform thicknesses of layers and curved shape of layer borders are examined. Influence of thickness variation, difference between left and right sidewall angles of asymmetric shape and curvature of layer borders are investigated. For the simulation of such complex structures of overlay marks, our in-house simulator based on rigorous coupled-wave analysis (RCWA) module is used. Maximum allowed values of these parameters are studied in order to determine the limitations of image-based overlay. Results of this consideration can be used for improvement of overlay precision and elaboration of optimal overlay strategy in conditions of node shrinking in the semiconductor industry.

Adoption of immersion technology to push printing resolution with existing wavelength (193nm) brings to many concerns about defect controls on lithography process. Along with aggressive design rule shrinkage k1 factor of lithography process is close to 0.3 and this low k1 factor process results in very tight process window. Narrow process window easily induces various types of pattern failure with lithography process variation. Therefore requirements of sensitive defect detection on lithography step are grown with the adoption of immersion and low k1 regime processing. Similar to lithography resolution enhancement with shorter wavelength the inspection tool also is required to move forward to shorter wavelength to improve defect sensitivity through resolution improvement and scattering cross section increase. Therefore the main wavelength regime on high end defect inspection system is already shifted to DUV. In this paper, we would like to report improvement of defect detection sensitivity on lithography process inspection through step by step trace of the defect formation and shape. Throughout the process flows till final etch and cleaning process from lithography the SEM non-visible defects or buried defects on lithography step are turned into line open or line thinning which are killer defects and has low defect signal on cleaning step. Also the benefits of DUV inspection system on lithography layer application is discussed through wafer noise suppression from Anti Reflection Coating (ARC) and larger defect signal from effective defect size increasing.

Electron beam inspection (EBI) of wafers has been widely shown to be a powerful tool for random defectivity on wafers, particularly for sub-surface electrical defects that cannot be seen by optical tools. Some types of systematic defects, such as subtle under- or over-etch of contacts, can be difficult to catch using traditional die-die or cell-cell comparison because all contacts may be similarly affected. In this paper we investigated methods for catching systematic process defects using EBI. We used a design of experiment where different dies on the same wafer were etched using a total of 4 different etch parameters. The dies were selected by using multiple resist coat, pattern, and etch steps at a single contact layer. A total of 3 wafers were given the same process treatment. Following the etch steps, one wafer continued through the fabrication process to final test, one wafer was inspected using an eS31 electron beam wafer inspection tool, while the third wafer was held in reserve. The initial inspection did not show any significant difference in defectivity between the dies, although final bit test did show pseudo-systematic defectivity depending on etch process condition. The wafer was then inspected on an eS32 tool using a special e-beam preconditioning step to enhance the contrast of subtle under-etched contacts. In this case, we were able to pick out a defectivity corresponding the etch condition of each die. The in-process defectivity found by the electron beam inspection tool matched well with the end-of-line bit failure map. In summary, subtle systematic etch process variations were detected by varying the etch process parameters across a single wafer, and tuning the electron beam inspection sensitivity to maximize contrast for subtle etch variations. Such techniques can be a powerful tool for optimization of etch process recipes to minimize wafer electrical defectivity.

Immersion lithography offers great benefit for advanced technology nodes but at the same time poses a great challenge. Along with hyper NA values, which increase the scanner resolution, new types of imaging process related defects emerge. These new defects are related to water, top coating, resist and BARC in the litho process. Root cause analysis of the so-called wet defects (immersion) versus the so-called dry defects (non immersion-related) becomes crucial in any immersion lithography related defect reduction program. Manual and eventually automated classification of defects can be used to analyze the data and monitor baselines. Furthermore, a robust Automatic Defect Classification (ADC) increases productivity and decreases the wafer cycle time. This article outlines a methodological approach for wet and dry defect classification that employs rule-based ADC and enables the generation of an immersion induced defect library for fast baseline improvement and excursion monitoring. The work described in this article has been performed at ASML using Applied Materials' SEMVision G3 FIB automated defect review and analysis tool.

As the semiconductor design rules shrink down, process margins are getting narrower, and thus, it is getting more important than ever to monitor pattern profile and detect minor structure variation. A breakthrough technology has been introduced as a solution to this concern. The new technology converts the fluctuation of polarization ingredient, which is caused by form birefringence, into light intensity variations as an optical image. This technology, which is called Pattern Edge Roughness (PER) inspection mode, is proved to be effective for 55nm production process. We also studied the possibility of the macro inspection method for half pitch 32nm technology node through FDTD method.

A new die-to-database high-resolution reticle defect inspection system has been developed for the 45nm logic node and extendable to the 32nm node (also the comparable memory nodes). These nodes will use predominantly 193nm immersion lithography although EUV may also be used. According to recent surveys, the predominant reticle types for the 45nm node are 6% simple tri-tone and COG. Other advanced reticle types may also be used for these nodes including: dark field alternating, Mask Enhancer, complex tri-tone, high transmission, CPL, EUV, etc. Finally, aggressive model based OPC will typically be used which will include many small structures such as jogs, serifs, and SRAF (sub-resolution assist features) with accompanying very small gaps between adjacent structures. The current generation of inspection systems is inadequate to meet these requirements. The architecture and performance of a new die-to-database inspection system is described. This new system is designed to inspect the aforementioned reticle types in die-to-database and die-to-die modes. Recent results from internal testing of the prototype systems are shown. The results include standard programmed defect test reticles and advanced 45nm and 32nm node reticles from industry sources. The results show high sensitivity and low false detections being achieved.

As cell size of advanced memory is approaching to around 50nm hence the size of defect is required to be detected is less than 30nm. In the array area best combinations of the inspection tool that can be achieved the maximum sensitivity through optics based are short wavelength, small pixel and collection from off-axis perspectives when the noise from pattern can be blocked. To remove the pattern noise efficiently and having enough defect signal to detector laser illumination is better approach than broadband lamp where lobe formation is not well defined and light intensity is not high enough. UVision^TM 3D channel which is off-axis collection of light from normal illumination was evaluated on array area of advanced memory design rules. Below 100nm node design rule 3D channel can successfully suppress the Customized Light Collection (CLC) lobes which are diffraction lobes from memory array pattern. In this paper we would like to report significant improvement of defect detection sensitivity through optimizing CLC lobe mask. It was developed to maximize the defect collection area and angle and showed improvements on defect detection through SNR and signal enhancement. Because of CLC lobe suppression's inverse relationship with device design rule the results show that the smaller design rule gives better defect signal detection capability.

Accurate placement of the edge exclusion region is critical to maintaining edge die yield. Variation in film overlay in the edge exclusion region can lead to yield-limiting defects. Edge Bead Removal (EBR) metrology or Edge Exclusion Width (EEW) metrology describes a topside surface measurement of the wafer edge exclusion region relative to the wafer center and the wafer edge. This measurement is typically made at several points along the wafer's edge and often ranges between 0mm and 6 mm in width. In photolithography, EBR metrology data can be used to determine the repeatability of wafer alignment and the accuracy of EBR dispensing nozzles on the coat track. In addition to EBR/EEW metrology, wafer edge inspection provides an indirect method to control the EBR process by detecting jaggedness of the EBR profile, scalloping, splashing, and other EBR line defects. Improper EBR can also create residuals on other edge surfaces that can lead to cross-contamination of wafers and handling equipment. This paper describes a combined EBR/EEW metrology and wafer edge inspection method that can quickly detect EBR-related defects and characterize the quality of the EBR process. This data reveals the relationship between EBR-related defects and the quality of the EBR process, and can be used to make necessary adjustments to the coat track - and as a basis for wafer rework decisions. Proper tuning and monitoring of the EBR/EEW process allows for the eventual elimination of an entire class of EBR-related defects, thus significantly increasing edge die yield.

Advances in lithography create a unique challenge for process window control with defects inspection tools. As the technology moves towards smaller line widths and more complicated structures, the sensitivity requirements for some process defects become higher, such as defocus and dose defects at 50nm or lower technology nodes. Currently automated macro inspection tools are used to detect a wide range of macro defects in the litho area, such as coating defects, particles, scratches, as well as the process defects. Most tools, however, cannot satisfy the new sensitivity requirements for the process defects while maintaining their current inspection capability for other defects. Rudolph Technologies approaches this challenge by integrating a unique polarization-imaging configuration, which enhances detection of defocus and dose defects without sacrificing the existing capability to detect other types of macro defects. The improved inspection system has demonstrated high sensitivity for defocus and dose defects on production wafers at multiple process nodes at high throughput.

Critical dimension (CD) is one the most critical variable in the lithography process with the most direct impact on the device speed and performance of integrated circuit. The development rate can have an impact on the CD uniformity from wafer-to-wafer and within-wafer. Conventional approaches to controlling this process include monitoring the end-point of the develop process and adjusting the development time or concentration from wafer-to-wafer or run-to-run. This paper presents an innovative approach to control the development rate in real-time by monitoring the photoresist thickness. Our approach uses an array of spectrometers positioned above a programmable bakeplate to monitor the resist thickness. The develop process and post-development bake process is integrated into one equipment. The resist thickness can be extracted from the spectrometers data using standard optimization algorithms. With these in-situ measurements, the temperature profile of the bakeplate is controlled in real-time by manipulating the heater power distribution using a control algorithm. We have experimentally obtained a repeatable improvement in controlling the end-point of the develop process from wafer-to-wafer and within wafer.

A general predictive method based on Canonical Correlation Analysis (CCA) is developed to identify globally correlated process modes that are responsible for the spatial variability in deep nanoscale semiconductor manufacturing. This multivariate statistical method overcomes the limitations of ordinary multiple linear regression technique by introducing canonical variates with certain properties which allow us to construct a transfer matrix to relate the predictand vector to the predictor vector directly. Principal Component Analysis (PCA), another multivariate statistical technique, is introduced to find the orthogonal modes that explain the larger fraction of the total process variations. We also discuss the constraint of sample number in CCA and propose using the leading principal components (PCAs) to replace the original raw data in correlation analysis.

With the recent introduction of immersion lithography, optical systems with numerical aperture (NA) reaching 1.0 or larger can be realized. Various Resolution Enhancement Techniques (RET) such as various phase shift mask approaches have been used to push even further the resolution limit by reducing k₁ scaling factor, including Double Patterning Technology. However, with the improved resolution by Hyper-NA and Low-k₁, lithographers face the problem of decreasing Depth of Focus and in turn reduced process latitude. Throughout the industry, Process Window has been widely used as an analytical tool to evaluate process latitude for a given design feature size; therefore, the ability to accurately and efficiently derive a Process Window within which a process can run on target and in control is fundamental to Low-k₁ lithography. Accuracy of Process Window derivation is based on the ability to accurately measure and model the physical dimension of the design feature and how it changes in response to changes in process parameters. In the case of lithography, the Process Window of a desired critical dimension target is bounded by changes in exposure energy and defocus. To be able to accurately measure the physical dimension of the design feature remains a big challenge for metrologists especially in the presence of other process noise. In this work, it is shown that the precision of PW measurement can be enhanced by using CD-ACD (Average CD) function to measure a FEM (Focus-Exposure matrix) wafer. ACD is a function, which simultaneously measures several points, thus providing higher precision measurement in comparison to the conventional single point measurement. As seen in this work, by using ACD measurements to derive the Process Window, there is a significantly improvement in the stability of the derived Process Window. Also reported is the MPPC (Multiple Parameters Profile Characterization) ^*1), a function which provides the ability to extract pattern shape information from a measured e-beam signal. This function together with the ACD function enables PW measurement with high precision, which also takes into account the actual pattern shape. PW derived from conventionally measured data was compared with PW derived from ACD and MPPC measurement and we were able to demonstrate an improvement of more than 30% in precision of PW determination.

Scatterometry is currently being used in lithography production as an inline metrology tool to monitor wafer processing and detect excursions. One well-documented excursion is the process variation caused by differences in resist batches. This paper describes the use of Tokyo Electron Limited's integrated Optical Digital Profilometry (iODP^TM) scatterometry system to detect process variations caused by resist batch changes. This system was able to detect a significant shift in resist sidewall angle (SWA) on an incoming resist batch that was undetected by the primary metrology in use at the time, a scanning electron microscope (CD-SEM). This SWA shift correlated to an undesirable shift in post-etch CD created by the new resist batch. Experiments performed in conjunction with the resist supplier confirmed that the normal batch-to-batch variation of a key resist component was enough to produce a change in SWA after processing. This validation led to quality improvement controls by the resist vendor and Qimonda and resulted in the use of iODP as the primary metrology for this process.

Optimal lithographic process control involves a closely coupled combination of test wafer and product wafer characterization. It has been shown in previous work that MPX (Monitor Photo Excursion) optical technology for line-end-shortening metrology of focus and dose provides reliable and low cost product monitor solution. In this work we apply MPX technology to litho cell monitor and control on test wafers. Focus-exposure matrix (FEM) wafers are measured and analyzed automatically on a routine basis. Process window parameters are tracked over time by scanner, including spatial analysis of results across the scanner field such as tilt and curvature. Improvements in litho cell control are discussed.

We have developed a simple and cost-effective data sharing system between fabs for lithography advanced process control (APC). Lithography APC requires process flow, inter-layer information, history information, mask information and so on. So, inter-APC data sharing system has become necessary when lots are to be processed in multiple fabs (usually two fabs). The development cost and maintenance cost also have to be taken into account. The system handles minimum information necessary to make trend prediction for the lots. Three types of data have to be shared for precise trend prediction. First one is device information of the lots, e.g., process flow of the device and inter-layer information. Second one is mask information from mask suppliers, e.g., pattern characteristics and pattern widths. Last one is history data of the lots. Device information is electronic file and easy to handle. The electronic file is common between APCs and uploaded into the database. As for mask information sharing, mask information described in common format is obtained via Wide Area Network (WAN) from mask-vender will be stored in the mask-information data server. This information is periodically transferred to one specific lithography-APC server and compiled into the database. This lithography-APC server periodically delivers the mask-information to every other lithography-APC server. Process-history data sharing system mainly consists of function of delivering process-history data. In shipping production lots to another fab, the product-related process-history data is delivered by the lithography-APC server from the shipping site. We have confirmed the function and effectiveness of data sharing systems.

We analyzed substrate current signal of flash memory with floating and control gates using EB-Scope for the measurement of bottom CD. We showed that the signals come from capacitance structure of the floating and control gates. From this analysis, we showed we can get the information of electrical characteristics of floating and control gates such as capacitance, resistance and time constant as well as the bottom CD of flash memory with floating and control gates. This technique form this analysis can contribute yield enhancement in flash memory manufacturing process by in-situ monitoring.

Simulation and experimental study results are reported to solve align/overlay problem in dark hard mask process in lithography. For simulation part, an in-house simulator, which is based on rigorous coupled wave analysis and Fourier optics method of high NA imaging, is used. According to the simulation and experiment study, image quality of alignment and overlay marks can be optimized by choosing hard mask and sub-film thickness carefully for a given process condition. In addition, it is important to keep the specification of film thickness uniformity within a certain limit. Simulation results are confirmed by experiment using the state of art memory process in Samsung semiconductor R&D facility.

We have demonstrated the feasibility of measuring overlay using small targets with an optical imaging tool has in earlier papers. For 3&mgr;m or smaller targets, overlay shifts introduce asymmetry into the target image. The image asymmetry is proportional to the overlay shift and so this effect can be used to measure the overlay. We have used wafers built using production 45nm and 55nm processes to test these targets in production control situations. Targets with different programmed offsets allow the necessary conversion between image asymmetry and overlay shift to be determined empirically on the wafer under test. Measurements made using standard 25&mgr;m bar-in-bar targets and 3&mgr;m in-chip targets agree to within 10nm (3&sgr;). By processing results from five or more fields the agreement is improved to 5nm, a level which is limited by a mechanism other than random errors and which is similar to differences between different styles of bar-in-bar targets. Analysis of data from both in-chip and bar-in-bar targets shows similar patterns of overlay variation within the device area. The pattern of overlay variation does not fit mathematical models of overlay as a function of location. The total change of overlay within the field is 10nm, exceeds the overlay budget for critical layers at 45nm design rules. This uncontrolled in-field variation in overlay must be reduced and ideally eliminated if process control is to be achieved. A first step in controlling these errors is having an ability to measure them, and our data shows that this is possible with targets no larger than 3&mgr;m in total size.

Overlay control becomes more crucial for wafer processing in thin film head (TFH) industry with continuous shrinkage in Critical Dimension (CD) in order to achieve higher data storage capacity. High topographic feature and thick transparent oxide between two overlay layers are unique challenges for TFH overlay measurement. It is important to know if overlay target represents the true overlay and its effect on overlay control. In this work, three overlay marks, Box-in-Box (BiB), Frame-in-Frame (FiF) and KLA-Tencor Advanced Imaging Metrology (AIM), were evaluated under different process conditions. The performance study of the overlay marks included following tests: overlay precision, Tool Induced Shift (TIS) variability and Total Measurement Uncertainty (TMU); effect of photo resist thickness and transparent oxide spacing between two overlay layers; overlay mark fidelity (OMF) from array test; analysis of stepper correctable terms residuals. It was found that AIM marks provided better metrology tool performance than BiB and FiF in terms of precision, TIS variability and TMU. It was also found that precision and TIS variability were sensitive to photo resist thickness and oxide thickness. Smaller overlay residual error was achieved using AIM target and OMF could be improved too.

Optical overlay metrology is thought to face the challenges in precision improvement with edge-determination based algorithm because the design rule is gradually decreasing in advanced semiconductor process. We develop a novel algorithm for determining the overlay error of grating structures with an optical bright-field imaging tool. By evaluating the intensity variation of the different acquired images through the analysis of the optical images obtained at different defocus positions, the analysis curves of the focus measure versus the overlay error experimentally demonstrate the nanometer sensitivity with the overlay of the grating structure. When plenty of images of different target pattern captured with image sensor at different amounts of defocus position, the image intensity variation in each image can be calculated by focus criteria. In our application, the gradient energy is the best metric of the image within the grating area because it discriminates the main and side lobe local maximum more sharply that is a key phenomenon in our algorithm application. Empirical models were developed to fit the experiment results of image intensity variation versus overlay error. The experimental data show that the variations of the focus measure has nano-scale sensitivity to the overlay of the grating structure, so that it can be used to determine the overlay error by implementing the algorithm. Thus, the through-focus method has potential application in overlay metrology for the process control in future semiconductor manufacturing.

ArF immersion lithography and RETs (Resolution Enhancement Technology) are the most promising technology for sub 60nm patterning. As the device size shrinks, overlay accuracy has become more important due to small overlap margin between layers. Overlay performance of immersion process is affected by thermal effect due to water evaporation, so it shows worse performance than dry process and CD variation in DPT (Double Patterning Technology) process is affected by overlay performance. So improvement of overlay accuracy became hot issue in realization of future lithography technology, especially immersion process and double patterning process. Current status of lithography tool shows 10 ~ 12nm (3sigma) overlay control in front-end process, but this overlay performance is not sufficient for future technology. In this paper, we investigated the causes of overlay variation and tried to improve overlay accuracy in front-end process of 60nm DRAM device. Therefore, the results in this study can be implemented to new technology such as immersion and double patterning. First, overlay residual error factor is classified into two types, one is the equipment error factor and the other is process error factor. Equipment error can be divided into SCMV (Single Chuck Mean Variation) by stage accuracy variation, chuck to chuck mean and correction factor variation by using twin chuck etc. And process error can be divided into alignment signal variation by chuck defocus (stage particle by contamination), increase of overlay residual by material deposition, alignment key height variation by etch loading effect, overlay vernier attack by CMP (Chemical Mechanical Polishing) process etc. We analyzed causes of these overlay error factor and we applied new system and process to improve these overlay error factor. In conclusion, we were able to find where overlay error comes from and how to improve overlay accuracy in 60nm device, and we got good overlay performance using new alignment system and process optimization.

Though immersion lithography is on the verge of starting mass-production, demerit in overlay controllability by immersion is thought as one of last huddle for that. The first issue in immersion tool has not been matured compared to dry tool. As design rule is getting smaller, overlay specification is also changing the same way. But immersion tool is not ready to meet this tighter overlay specification. The second issue is regarding the material which is used for immersion process: top coat and water. Process details of material are needed to be verified thoroughly about how each parameter affect on alignment and overlay respectively. In this paper, we made a split experiment about machine parameter and investigated top coat effect on overlay. To improve overlay performance of immersion, we analyzed machine parameters: scan-speed, settling time, UPW(Ultra Pure Water) flow etc. And we made an experiment about how the effect of top coat is appeared on overlay through simulation and experiment. In the experiments, we used ASML 1400i scanner. Resolution improvement of immersion tool has been proved by lots of papers, but it is need to be verified of overlay controllability that getting tighter. Continuously, we believe that most efforts are to be focused on overlay control issue.

Layer to layer alignment in optical lithography is controlled by feedback of scanner correctibles provided by analysis of in-line overlay metrology data from product wafers. There is mounting evidence that the "high order" field dependence, i.e. the components which contribute to residuals in a linear model of the overlay across the scanner field will likely need to be measured in production scenarios at the 45 and 32 nm half pitch nodes. This is in particular true in immersion lithography where thermal issues are likely to impact intrafield overlay and double pitch patterning scenarios where the high order reticle feature placement error contribution to the in-die overlay is doubled. Production monitoring of in-field overlay must be achieved without compromise of metrology performance in order to enable sample plans with viable cost of ownership models. In this publication we will show new results of in-die metrology, which indicate that metrology performance comparable with standard scribeline metrology required for the 45 nm node is achievable with significantly reduced target size. Results from dry versus immersion on poly to active 45 nm design rule immersion lithography process layers indicate that a significant reduction in model residuals can be achieved when HO intrafield overlay models are enabled.

In this paper we present one application of our new Advanced Lithography Parameters Extraction (ALPE) system in the lithography process window analysis. Compared with traditional DOF/EL based process window analysis or Monte Carlo approaches with pre-assumed process variations, our new approach uses real-life process variations (exposure, focus, and even PEB temperature, etc. if needed) collected by the new ALPE system. Different from pre-assumed process variations and independently measured process variations, all these process variations are directly correlated with inline CD variations, so we call them real-life process variations. Based on these real-life process variations, the estimation of final CD uniformity will be more accurate and objective. Comparing estimated CD uniformity of new process with CD uniformity of baseline process, it is possible for us to tell which process is better from statistical point of view.

As critical dimensions shrink to fit advanced process generation requirements, line width roughness (LWR) has become more and more important. As design rules for semiconductor devices shrink, the line width roughness approaches the CD of the line itself. This leads to poor device performance or even device failure. Thus, an accurate process monitor for LWR is required. CD-SEM measurements for LWR require a reference to verify the accuracy. TEM has traditionally played this role. However, its destructive nature, the errors induced by sample preparation, the limited data output and long turnaround time make routine TEM measurement undesirable. CD-AFM is a non-destructive technique that is able to generate highly accurate three-dimensional profiles of a sample surface over tens of microns in the X and Y directions with sub-nanometer resolution. In this paper we present results that show strong correlation between CD-SEM, TEM and inline CD-AFM based on measurements of an OPC grating. Based on these results, CD-AFM has successfully replaced TEM as the reference tool of choice for the R&D stage of a 45nm generation process. To improve this situation, we have successfully adopted in-line X3D AFM to replace FA TEM as the verification tool in the R&D stage of a 45nm generation process.

With the shrinking of device sizes, the issue of controlling gate critical dimension (CD) is becoming increasingly important. In particular, the ability to find systematic defects and use that information in the design, optical proximity correction (OPC), and mask creation phases is becoming critical to improving circuit yield. Current critical dimension electron scanning microscopes (CD-SEMs) and macro inspection systems, however, fail to address this area in a practically usable manner - with CD-SEMs limited by their low throughput, and macro inspection systems limited by their low resolution. The NGR2100 die-to-database verification system introduces high-throughput, wide field of view (FOV) electron beam scanning technology to allow for mass gate measurement and analysis. Using the collected data combined with layout data and statistical analysis, the NGR2100 system categorizes and outputs the systematic CD errors existing on a wafer, which can be fed back to the design, OPC, and mask creation phases for true design-for-manufacturing (DFM) realization. This paper provides an overview of the NGR2100, the process involved for gate CD error detection, and presents an actual case in which the NGR2100 was used to collect and analyze data for a memory device.

Requirements for increasingly integrated metrology solutions continue to drive applications that incorporate process characterization tools, as well as the ability to improve metrology production capability and cycle time, with a single application. All of the most critical device layers today, along with even non-critical layers, now require optical proximity correction (OPC), which must be rigorously modeled and calibrated as part of process development and extensively verified once new product reticles are released using critical dimension-scanning electron microscopy (CD-SEM) tools. Automatic setup of complex recipes is one of the major trends in CD-SEM applications, which is adding much value to CD-SEM metrology. In addition, as integrated circuit dimensions continue to shrink, local line width variation influences the statistical confidence of a measured CD's representation of the process. A feature, called "Average CD (ACD)," measures multiple targets within the field of view (FOV). ACD allows not only measurements of a single data point representing one discrete feature, but also sampling of the mean and variance of the process. These two applications, automatic recipe creation and ACD, are combined in the second version of the DesignGauge software, which is available for the latest-generation Hitachi S-9380II CD-SEMs. DesignGauge V2 is not only capable of offline recipe creation and CD-SEM control, but it also has the ability to directly transfer design-based recipes into standard CD-SEM recipes. These recipes can be used for OPC model-building and verification as with previous DesignGauge applications. The software also provides design template-based recipe setup for production layer recipes, which yields much needed improvement to production tool utilization, as production recipes can thus be written offline for new products, improving first silicon cycle time, reducing engineering time required to generate recipes, and improving CD-SEM utilization. Another benefit of the application is an improvement in recipe robustness over conventional direct image-based pattern recognition. This work will show an extensive evaluation of DesignGauge V2, including rigorous tests of navigation, pattern recognition success rates, SEM image placement, throughput of recipe creation, and recipe execution. The impact of ACD will also be evaluated.

The whole process of stochastic lithography simulation combined with an electron-beam simulation module, could be useful in the validation of design rules taking into account fine details such as line-edge roughness, and for simulating the layout before actual fabrication for design inconsistencies. Material and process parameters can no more be considered of second order importance in high-density designs. Line-width roughness quantification should accompany CD measurements since it could be a large fraction of the total CD budget. An example of the effects of exposure, material and processes on layouts are presented in this work using a combination of electron beam simulation for the exposure part, stochastic simulations for the modeling of resist film, the post-exposure bake, resist dissolution, and a simple analytic model for resist etching. Particular examples of line-width roughness and critical dimension non-uniformity due to, material, and process effects on the gate of a standard CMOS inverter layout are presented.

Contact hole integrity is an important metric for IC manufacturers, which is reflected in tight ellipticity control as part of the lithography tool qualifications. The current ellipticity measurement methodology is very sensitive to random process variations of the contact hole shape. Determining ellipticity in a systematic manner poses a challenge on qualification productivity, as acquiring more data for statistical validity leads to unacceptably long measurement times. The introduction of the so-called MacroCD Vector measurement enables a single shot large sampling of contact holes, including vector calculation and averaging of all individual contact ellipticity results within the MacroCD measurement array. Based on these enhanced measurement features, it is shown that contact hole ellipticity can be determined with much higher accuracy while local, mostly process induced variations can be characterized simultaneously. This opens possibilities to study correlation between ellipticity and possible root causes in the litho process module.

Reducing metrology fleet variation through improved matching techniques is a never-ending journey. In exceeding vendor specifications, CD-SEM matching of < 1nm were demonstrated between two tools. Details and methods are discussed, including FOV Factor matching, automated SEM tuning, new qual sampling plans (termed 5x5x5), and a 1st difference monitoring plan for tool drift. The results obtained in this paper were collected over a year and included data before and after maintenance events (ie. Tip changes.)

Visible light angular scatterometry is investigated for sub-100 nm line metrology. Measurement sensitivities to small variations in line dimensions are examined and some observations are made on the measurement conditions leading to improved sensitivities even for 20 nm CD. Experimental results with good accuracies are also shown for red light angular measurements of PMMA gratings made by e-beam lithography and nanoimprint lithography. The theoretical and experimental studies show high sensitivity and accuracy in characterization of the geometry and dimensions of nano-lines, particularly in measuring the polymer residue thickness of nanoimprinted polymer gratings and the undercut line profiles resulting from e-beam lithography. The results promote using this low cost and non-invasive technique to examine and control some underlying lithographic processes in nanofabrication.

Sub-50 nm half pitch critical dimension metrology of resist lines by a fast goniometric scatterometry technique in the visible range has been investigated. The goniometric optical instrumentation allows illumination and reflection of patterned objects from almost all angles of view (0°/80° polar angles, and 0°/360° azimuthal angles) simultaneously. Applied to scatterometry, this tomography-like technique ensures a robust lines profiles reconstruction. Sensitivity and correlation analysis show that this technique exhibits at least equal performances compared to ellipsometry. Since the technique uses a single wavelength, no spurious assumptions about the refractive index of the materials illuminated is introduced is the modeling process. So the technique is believed to be more robust than ellipsometry. We present a demonstration of CD measurement with this technique on 30 nm CD resist lines with various pitches. The results are compared to CDSEM.

As device critical dimensions (CD) decrease, they approach the limits of standard metrology techniques and measuring features smaller than 20 nm represents a serious challenge. Within the framework of the 32 nm program at IMEC, a reliable and accurate approach to small feature metrology is required. We describe here a methodology aimed at measuring features down to 10nm by means of scatterometry. The results are compared to calibrated CDSEM measurements [1]. The active fins of a Multi Gate Field Effect Transistors (MuGFET) was measured across wafer and across batch. Scribe to cell correlation, wafer fingerprint, 3D profile, oxide thickness were also investigated. In particular, 3D profile information was compared to TEM. Our approach produced very consistent results for all measurement techniques (scatterometry, CDSEM and TEM) and it is now fully integrated in the IMEC production line to monitor the MuGFET platform.

In this paper, one of the major contributions to the OCD metrology error, resulting from within-wafer variation of the refractive index/extinction coefficient (n/k) of the substrate, is identified and quantified. To meet the required metrology accuracy for the 65-nm node and beyond, it is suggested that n/k should be floating when performing the regression for OCD modeling. A feasible way of performing such regression is proposed and verified. As shown in the presented example, the measured CDU (3σ) with n/k fixed and n/k floating is 1.94 nm and 1.42 nm, respectively. That is, the metrology error of CDU committed by assuming n/k fixed is more than 35% of the total CDU.

A new application for ultra-fast and repeatable in-die determination of CD structures at the ~1 &mgr;m length scale using BPR®/BPE® (Beam Profile Reflectometry/Ellipsometry) technologies on an Opti-Probe OP9000 series system, is presented and summarized. Two structures were measured and analyzed, including a poly-silicon CD standard and an advanced poly-silicon recessed structure relevant to advanced memory devices. A focused beam spot (~1 &mgr;m) and "fast BPR" data acquisition capability (~17 ms) were utilized to perform high-resolution scans across wafer and within single die regions. Rotating Compensator Spectroscopic Ellipsometry (RCSE®) signals were also used to independently determine and compare to BPR results from data collected over larger areas (~15 &mgr;m). The BPR/BPE and SE results for line CD were found to have high correlation. Further, model regression for SE data coupled with an artificial neural network model and fast BPR were utilized to measure and calculate 10,000 points across a 1 mm² area in a matter of minutes. Overall, the results were found to be repeatable and correlated well to CD-SEM analysis.

As pattern size is shrinking, required mask CD specification is tighter and its effect on wafer patterning is more severe. Recent study showed that the effect of mask local CD variation of mask on wafer is much smaller than that of global CD variation.[1] To enhance the device performance, wafer CD uniformity should be enhanced and controlled by mask global CD uniformity. Mask global CD uniformity usually can be enhanced by mask process and optimal fogging effect correction. To enhance the mask global CD uniformity on mask, resist process and FEC (Fogging Effect Correction), reliable CD measurement tool and methods are necessary. Recently, group CD using OCD(Spectroscopic Ellipsometer) or AIMS(Aerial Image Measurement and Simulation) or polynomial fitting method is introduced to represent global CD variation on mask.[2][3][4] These methods are removing local CD variation on mask. The local CD variation will be remained as residual CD after approximation. In this paper, local CD variation of mask and wafer is evaluated and 2 kinds of methods are used to measure CD on mask and wafer, and the correlation of global CD of mask and field CD of wafer are evaluated. And the repeatability of field to field CD uniformity of wafer is evaluated to correct the fields CD uniformity of wafer by controlling the selective changing of transmittance of mask or to feed back to mask process. Higher correlation between fields of wafer, more accurate correction can be possible.

Due to the discussed introduction of double patterning techniques the overlay and registration metrology requirements in advanced lithography will drastically increase so that reference metrology tools need to be developed further to be able to follow the resulting tightening of the specifications. Therefore, the PTB further develops the Nanometer Comparator, a 1D vacuum comparator, which already has proven its performance during the measurements of incremental encoders. The implementation of the angular control loops decreases the angle deviations of the measurement carriages down to 0.15 μrad, which led to a reduction of the contribution of the Abbe errors to the measurement uncertainty to insignificant levels. Changes in the illumination and alignment of its optical microscope resulted in an improved defocus behaviour, which consecutively reduced the reproducibility (1 σ) of measurements of high quality scales in the order of 1 nm. Therefore an expanded measurement uncertainty of below 5 nm has been achieved.

Advanced lithography became possible using breakthrough technologies, including phase shift masks, advanced illumination modes, aggressive OPC patterns and 193nm immersion optics. The Applied Materials Aera193 system, an at-wavelength aerial reticle inspection tool, was introduced for the 90-65nm technology nodes. In the era of immersion lithography and 55-45nm nodes, there is an increasing demand for Aerial inspection under immersion conditions. To face this demand, the Aera193i was upgraded with expanded illumination and collection optics to support up to 1.4 NA immersion conditions. Here, we describe novel Aerial inspection results under immersion conditions. We studied the detection of a variety of defect types on 55nm node phase shift masks for immersion lithography. We found that the immersion-emulation inspection was able to demonstrate a good detection line, with extremely low false alarms and nuisance call rate. We also studied the relationship between Aerial defect detection and actual defect printability by printing the same mask on wafer. We found good correlation between Aera193i detection line and actual defect printability. We also address the polarization effects under immersion NA. We demonstrate that under polarized stepper illumination the polarization effects on the image are negligible, while aerial imaging reliably emulates mask pattern polarization effects.

A useful extension of the optical mask pattern placement metrology is the measurement of critical dimensions (CD), exploiting the outstanding mechanical resolution and stability of a corresponding mask metrology machine. In particular the CD measurement on phase-shift masks (PSMs) poses a challenge on the optical measurement method. The paper presents measurements and the corresponding computational modeling of the setup with respect to illumination beam path (reflection, transmission), PSM properties and measurement optics for a dedicated edge detection method. Variables have been the focus variation of the edge position and the critical dimension of the pattern. Based on the modeling outcome the alignment and the illumination have been improved and verification measurements have been performed on various machines of the type Vistec LMS IPRO3. The paper presents the measurements, the modeling and the comparison to the practical measurement results for original and improved setup, showing the achievement of the envisaged 2-nm repeatability.

We fabricated a grating reference with EB cell projection lithography and silicon dry etching, instead of conventional 240-nm pitch grating references fabricated with laser-interferometer lithography and anisotropic chemical wet etching. We developed a novel 100-nm pitch grating reference based on our grating reference for critical dimension-scanning electron microscope (CD-SEM) calibration. We obtained high-contrast secondary electron signals and uniform grating patterns within 3 nm in 3σ during CD-SEM measurements because we eliminated the proximity effect of EB exposure. The reference has an array of 100-nm grating cells in the x-and y-directions. Each cell consists of a 100-nm grating unit, an X-Y coordinate number in the array, and an addressing mark for the CD-SEM to identify the calibration position. These positional identification marks enable accurate calibration by specifying the location of the grating and the number of calibrations. Also, the pitch size of the reference grating can be accurately calibrated by optical diffraction angle measurements with a deep ultraviolet (DUV) laser.

As semiconductor and data storage industries apply Critical Dimension Atomic Force Microscopy (CD-AFM) for their metrology needs in research and production, (1) measurement accuracy/repeatability and (2) measurement throughput are the major criteria for acceptance. However, these two requirements are usually contradictory for a metrology instrument. For example, a scatterometer can take a snapshot of a wafer in seconds, but such indirect CD measurements are biased by the availability of library models and uncertainty of computer simulations. Transmission Electron Microscopy (TEM) provides an atomic-scale resolution that is traceable back to the lattice structure of atoms, yet the cross-section data is highly localized and can take days or weeks to acquire. In the case of CD-AFM, since the scanning probe physically interacts with the structure of interest at a close proximity, the determination of sample morphology comes from direct measurements. Therefore, the measurement uncertainty can be attributed to: (1) AFM probe tip shapes and (2) system control and scan algorithms. For the former, past efforts have been mainly focused on improving metrology accuracy and repeatability by reducing the dimensional uncertainty of a tip shape. This approach includes characterizing the probe tip shape periodically. Inevitably, such tip shape calibration procedure takes time (approximately 5 min) and burdens production throughput. In this paper, we introduce several new methods for AFM probe tip shape characterization with different designs of tip shape characterizers. The new tip shape characterizers were designed to address the limitation of current structures. First, a single silicon overhang structure with wear-resistant coatings was used as the characterizer for both tip width and tip shape profile. Tip-to-tip scan repeatability data (0.7 nm 3 Sigma) and measurement statistics suggest an improvement over present state-of-the-art practice. Tip shape profiles of several high aspect ratio (20:1 to 25:1), low lateral stiffness probes were successfully characterized with this method. Furthermore, the use of single characterizer provides an opportunity to shorten tool calibration time, and consequently, increase measurement throughput. In addition, a carbon nanotube characterizer prototype is proposed for CD-AFM. When scanning probe geometry shrinks with semiconductor technology nodes, it has become a challenge to characterize a probe with a few tens of nanometer of width with a micrometer-size characterizer. Using a comparable or smaller size of characterizer for a small (20 to 50 nm) AFM probe not only reduces the dimensional uncertainty, but also expands the 2-D profiling capability of current tip shape characterization. We will discuss limitations of current tip shape profiling techniques, proof-of-concept experiments for new characterizers, implementation of new tip shape characterization methods, and approaches to increasing measurement throughput.

Design rule shrinkage and wider adoption of new device structures such as STI, copper damascene interconnects, and deep trench structures have made the need for in-line process monitoring of step heights and profiles of device structures more urgent. To monitor active device patterns, as opposed to test patterns as in OCD, AFM is the only non-destructive 3D monitoring tool. The barriers to using AFM in-line monitoring are its slow throughput and the accuracy degradation associated with probe tip wear and spike noise caused by unwanted oscillation on the steep slopes of high-aspect-ratio patterns. Our proprietary AFM scanning method, StepIn^TM mode, is the method best suited to measuring high-aspect-ratio pattern profiles. Because the probe is not dragged on the sample surface as in conventional AFM, the profile trace fidelity across steep slopes is excellent. Because the probe does not oscillate and hit the sample at a high frequency, as in AC scanning mode, this mode is free from unwanted spurious noises on steep sample slopes and incurs extremely little probe tip wear. To take full advantage of the above properties, we have developed an AFM sensor that is optimized for in-line use and produces accurate profile data at high speeds and incurs little probe tip wear. The control scheme we have developed for the AFM sensor, which we call "Advanced StepIn^TM", elaborately analyses the contact force signal, enabling efficient probe tip scanning and a low and stable contact force. With a developed AFM sensor that realizes this concept, we conducted an intensive evaluation on the effect of low and stable contact force scan. Probes with HDC (high density carbon) tips were used for the evaluation. The experiment proves that low contact force enhances the measured profile fidelity by preventing probe tip slip on steep slopes. Dynamics simulation of these phenomena was also conducted, and its results agreed well with the experimental results. The low contact force scan also incurs extremely little probe tip wear, which is essential to assure high measurement repeatability. An inherent property of StepIn^TM is that it causes little probe tip wear because of the minimal contact between tip and sample. The effects of this property have been enhanced by adding low contact force scanning.

A new inline metrology tool utilizing atomic force microscope (AFM) suited for LSI manufacturing at the 45-nm node and beyond has been developed. The developed AFM is featuring both of high-speed wafer processing (throughput: 30 WPH) and high-precision measurement (static repeatability: 0.5nm in 3σ). Several types of carbon nanotube (CNT) probes specially designed for the AFM have also been developed. The combination of Advanced StepIn^TM mode and CNT probes realizes high precision measurement for high-aspect-ratio samples such as photoresist patterns. In Advanced StepIn^TM mode, a probe tip approaches and contacts a sample surface, and then moves away from the surface and toward a new measurement position. A series of these actions is performed in a short time (3.8 ms for single measurement point) full-automatically. Advanced StepIn^TM mode not only ensures gentle probe tip contact and precise measurement of high aspect ratio samples, but also minimum tip wear. CNT probes can provide long term performance, while eliminating the need for probe exchange. The developed AFM also realizes flatness measurement of 10-nm level in a wide area of 40x40-mm maximum. This performance is sufficient for the evaluation of CMP processes at the 45-nm node.

With the semiconductor industry moving into the 65nm technology node, the metrology of the critical dimension (CD) becomes an important part for the industry. Metrology relies not only on the precision, but also on the accuracy of the tools like the high performance CD-SEMs. A major area of concern affecting the accuracy of the high performance CD-SEMs is the magnification calibration. The purpose of the research is to address this area of concern by fabrication of magnification calibration artifact by using direct write electron beam lithography. A calibration artifact has been fabricated in negative resist Hydrogen Silsesquioxane (HSQ) onto a silicon substrate, thereby decreasing the contamination on the substrate. The design of the artifact has been corrected for the proximity effects, giving a 2-D dense grid structure with 100nm pitch. Pitch determination using optical metrology tools and the inbuilt laser interferometer in the electron beam lithography tool is being evaluated for making the artifact traceable to some national standards. Once the traceability is achieved, mass production at low cost using Nanoimprint technology is feasible.

Improving device performance and yield is one of the primary goals of microelectronic research and development. In order to attain this goal, process engineers are focusing on the integration of new materials and the development of new device architectures. For production process control, the two main techniques to monitor device dimensions are CD-SEM and Scatterometry. Despite the excellent repeatability of these techniques, SEM and Scatterometry often suffer from unacceptably large measurement uncertainty, particularly when applied to newly developed device technologies. A consequence of these metrology limitations is a delay in the transition of new process technologies into production. Furthermore, these techniques have not been proven to be effective in measuring 3-dimensional characteristics such as Line Edge Roughness and Line Width Roughness in the Bottom-CD region. A potential alternative to SEM and Scatterometry in many applications is CD-AFM, a highly versatile metrology technique, which is capable of providing consistent, precise 3-dimensional measurements for a wide range of sample types and geometries. In this paper we present a recent CD-AFM scan algorithm enhancement that significantly improves Bottom-CD measurement bias and precision. In addition, we present a separate but complementary enhancement in the CD-AFM scan algorithm, which we have demonstrated to improve overall CD measurement resolution and precision, while increasing scan speed when using advanced CD-AFM Tips. Our results show that the use of these two techniques enhances Line-Edge Roughness and Line-Width Roughness resolution, precision and accuracy.

The need for a non-contact contamination removal technique has been exhibited by various companies. While an EUV compatible pellicle is being researched, contamination will become an ongoing problem to overcome. Some techniques that are being considered for contamination removal include the use of shockwaves which are potentially damaging, as well as rolling contamination off of a surface. Depending on feature size, rolling or moving of contamination horizontally across a surface is limited as there is a strong possibility that the contamination will get trapped in between features. Plasma- Assisted Cleaning by Electrostatics (PACE) is a non-contact removal method that utilizes charge imbalances to remove particles perpendicular to the surface. A positive bias is applied to the top of the sample for conducting samples or to the substrate behind an insulating sample. This positive bias draws in net electrons from the plasma to the entire surface. The contamination charges negatively and the positive bias is removed and switched with a negative bias. The combination of substrate/particle charge imbalance as well as electric field effects from the plasma sheath provide for the removal mechanism. Surface damage has been avoided by staying below the sputtering threshold for the surface materials of the samples. Recent tests on 2.5 nm ruthenium on Si/Quartz using the PACE technique coupled with Atomic Force Microscopy data has shown no roughening of the surface and approximately 90% removal efficiency of contamination. In addition, Auger Electron Spectroscopy scans show no removal of the 2.5 nm ruthenium capping layer. Removal results for 30 nm to 220 nm PSL particles as well as select other contamination materials on samples comparable with EUV masks in addition to damage assessments will be presented.

In the present research we have fabricated and investigated microfluidic device (system of periodic groves - diffraction grating) employing contact photolithography combined with the reactive ion etching (RIE). Relative diffraction efficiency of diffraction gratings (originally produced in silicon substrates) was measured experimentally and simulated using linear dimensions of gratings defined by scanning electron microscopy (SEM). The main experimental results were compared with the computer simulations where the standard software ("PCGrate-S 6.1") was employed to calculate relative diffraction efficiency of diffraction gratings for the different wavelengths of visible light. Comparing two evaluation methods: direct (electron microscopy) and indirect (relative diffraction efficiency measured at different angles of incidence for the three wavelengths of light) we have demonstrated feasibility of optical methods in control of geometrical dimensions of periodic structures at the microscopic range.

Despite ample phenomenological evidence of reticle haze in IC manufacturing fabs, the mechanism of reticle haze formation is not well understood. Many attempts to control reticle haze formations are driven by trial-and-error approach and results are frequently contradicting and confusing. The authors apply extensive expertise of airborne molecular contamination (AMC) measurement and control and DUV optics protection [1,2] to develop a potential solution to the issue of 193-nm reticle haze. The authors outline the common mechanism of reticle haze formation and show that chemical modification of the reticle surface during mask manufacturing procedure is largely responsible for mask reticle susceptibility to AMC and surface molecular contamination (SMC). A proposed mechanism well explains available experimental and phenomenological data and the differences seen in chemical compositions of the haze particles observed at different fabs. The authors propose a single elegant solution for controlling multiple types of haze. Effectiveness of this solution is demonstrated through the field data obtained from production fabs.

A spatial and temporal thermal image of a lithography cell from resist dispense through develop is obtained with a novel instrumented wafer. The wireless sensing wafer was able detect temperature changes the occurred during the photoresist dispense and exposure steps as well as in the photoresist bake steps.

In resolution limited lithography process, the image deformation is getting severer. This is very important area where we need to fully understand and improved since the image deformation is directly giving poor CD control effect. Especially, contact hole image will be more sensitive since it has lower k1 factor that line and spaced pattern. This image deformation of contact hole can give some severe electrical fail due to not opened contact. In our case, we observed some critical failure mode of diagonal induced by abnormal contact hole shape of rough edge. In this paper, we investigate how deformed contact hole image impacted on degradation of device performance in electrical properties and yield and how we can improve it. To quantitatively analyze image deformation of contact hole, we recommend new measurement method first. This new measurement gives exact image deformation amount at different experimental conditions. Finally, we will show how experimental conditions such as soft bake temperature, post expose bake temperature, hardening bake temperature, illumination condition and mask bias change image deformation of contact hole.

In lithography process, resolution enhancement technique (RET) which makes us use same lithographic equipments and materials is one of most important area to enhance development speed of device. The studies for RET have widely been done and the examples of RET are modified illumination, phase shifted mask and double exposure. The most studies have been done in lithography area. We think that area of RET study is not only lithography but also overall patterning including etching process. In this paper, we develop new RET and simultaneous patterning of Shallow Trench Isolation(STI) with gate pattern which is using oxidation process of silicone. When we use nitride hard mask process and etching with this oxidation process, we observed to achieve small resolution. Also we investigate process capability of this new process in terms of CD control, STI height and so on.

As the resolution requirement downing 90 nm beyond, hole pattern is one of the most challenging features to print in the semiconductor manufacturing process. Especially, when hole patterns have dense array of holes as they are consisted of several columns with single row, there can be serious distorted form from desired patterns such as oval hole shape and bridge between holes. It is due to nature of diffraction which generates interaction of diffracted light from near holes. Overlap margin reduction by hole shape change as oval shape is very harmful in sub-90nm photolithography process which has very narrow overlay margin. To increase overlap margin, it is necessary to solve these phenomenon. Optical Proximity Correction (OPC) has been used for overcoming oval hole shape. Through the result of OPC modeling and simulation, we could get optimized mask bias of hole. Sometimes, good experimental data will be help for this modeling and OPC process. From these OPC simulation and experimental data, most compatible rule based OPC process could be developed. In this paper, we suggest the method of improving oval hole shape by using OPC simulation and making rule base OPC process from experimental data.

Electrostatic discharge (ESD) problem resulting from charges on wafers is a serious concern in IC manufacturing processes. Even though micro-environments, such as a FOUP or a SMIF pod, provide path to ground to conduct away charges on wafers, this method cannot remove charges on the insulative features on a work-in-process wafer. In this study, we integrated an ionization module to a FOUP purge system to neutralize charges on wafers. With a full load of wafers, ionized nitrogen entered the FOUP and effectively reduced the wafer charge level from 1,000 v/cm to 100 v/cm within 5 minutes. The effectiveness of neutralizing charges and ease of integrating with currently available purge facility enable this method a promising way to help reduce wafer charges, thus reduce the possibility of ESD damages to ICs on wafer. The same idea can be applied to reduce charges on reticles in a recticle pod.

Monitoring and controlling Airborne Molecular Contamination (AMC) has become essential in deep ultraviolet (DUV) photolithography for both optimizing yields and protecting tool optics. A variety of technologies have been employed for both real-time and grab-sample monitoring. Real-time monitoring has the advantage of quickly identifying "spikes" and upset conditions, while 2 - 24 hour plus grab sampling allows for extremely low detection limits by concentrating the mass of the target contaminant over a period of time. Employing a combination of both monitoring techniques affords the highest degree of control, lowest detection limits, and the most detailed data possible in terms of speciation. As happens with many technologies, there can be concern regarding the accuracy and agreement between real-time and grab-sample methods. This study utilizes side by side comparisons of two different real-time monitors operating in parallel with both liquid impingers and dry sorbent tubes to measure NIST traceable gas standards as well as real world samples. By measuring in parallel, a truly valid comparison is made between methods while verifying the results against a certified standard. The final outcome for this investigation is that a dry sorbent tube grab-sample technique produced results that agreed in terms of accuracy with NIST traceable standards as well as the two real-time techniques Ion Mobility Spectrometry (IMS) and Pulsed Fluorescence Detection (PFD) while a traditional liquid impinger technique showed discrepancies.

As the semiconductor industry continues to implement the ITRS (International Technology Roadmap for Semiconductors) node targets that go beyond 45nm [1], the need for improved cleanliness between repeated process steps continues to grow. Wafer cleaning challenges cover many applications such as Cu/low-K integration, where trade-offs must be made between dielectric damage and residue by plasma etching and CMP or moisture uptake by aqueous cleaning products. [2-5] Some surface sensitive processes use the Marangoni tool design [6] where a conventional solvent such as IPA (isopropanol), combines with water to provide improved physical properties such as reduced contact angle and surface tension. This paper introduces the use of alternative solvents and their mixtures compared to pure IPA in removing ionics, moisture, and particles using immersion bench-chemistry models of various processes. A novel Eastman proprietary solvent, Eastman methyl acetate is observed to provide improvement in ionic, moisture capture, and particle removal, as compared to conventional IPA. [7] These benefits may be improved relative to pure IPA, simply by the addition of various additives. Some physical properties of the mixtures were found to be relatively unchanged even as measured performance improved. This report presents our attempts to cite and optimize these benefits through the use of laboratory models.

The authors present results of extensive studies on the chemical behavior of low molecular weight silicon-containing species (LMWS) and associated challenges of their analytical determination and control to prevent adverse influence on critical optical elements of exposure tools. In their paper the authors describe a non-traditional approach to the creation of a TMS gaseous source for filter media development and an engineering solution to the challenge of controlling LMWS - a solution that shows a significant advantage over currently existing approaches.

As part of the continuing reduction of half-pitch line widths, the International Technology Roadmap for Semiconductors (ITRS) forecasts an increasing number of issues with electrostatic discharge (ESD) related phenomena and the need for improved electrostatic charge control in semiconductor wafer processing. This means that wafer metrology should encompass charge measurements as a routine operation. Additionally, with the increasing complexity of wafer processing, in-line measurements including surface voltage and charge detection and analysis are becoming more important. One of the instruments utilized in such measurements is a non-contacting electrostatic voltmeter (ESVM). In this paper the authors would like to introduce a new design for the ESVM probe which allows for the measurement of surface voltages with DC stability and millivolt sensitivity. The construction of the probe utilizes a gold plated sensor that is mounted on a vibrating tuning fork which is electromechanically excited by a piezoelectric driver.

A new approach to monitoring molecular contamination in lithography is presented. Recent technical advances have made it feasible to perform continuous real-time monitoring with significant advances in sensitivity and stability while minimizing sample tubing effects. These improvements are realized by using a small, low-cost monitor that is dedicated to monitoring a single location. A dedicated, point-of-use monitor offers the following advantages over a conventional multipoint sampling system: continuous monitoring, no missed contamination events, sample tubing lengths reduced from 20 - 30 meters to 2 - 3 meters, and 5 - 10x better sensitivity. Improvements in sensitivity and stability are realized through a dedicated monitor approach to molecular contamination monitoring. Because the monitor is continuously sampling the same environment, sample averaging can be used in a highly effective manner to reduce the detection limit. This is particularly useful in chemically filtered environments where the concentrations are usually low and stable. An automated monitoring software package can simultaneously plot individual one minute data points and a long-term running average. The one minute samples are used to immediately detect the onset of a contamination event while the long term running average is used to monitor background contamination at the lowest levels.

AlCu PVD (Physical Vapor Deposition) induced overlay shift has been a critical concern for non-damascene metallization process to tackle with the ever decreasing overlay tolerances. In this study, a new approach was demonstrated to effectively eliminate the AlCu PVD induced overlay shift. With measuring the metal-to-contact registration before the metal deposition and feeding forward the values for metal-to-contact overlay compensation at the metal photo process, the metal-induced shift can be optimally managed. Besides, an investigation was also carried out to figure out the suitable measurement target with least sensitive to process parameter variations at after contact etch, after contact W CMP and after metal etch. As a consequence, the conventional wide-trench overlay target has been identified to be the more susceptible to the process variation and easily results in measurement reading error. Compared to the conventional wide-trench target, a 0.2um width narrow trench target performed the better mark integrity for our feed-forward compensation approach. Finally, the feed-forward compensation in combination with narrow width overlay mark has demonstrated its effectiveness on managing the AlCu-PVD induced overlay shift.

Airborne molecular contamination (AMC) continues to play a very decisive role in the performance of many microelectronic devices and manufacturing processes. Besides airborne acids and bases, airborne organic contaminants such as 1-methyl-2-pyrrolidinone (NMP), hexamethyldisiloxane (HMDSO), trimethylsilanol (TMS), perfluoroalkylamines and condensables are of primary concern in these applications. Currently, the state of the filtration industry is such that optimum filter life and removal efficiency for organics is offered by granular carbon filter beds. However, the attributes that make packed beds of activated carbon extremely efficient also impart issues related to elevated filter weight and pressure drop. Most of the lower pressure drop AMC filters currently offered are quite expensive and are simply pleated combinations of various adsorptive and reactive media. On the other hand, low pressure drop filters, such as those designed as open-channel networks (OCN's), offer good filter life and removal efficiency with the additional benefits of significant reductions in overall filter weight and pressure drop. Equally important for many applications, the OCN filters can reconstruct the airflow so as to enhance the operation of a tool or process. For tool mount assemblies and fan filter units (FFUs) this can result in reduced fan and blower speeds, which subsequently can provide reduced vibration and energy costs. Additionally, these low pressure drop designs can provide a cost effective way of effectively removing AMC in full fab (or HVAC) filtration applications without significantly affecting air-handling requirements. Herein, we will present a new generation of low pressure drop OCN filters designed for the removal of airborne organics in a wide range of applications.

As the design rules of semiconductor devices have decreased, the detection of critical killer defect has became more important. One of killer defect is under-etch defect caused by insufficient contact etch. Although very low throughput only e-beam inspection tool has used for monitoring tools of under-etch defect because optic wafer inspection does not have enough defect signal to detect that on a contact layer. In this study, a new method is suggested for detection of under-etch defect using optic wafer inspection tools which have high throughput and repeatability.