This PDF file contains the front matter associated with SPIE Proceedings Volume 6607, including the Title Page, Copyright information, Table of Contents, and the Conference Committee listing.

In order to comply with the demanding technology requirements for 45 nm half pitch (HP) node (32 nm technology node), Nuflare Technology Inc. (NFT) has developed Electron-beam mask writing equipment, EBM-6000, with increased current density (70A/cm²), while its other primary features basically remain unchanged, namely 50 kV acceleration voltage, Variable Shaped Beam (VSB)/vector scan, like its predecessors [1-5]. In addition, new functionalities and capabilities such as astigmatism correction in subfield, optimized variable stage speed control, electron gun with multiple cathodes (Turret electron gun), and optimized data handling system have been employed to improve writing accuracy, throughput, and up-time. VSB-12 is the standard input data format for EBM-6000, and as optional features to be selected by users, direct input function for VSB-11 and CREF-flatpoly are offered as well. In this paper, the new features and capabilities of EBM-6000 together with supporting technologies are reported to solidly prove the viability of EBM-6000 for 45 nm HP node.

Optical proximity correction (OPC) is widely used in wafer lithography to produce a printed image that best matches the design intent while optimizing CD control. OPC software applies corrections to the mask pattern data, but in general it does not directly compensate for the mask writer and mask process characteristics. The Sigma7500 deep-ultraviolet (DUV) mask writer projects the image of a programmable spatial light modulator (SLM) onto the mask using partially coherent optics similar to wafer steppers, and the residual optical proximity effects of the mask writer are in principle correctable with established OPC methods. To enhance mask patterning, an embedded OPC function called LinearityEqualizer^TM has been developed for the Sigma7500 that is transparent to the user and which does not degrade mask throughput. It employs the Mentor Graphics Calibre OPC engine, selected for the computational speed necessary for mask run-time execution. A multi-node cluster computer applies optimized table-based CD corrections to polygonized pattern data, which is then refractured into a standard writer format for subsequent data processing. This short-range proximity correction works in conjunction with ProcessEqualizer^TM, a previously developed print-time function that reduces long-range process-related CD errors. OPC flattens the linearity behavior for all linewidths and pitches, which should improve the total CD uniformity on production photomasks. Along with better resolution of assist features, this further extends the application space of DUV mask writing. Testing shows up to a 4x reduction in the range of systematic CD deviations for a broad array of feature sizes and pitches, and dark assist features are reliably printed down to 120 nm at mask scale.

The mask cost is increasing substantially from generation to generation. Hence, reducing the mask cost is one of the most critical needs in developing a new generation of technology. Compared with variable shaped beam (VSB) e-beam tools, laser writers have the advantage of higher throughput and lower cost. Moreover, the writing time is not dependent on feature count but on the area written. Additionally the FEP-171 resist, which is used for the DUV laser writer, is also the resist used for VSB writers. This enables process sharing and reduces the number of processes needed for mask manufacturing. Finally the laser writer is expected to print Manhattan and X-architecture features with no major differences. Whereas, VSB e-beam tools take longer to write, if X features are included with Manhattan-type features. The inclusion of X features also worsens CD uniformity when written with VSB e-beam tools. The Sigma7500 DUV laser writer uses partially coherent imaging of a spatial light modulator (SLM) to maximize resolution, while providing 4-pass and 2-pass printings, corner enhancement, and grid matching. These functions are evaluated and the results are reported in this paper. Evaluation data shows that the global CD uniformity of dense line/space and isolated spaces is around 6 nm (3σ) for features at 0-, 45-, 90-, and 135-degree angles, which are used in the X architecture. The resolution of lines and spaces can both reach 150 nm. Based on our evaluation, the Sigma7500 can meet both critical 65-nm and sub-critical 45-nm generation mask specifications and reduces the writing cost by 40%. The writing time for X architecture patterns can be reduced by at least a factor of two as compared to VSB systems, while the CD performance remains comparable. However, the pattern fidelity is slightly worse and the CD of 45- and 135-degree lines is difficult to adjust independently. In addition, the Sigma7500 comes with a data-sizing function (ProcessEqualizer) to compensate for global CD signatures, but the potential impact of data sizing on OPC accuracy is a concern and it must be evaluated. Evaluation data shows that the Sigma7500 is capable of 45-nm node sub-critical mask production. Its advantages in high productivity and acceptable CD control should provide a solution to reduce the mask cost of advanced nodes.

After quartz blanks with various sulfate ion amount on the surfaces were exposed by an ArF laser, growing defects, haze, on the surfaces were consequently counted by an inspection tool. As a result, the number of haze largely depends on the sulfate ion amount, and it is found that no haze is generated when the sulfate ion amount is smaller than a threshold value. A new haze generation model is provided to explain the threshold phenomenon. And then storage impact on increase of the sulfate ion amount was investigated. The sulfate ion amount increases with storage time and airborne SO_x concentration. From the results, the adsorption coefficient of an extended Langmuir equation was calculated, and the adsorption phenomenon was analyzed in detail. Simulation results show that it is recommended, regarding for storage environment, to keep under 0.01 ppbv airborne SO_x concentration in order to prevent haze for one year.

With the use of 193nm lithography, haze growth has increasingly become a critical issue for photomask suppliers and wafer fabs. Recent photomask industry surveys indicate the occurrence rate of haze is 10 times higher on 193nm masks compared to 248nm masks. Additionally, work has been presented that shows strong relationship between environmental conditions around the photomask and the occurrence of haze at 193nm. This underscores the need to better understand the basic mechanisms of haze and the measures such as environmental airborne molecular contamination (AMC) control which can be employed to reduce the occurrence of haze in use. A custom excimer laser test system capable of 193nm and 248nm wavelengths was built to accelerate haze growth and to better understand haze formation mechanisms. Work on materials impact on haze growth, such as pellicles and reticle compacts, as well as preliminary findings on environmental impacts have been presented previously. Results indicate even on pristine surfaces haze can grow when contaminants are present in the storage and use environment. The test system has been upgraded to include tight control on the concentration of specific airborne contaminants of concern. The impact of these contaminants and their relative concentrations will be examined in this paper and are presented to aid the industry in determining the level of environmental control needed over the life of a reticle.

We propose a new method of quality assurance for attenuated phase shifting mask (PSM) using the concept of the flexible mask specifications to extend the life of PSM [1]. The haze on PSM is a major issue for ArF lithography in semiconductor device manufacturing since it causes decline of device yield. PSM irradiated by ArF laser is periodically cleaned before haze is printed on wafer, which is a killer defect. Repetition of cleaning causes great changes of properties, i.e. phase, transmittance. Therefore, the number of times cleaning is performed has been limited by predetermined specifications based on ITRS. In this paper, relaxation of the pass/ fail criteria are studied as one solution to this limitation problem. In order to decide a suitable number of times for cleaning to be performed, we introduce the concept of flexible mask specifications, taking lithography margin into account. Firstly, we obtained mask parameters before cleaning; these parameters were, for instance, phase, transmittance and CD. Secondly, using these parameters, we simulated images of resist pattern exposed on wafer and obtained exposure latitude at desired depth of focus. Thirdly, we simulated mask parameters and exposure latitude when the mask was cleaned several times and obtained correlation between number of times cleaning is performed and exposure latitude. And finally, we estimated suitable pass/ fail criteria of mask parameters and the maximum number of times cleaning should be performed for each mask at the standard exposure latitude. In the above procedure, the maximum number of times cleaning should be performed exceeded that determined in the case of conventional specifications based on ITRS.

We have explored substrate effects upon the characteristics of haze creation on the mask surface by performing surface analysis for each of Cr, MoSiON, and Qz substrates of the mask before and after laser exposure. We found out chemical ions such as sulfur and ammonium ions should have different mobility behavior towards haze defect creation depending on each substrate during laser exposure. This fact can partially clarify the reason why haze occurrence on the mask in real mass production mainly comes up with Qz substrate surface even though it has the lowest level of chemical residue on it. We also realized that sulfur ions are penetrating into a sub layer of Qz substrate and even deeper during laser exposure, which signifies that we may have to remove a thin surface layer from Qz substrate to further improve haze issue from the current standpoint.

We achieved highly accurate Local CD in the vicinity of 1nm with the newly developed low sensitivity chemically amplified resist (CAR) for the e-beam reticle writer, EBM-6000. We applied shot noise model to estimate Line Edge Roughness (LER). According to the estimation result, LER is improved by increasing the threshold dosage. We evaluated the performance of newly developed low sensitivity CAR. Local CD accuracy, LER, pattern resolution and drawing time are evaluated. We concluded that the performance with the low sensitivity CAR was good enough to produce photomasks for 45nm half pitch (HP) devices.

As the required accuracy of the mask arises, Cr shading film thickness has been thinner gradually. CD linearity with the thinner Cr film thickness has better performance. However, it is difficult to apply thinner Cr film thickness simply under the condition of OD > 3, which is needed for wafer printing. So, we tried to develop new shading film. We adopted MoSi film, because MoSi film has almost no micro loading effect compared with Cr film. MoSi shading film with att.PSM satisfied OD > 3 at 193nm wavelength with good resist profile. But the issue was dry-etching selectivity, because shading layer material was the same of att. PSM layer material. Therefore super thin Cr etching stopper was inserted between MoSi shading layer and MoSi att.PSM layer. The mask CD performance of new blank was evaluated for CD linearity, CD through pitch, and global loading effect. This blank and mask process reduce loading effect, therefore the mask CD performance is improved remarkably. In conclusion, the mask manufacturing process margin was able to be expanded by this new blank and method, and it is expected that we can achieve the required specifications for att.PSM in 45nm node and beyond.

For 45 nm node and beyond, the alternating phase-shift mask (alt. PSM), one of the most expected resolution enhancement technologies (RET) because of its high image contrast and small mask error enhancement factor (MEEF), and the binary mask (BIM) attract attention. Reducing CD and registration errors and defect are their critical issues. As the solution, the new blank for alt. PSM and BIM is developed. The top film of new blank is thin Cr, and the antireflection film and shielding film composed of MoSi are deposited under the Cr film. The mask CD performance is evaluated for through pitch, CD linearity, CD uniformity, global loading, resolution and pattern fidelity, and the blank performance is evaluated for optical density, reflectivity, sheet resistance, flatness and defect level. It is found that the performance of new blank is equal to or better than that of conventional blank in all items. The mask CD performance shows significant improvement. The lithography performance of new blank is confirmed by wafer printing and AIMS measurement. The full dry type alt. PSM has been used as test plate, and the test results show that new blank can almost meet the specifications of pi-0 CD difference, CD uniformity and process margin for 45 nm node. Additionally, the new blank shows the better pattern fidelity than that of conventional blank on wafer. AIMS results are almost same as wafer results except for the narrowest pattern. Considering the result above, this new blank can reduce the mask error factors of alt. PSM and BIM for 45 nm node and beyond.

The demand for ever smaller features in integrated circuit manufacturing continues to put more stringent requirements on photomask fabrication, particularly with respect to critical dimension (CD) control. A high resolution process for making attenuated-phase-shift masks (attPSM) for the 45nm node with a negative-tone chemically amplified resist (nCAR), utilizing a new precision bake system, was evaluated. This process showed a significant performance improvement in critical dimension uniformity (CDU), respective to an established process based on an APB5500 system. A CD-uniformity improvement from 2.1nm CD 3σ to 1.3nm CD 3σ (40%) was achieved on a demanding layout. The new precision bake system utilizes an improved multi-zone hotplate design and control algorithm, which enables highly precise temperature controllability, facilitating a superior temperature ramp-up performance, as well as significantly improved temperature setpoint stability, as has been measured with a 25-point sensor mask for a 95°C bake process. The new precision bake system shall now be introduced to the market within the HamaTech MaskTrack series.

As the geometry of semiconductor devices continue to scale down, high-NA imaging will be used to enhance the resolution. Sub-resolution assistant features are used to gain depth of focus at the wafer. One of the challenges in patterning small assistant features during mask fabricating is resist collapse. Reducing resist thickness is one of the solutions. This necessitates an increase in the selectivity of chromium (Cr) to photo-resist (PR). The selectivity determines the PR remaining on the mask after Cr etching. Insufficient remaining PR will induce pinhole-type clear defect and poor line edge roughness (LER). In this paper, the Cr-to-PR selectivity was studied under induced couple plasma (ICP) and quasi-remote plasma environment. PR remaining, etching bias, and critical dimension uniformity (CDU) are the main subjects for evaluation. To understand the etching behavior for higher selectivity, design of experiment (DOE) L4 by Taguchi method is used to find the dominating factors. By adopting the optimized etching recipe, the resist can be thinned down to effectively improve its collapse margin, especially for smaller assistant features. The results show that 72-nm assistant features on mask can be patterned for early 32-nm node development. This paper also suggests several approaches that can be used to reduce the required resist thickness, such as hard-mask, film thickness reduction, and etcher hardware modification.

A research program on EUV lithography has been started at IMEC, based on ASMLs EUV full field scanner, the Alpha Demo Tool (ADT). It contains three main projects: EUV resists, EUV reticles and assessment of the ADT performance. The intent of this program is to help improve and establish the necessary mask and resist infrastructure, and achieve learning to prepare for the use of EUV lithography in future production of integrated circuits. Good progress in resist performance, as assessed by interference lithography, is illustrated by the ability of some materials to resolve 25nm HP. In its initial phase, the reticle project has concentrated on working with the mask and blank suppliers to assure timely availability of reticles for the ADT. An overview is given of the other reticle related activities, as well as first results of a defect printability assessment by simulation and a study of blank reflectivity control. Guidance is given to the EUV mask infrastructure to assure timely availability of reticles, first for the alpha demo tool (ADT), but also in preparation for future use of EUV lithography in production. In the ADT assessment project, simulation studies are reported aimed at the development of optical correction for flare and reticle shadowing effects. The impact of flare and shadowing effects are well understood Strategies for flare mitigation and shadowing effect correction are proposed.

Successful commercialization of extreme ultraviolet lithography (EUVL) requires high quality EUV mask blanks for patterned masks that are essentially defect-free and very flat with high performance reflective multilayers. For 32 nm half-pitch (HP) integrated circuit manufacturing, such blanks require zero defects down to 25 nm diameter sizes while simultaneously meeting other specifications. At least three critical specifications that need continued improvements (total defects, defect size inspection, and substrate flatness control) are challenging to attain individually; meeting all requirements simultaneously will be especially challenging. Since early 2003, SEMATECH has been engaged with the mask blank materials and mask tool supplier community to drive the readiness of alpha, beta, and production mask blanks to support EUV lithography introduction. SEMATECH uses its commercial mask blank development roadmap together with neutral metrology evaluations of commercial suppliers' materials to monitor progress against needed production requirements. Commercial blank capability has improved significantly over the past two years; however, beta-level performance has still not been attained for all requirements. Attaining integrated blank specifications is more difficult than meeting individual specifications. Significant improvements including defectivity, flatness, coefficient of thermal expansion (CTE), reflectivity, wavelength control, and buffer/absorber stack performances are needed. Several orders of magnitude improvement is needed in defectivity levels alone coupled with increased detection sensitivity to 25 nm diameter defects. This paper will illustrate the recent rate of improvements along with an updated SEMATECH commercial roadmap, highlighting individual specification performances and total blank integrated performance levels currently better than 0.2 def/cm² at ≥ 80 nm polystyrene latex (PSL), peak reflectivity ≥ 64.0%, substrate flatnesses ≤ 175 nm peak-to-valley (P-V), with other key requirements. EUV blank cost of ownership studies will highlight the cost to manufacture these materials and show potential issues if yields are marginal.

Overlay requirements of Extreme Ultra-violet Lithography (EUVL) dictate reticle flatness errors of 50nm or less. During the early phase of EUVL development, it was decided that an electrostatic chuck was required to flatten EUVL masks to these specifications. However current experience and test data have demonstrated that it will be very difficult to reach the desired mask flatness goal without a thorough understanding and advanced control of the echucking process. The results of a parametric model study are reported in this paper. In this study we calculated the chucking force dependence of activating voltage, e-chuck geometry, film material, and pin design, and then proposed an optimized chuck design. We have also engaged in a material study for the mask backside coating for the purpose of reducing flatness errors and minimizing backside particle generation. We have also designed and built an automated, vacuum based, interferometric metrology tool to enable e-chucking experimentation. An early status report of this tool will be included in this paper.

The detectability of a small phase defect on a multilayer-coated mask blank was investigated by using electromagnetic simulation. When a smoothing deposition of multilayer coating is used the inspection signal from the phase defects is characterized not only by a top surface topography of the multilayer but also by bottom topography. To understand the impact of the bottom topography we first calculated the phase shift of reflected EUV light from multilayers with various bi-layer thicknesses since the smoothing effect may be equivalent to the local multilayer thickness variation. Then, we estimated the actinic inspection signal intensity from bump, pit, line, and groove defects taking into account the phase shift due to bi-layer thickness change and the phase change due to the top surface topography. Simulation results revealed that the phase shift due to the top surface topography was enhanced by smoothing deposition for both convex and concave shaped phase defects. Thus the bump defect is detected as higher bump than the actual height of top surface and the pit defect is detected as a deeper pit than the surface depth.

EUV mask pattern inspection was investigated using current DUV reticle inspection tool. Designed defect pattern of 65nm node and 45nm node were prepared. We compared inspection sensitivity between before buffer etch pattern and after buffer etch pattern, and between die to die mode and die to database mode. Inspection sensitivity difference was not observed between before buffer etch pattern and after buffer etch pattern. In addition to defect inspection, wafer print simulation of program defect was investigated. Simulation results were compared to inspection result. We confirmed current DUV reticle inspection tool has potential for EUV mask defect inspection.

This paper proposes an evaluation pattern generating method that realizes stable printing for any two-dimensional feature. Below 65nm design node, even in the case of using the most advanced optical techniques, the resolution limit is approached. As a result, patterning fidelity to the target worsens in low k1 lithography conditions. Complex layout patterns, especially two-dimensional features, become increasingly sensitive to photo-resist bridging and necking. This means that the need for rich two-dimensional patterns is increasing in order to cope with lithographic patterning fidelity issues, such as quality assurance of OPC script and establishment of the design rule. A new pattern generating method reported in this paper can provide plenty of two-dimensional patterns by employing the Monte Carlo method. It can also take the design rule checker into account to present patterns without any design rule violation. In addition, to narrow significant generated patterns down to the real efficient patterns, some devices are employed. More than 2000 feature variations of feature can be generated in less than half day by this new method. To determine the efficacy of two-dimensional patterns generated by this method, some examples are provided. We have validated the efficiency of extracted patterns by employing some devices, and get quality assurance of our OPC script with the generated pattern features. It is shown that the proposed method is significantly efficient for detecting hotspots that are unfaithful to the target with low k1 factor.

Development of extended optical systems using liquid immersion for patterning enables numerical apertures > 1.2 lithography. Hyper numerical aperture (NA) lithography has to deal with extremely oblique incident light, mask polarization, mask topography effects and large diffraction angle from mask feature with tight pitch. Simulation tools predicting highly accurate results based on real experimental data are widely used in the industry and for lithography process development. Predictability of Optical Proximity Correction (OPC) tools is strongly dependent on the amount of physical effects taken into account. Therefore going below 45nm half pitch the correct description of the real mask nature including the effects of mask topography, polarization and pellicle apodization is vital to the success of immersion lithography. In this paper we investigate the impact of pellicle apodization effects predicted by simulations for OPC. Significant pellicle apodization induced CD differences including 1D and 2D OPC structures will be presented. The key emphasis of this paper is to highlight the criticality of an integrated OPC solution including mask polarization, mask topography and pellicle apodization effects for enabling immersion lithography moving beyond 45nm and 32nm nodes.

To reduce design spin time, OPC-unfriendly spots in IC layout should be found out by designer before tapeout. This can be done by firstly running a "trial OPC" step on the layout, followed by running an ORC step to verify the result. In this paper we introduce a specialized cell-wise OPC method using an edge bias modeling method to improve the accuracy while keeping the advantage on correction speed, which is dozens of times faster than traditional model-based OPC method. This makes the algorithm a good choice for "trial OPC".

As technology migrates from 90nm to 65nm and 45nm, it is increasingly difficult to achieve fast yield ramp due to random defects, process variations, systematic yield problems and other limitations referred to as design-for-manufacturing (DFM) issues. At 90nm and finer process nodes, these problems often appear as layout hot spots. To avoid downstream yield and manufacturing problems relating to layout hot spots, it is imperative that the layout of library cells used in system-on-chip (SOC) designs are printable, OPC compliant, litho compliant, as insensitive as possible to process variations, and capable of achieving the high yield. It is not uncommon to have fifty thousand plus hot spots in a typical 65nm SOC device¹. This paper describes a DFM methodology and a system for improving the quality of cell layouts, using physical layout optimization. This system takes into account actual foundry information, including defect data, fab-specific optical and litho settings, simple design rules and composite design rules. The automated layout optimization system analyzes a GDSII layout, determines the potential impact of failure and eliminates hot spots using 2-D physical layout optimization, resulting in an enhanced GDSII layout that is correct by construction and optimized for yield.

Extreme ultraviolet lithography (EUVL) tool development achieved a big milestone last year as two full-field Alpha Demo Tools (ADT) were shipped to customers by ASML. In the future horizon, a full field "EUV1" exposure tool from Nikon will be available by the end of 2007¹ and the pre-production EUV exposure tools from ASML are targeted for 2009². It is essential that high quality EUVL masks can be made and delivered to the EUVL tool users to support the technology development. In the past year, we have demonstrated mask fabrication with low stress absorber deposition and good etch process control yielding a vertical etch profile and a mask CD control of 5.7 nm for 32 nm (1x) space and 7.4 nm for 32 nm (1x) lines. Mask pattern resolution of 15 nm (1x) dense lines was achieved. Full field reflective mask die-to-die inspection at a 125nm pixel size was demonstrated after low defect multilayer blanks became available. In this paper, we will present details of the Intel EUVL Mask Pilot Line progress in EUVL mask defect reduction, pattern CD performance, program defect mask design and inspection, in-house absorber film development and its performance, and EUVL metrology tool development. We will demonstrate an overall improvement in EUV mask manufacturing readiness due to our Pilot Line activities.

EUV lithography is one of the most developing and promising lithography techniques. Recently many papers are focused on defect control of EUV mask multilayer blank, but development of profile metrology is also very important. 2D scatterometry becomes insufficient in conditions of further shrinking of feature size and complication of mask patterns. To overcome these limitations 3D scatterometry should be used. In this paper we study the precision of 3D scatterometry measurements of two-dimensional EUV mask features with variety of geometrical shapes. As in reflectometry of EUV mask we can use only one or a few wavelengths, we have to take into account intensities of many reflected orders to extract profile precisely. We calculate the library of diffraction efficiencies for periodic circular, elliptical, and rectangular shaped with rounded corners features using 3D RCWA method. Then we find the amplitudes of reflected diffraction orders from feature with random arbitrary shape, compare them with each set of data in the library, and extract the most appropriate shape. After that we analyze whether the extracted shape is really close to initial arbitrary shape or not. In some cases extracted shape is not the closest one to the real. It is demonstrated that non-zero value of azimuth angle of incident light influence on precision of feature shape determination and lead to deterioration of results. Using of polarized light helps to improve precision of results, but unlike 2D scatterometry the optimal polarization can not be determined unambiguously. According to received data we provide recommendations for optimal 3D EUV scatterometry measurements and determine the necessary steps of varying of geometrical parameters for library features.

The Step and Flash Imprint Lithography (S-FIL^TM) process uses field-to-field drop dispensing of UV curable liquids for step and repeat patterning for applications where high-resolution mix-and-match overlay is desired. Several applications, including patterned media, photonic crystals and wire grid polarizers, are better served by a patterning process that prints the full wafer since alignment requirements are not so stringent. In this paper, a methodology for creating high resolution thin templates for full wafer (or disk) imprinting is described. The methods have been applied toward the imprinting of both photonic crystal and patterned media devices using a large area printing tool developed around the S-FIL process.

NIL technique enables an easy replication of three dimensional patterns. Combined with a UV printable low-k material the NIL lithography can dramatically simplify the dual damascene process. Goal of this work was to develop a template process scheme which enables the generation of high resolution pillars on top of corresponding lines for direct printing of later vias and metal lines. The process flow is based on conventional 6025 photomask blanks. Exposure was done on a variable shaped e-beam writer Vistec SB350 using a sample of an advanced negative tone CAR and Fujifilm pCAR FEP171 for the first and the second layer, respectively. Chrome and quartz etching was accomplished in an Oerlikon mask etcher Gen III and Gen IV. Assessment of the developed template process was done in terms of overlay accuracy, feature profile and resolution capability depending on aspect ratio and line duty cycle. Finally the printability of 3D templates fabricated according the developed process scheme was proved.

As the minimum feature size gets smaller, the use of optical proximity correction (OPC) becomes more aggressive. The time for mask data preparation dramatically increases. The increase in the number of small size patterns in design causes the increase of Mask Rule Check (MRC) error. It brings the need for checking the error between mask fab and Taped-out customers. Therefore, the Turn-Around Time (TAT) is enlarged. MRC offers not only the rule check but also the violated-pattern-correction to satisfy the quality requested by the customers. In this paper, we suggest a new MRC flow by using new MRC tool that carrys out MRC over various input of e-beam data and handles the MRC output data. In case of the violated pattern which approaches Mask Constraint we expand violated pattern size for pattern correction. And the elimination method can be applied to very small pattern. We describe how well preformed differently in mask exposure time and inspection capability.

As the industry moves to 45nm and beyond, rapidly increasing file sizes are an obstacle to achieving fast turnaround time for mask manufacturing. Conventional Mask Data Preparation (MDP) requires the production of large files, in a format specific to each make and model of E-beam tool. An alternative approach extracts the data from a data file already present in the MDP flow, and provides it directly to the E-beam tool. This extraction is called a "Data Exploder", because the output data volume can be larger than the input data. Exploding the data in real-time saves the time required to write and then read large disk files. The Data Exploder is compatible with multithread and multiprocess parallel reading. The practical application and limitations of the Data Exploder are described, including throughput performance, requirements for disk storage, network interconnect, and CPU configurations.

With rapid increase in the number of geometries in a chip and aggressive RET carried out on layout data, it has become very much imperative to address the issue of layout and EB data explosion during IC design. Currently, the most widely used GDSII format for layout data as well as the widely used data formats for EB data, are incapable of handling the huge amount of data prevalent in the UDSM regime. The new non-proprietary standardized formats of OASIS for layout data and OASIS.VSB for EB data are the way the industry is likely to go in the near future to address the issue of data explosion. But, the process of adoption of these new formats is too slow as it takes a long time for new design flows to mature. The speed of adoption is especially slow in the post-layout domain as it is very close to manufacturing and the cost of error is too high. However, the issue of layout and EB data explosion is real and immediate and hence, it should be addressed in short term without waiting for the long term solution to arrive. This paper discusses about an alternative approach of employing format-specific lossless reversible layout and EB data compression schemes to compress the layout and EB data. The performance and the advantage of this approach are compared with the currently prevalent approach of using OASIS primarily and solely for on-disk file size reduction. It is argued that the reversible compression techniques could be a better approach for on-disk data file size reduction as they would not only reduce the file sizes but could also almost seamlessly get integrated into the current tool flow without necessitating major changes in the tool flow. The possibility of using OASIS itself as a format for lossless reversible compression of GDSII and MEBES data is also discussed. It is also argued that for successful adoption of OASIS formats by the industry mere on-disk file size reduction may not be sufficient. Higher value additions such as reduction in in-core database size, enabling higher performance in data processing etc. may have to be addressed by the tool flows which adopt OASIS based formats natively.

As lithography mask process moves toward 45nm and 32nm node, phase control is becoming more important than ever. Both attenuated and alternating Phase Shifting Masks (PSM) need precise control of phase as a function of both pitch and target sizes. However conventional interferometer-based phase shift measurements are limited to large CD targets and require custom designed patterns in order to function properly, which limits phase measurement Zeiss is currently developing an optical phase measurement tool (Phame^TM), providing the capability of extending process control from large CD test features to in-die phase shifting features with high spatial resolution. The necessity of designing this optical metrology tool according to the optical setup of a lithographic exposure tool (scanner) has been researched to be fundamental for the acquisition of phase information generated from features close to the size of the used wavelength. It was found by simulation that the image phase of a scanner depends on polarization and the angle of incidence of the illumination light due to rigorous effects. Additionally, for small features the phase value is strongly influenced by the imaging NA of the scanner due to the loss of phase information in the imaging pupil. Simulations show that the resulting scanner phase in the image plane only coincides with the etch-depth equivalent phase for large test features, exceeding the size of the in-die feature by an order of magnitude. In this paper we introduce the Phame^TM phase metrology tool, which enables the industry to perform in-die phase control for Alternating PSM, Attenuated PSM and CPL masks. The Phame^TM uses a 193nm light source with the optical capability of phase measurement at scanner NA up to the equivalent of a NA1.6 immersion scanner, under varying, scanner relevant angle of incidence for Attenuated PSMs and CPLs, and with the possibility of polarizing the illuminating light. New options for phase shifting mask process control on in-die features will be outlined with first phase measurement results for varying states of polarization.

For the first time, polarized broadband transmittance (T) plus reflectance (R) measurements, combined with the Rigorous Coupled-Wave Analysis (RCWA) and the Forouhi-Bloomer dispersion equations for n and k, were used to measure 2D trench dimensions. This is in contrast to traditional scatterometry, which is based on reflectance-only measurements. T and R were measured from 190 to 1000 nm in one-nanometer intervals. Inclusion of the transmittance measurements proved to be advantageous, because there is a greater sensitivity of the T spectra to the sub-nanometer structural and/or material variations, which are difficult to detect with R-only measurements. Furthermore, the intensity of T is much higher than the intensity of R, resulting in a much improved signal-to-noise ratio, since intensity is proportional to number of photons reaching the detector, which in turn is proportional to the signal. Thus, the higher the intensity, the higher the signal-to-noise, and the better the repeatability and reproducibility of the results. For the current study, 2D arrays of square and circular contact holes of various pitches were measured on an After-Clean-Inspection (ACI) phase-shift mask, using a spectrophotometer-based instrument, capable of collecting four continuous spectra during one measurement - two polarized reflectance spectra (R_s and R_p) and two polarized transmittance spectra (T_s and T_p). The measured spectra were analyzed using the Forouhi-Bloomer dispersion equations, in conjunctions with RCWA algorithm, applied simultaneously to R and T polarized spectra. The method provided accurate and repeatable results for contact hole depths, critical dimensions film thicknesses and n and k spectra. High-resolution uniformity maps were obtained for all the parameters mentioned above.

An immersion microscope with high NA condenser lens is evaluated. The effects of high NA condenser lens are studied with simulation and experiment. The one effect is CD linearity improvement. We have already reported that our calibration method improves CD linearity of an immersion microscope. The simulation result indicates the high NA condenser lens improves the accuracy of the calibration method. The other effect is CD repeatability. The experimental result demonstrates the high NA condenser lens reduces the peak of intensity profile and improves CD repeatability. As the result, an immersion microscope with high NA condenser lens is available for CD measurement of 45 nm generation masks.

Nano-machining repair tool plays an important role in the current 65 nm node photomask repair. It removes defects mechanically with nanometer sized diamond tip with high accuracy and low damage using high accuracy AFM data. The repair performance of nano-machining repair system largely depends on the diamond tip whose aspect ratio decides the minimum reparable feature size. As the device shrinks to 45 nm or 32 nm node, higher aspect ratio tip with weak structure is required. It is contradiction to the fact that more accurate edge placement and better repair slope is required in smaller node repair, because deflection or tip wear effect could happen in high aspect ratio tip. In this article, deflection and wear effect were investigated in single layer repair recipe using SEM and AIMS^TM. Multilayer recipe which complements weak structure was estimated carefully, and some limits were discussed. Finally some requirements of nano-machining repair system for 45 nm node were presented.

A new die-to-database high-resolution reticle defect inspection platform, TeraScanHR, has been developed for advanced production use with the 45nm logic node, and extendable for development use with the 32nm node (also the comparable memory nodes). These nodes will use predominantly ArF immersion lithography although EUV may also be used. According to recent surveys, the predominant reticle types for the 45nm node are 6% simple tri-tone and COG. Other advanced reticle types may also be used for these nodes including: dark field alternating, Mask Enhancer, complex tri-tone, high transmission, CPL, etc. Finally, aggressive model based OPC will typically be used which will include many small structures such as jogs, serifs, and SRAF (sub-resolution assist features) with accompanying very small gaps between adjacent structures. The current generation of inspection systems is inadequate to meet these requirements. The architecture and performance of the new TeraScanHR reticle inspection platform is described. This new platform is designed to inspect the aforementioned reticle types in die-to-database and die-to-die modes using both transmitted and reflected illumination. Recent results from field testing at two of the three beta sites are shown (Toppan Printing in Japan and the Advanced Mask Technology Center in Germany). The results include applicable programmed defect test reticles and advanced 45nm product reticles (also comparable memory reticles). The results show high sensitivity and low false detections being achieved. The platform can also be configured for the current 65nm, 90nm, and 130nm nodes.

A new DUV high-resolution reticle defect inspection platform has been developed. This platform is designed to meet the reticle qualification requirements of the 65-nm node and beyond. In this system, the transmitted and reflected inspection lights are collected simultaneously to produce reticle images at high speed. Transmitted and reflected inspections in the die-to-die (DD) and the die-to-database (DB) modes can be executed concurrently. Both images can be gathered at full synchronization with low noise. Basically, both inspection modes are needed to detect as many types of hard and soft defects as possible. Concurrent inspection saves time from using transmitted and reflected lights sequentially. In this presentation, results of DD and DB inspection using standard programmed defect test reticles as well as advanced 65-nm production reticles, are given, showing high-sensitivity and low-false-count detections being achieved with low operating cost.

The importance of mask pattern inspection is increased as design node shrinks below. The major reason is as follows. Firstly, inspection systems have to enhance sensitivity because the high grade devices are seriously affected from small defects compared with low grades. The other is SRAFs RET masks. In order to inspect SRAF properly, inspection systems need severer conditions such as small pixel size, short wavelength and special algorithms. Therefore, it takes more than 3 hours to inspect a mask and this increasing inspection time is a serious burden in mask making process. Moreover in spite of mask market and its infrastructure, cost of inspection system is too high. In this paper, the advantages of using Xe-Hg lamp instead of a DUV laser are presented. Special defect algorithms get over low sensitivity of lamp optics. We have evaluated performances of the defect inspection system with programmed defect mask and production mask. The inspection system is cost-effective because the optic part is configured by DUV lamp and fiber optic delivery system. The fast scanning speed is enough to charge the inspection capacity in the fabrication line. These features of the system well match with the flexibility of the facility layout in the mask production.

For the technology node of 90 nm and below, application of design for manufacturing (DFM) techniques is indispensable. We proposed the line end extension method for metal layer layouts in mask data preparation for robustness process, and achieved to reduce systematic yield loss caused by isolated patterns [1]. However, these lithography friendly design approaches sometimes cannot optimize the chip yield by increase in critical area and creating a new yield failure mechanism. In order to accurately analyze systematic yield failures and optimize layout to improve manufacturability, a set of metrics that evaluate the robustness of a layout is needed. We propose the new method to estimate systematic yield due to lithography variations on the chip layout. Lithography variations are expressed as a function of focus margin, exposure latitude and overlay misalignment, and marginal patterns at process corners in the chip layout are extracted. Each process window of the extracted patterns is calculated and common process window is calculated to achieve the full process window of the concerned patterns. The resulting process window specifications are used on the full chip to calculate systematic yield. A quantitative result of the comparison of systematic yield and random yield is shown by this method.

The adoption of the model-based OPC and RET does not guarantee enough process margin any more in the low k1 lithography because potential patterning defects by layout-induced hot spots reduce common process window. The introduction of the litho-friendly layout has faced practical limitation by the designers' short knowledge of the lithography and its impact on the layout. In this paper, we develop a novel method based on restricted design rules (RDR) and process window verification (PWV) to get rid of the layout-related process hot spots during the physical layout design. Since RDR consists of simple design rules familiar to designers and PWV is implemented on layout editor environment, this proposed method is easy to apply in the current design flow. Since memory core layout is designed with typical and repeated patterns, the restriction of layout by design rule enforcement is effective to remove hot spots in the core area. We develop a systematic RDR extraction method by designing test patterns representing repeated memory core patterns by simple pattern matching technique. 1-dimensional (1D, simple line and space pattern) and 1.5-dimensional (1.5D, complicated line and space pattern) test patterns are analyzed to take into account the printability. The 2-dimension (2D) test patterns split by contact pad size are designed to consider the overlap margin between related layers. After removing the hot spots with RDR violations on unit cell by auto-fixer, PWV is applied to detect the random hot spots located on peripheral area. Analyzing CD difference between measurement and simulation according to variation of resist cutting plane and focus, the optical model having physical meaning is generated. The resist model, which uses focus exposure matrix (FEM) data within the process margin of memory cell, can represent the photo process variations accurately. Implementing the proposed method based on RDR and PWV, depth of focus (DOF) of sub-60nm memory device is improved by 50% compared with the result of original layout.

We investigated the possibility of hotspot detection after lithography simulation by using Neural Networks (NN). We applied the image recognition technique by the NN for hotspot detection and confirmed the possibility by its recognition rate of the device pattern defects after NN learning. Various test patterns were prepared for NN learning and we investigated the convergence and the learning time of the NN. The compositions of the input and the hidden-layers of the NN do not have so much influence on the convergence of NN, but the initial parameter values of weight setting have predominant effect on the convergence of the NN. There are correlations among the learning time of the NN, the number of input samples and the number of hidden-layers, so a certain consideration is required for NN design. The hotspot recognition rate ranged from 90% to 42%, depending pattern type and learning sample number. Increasing learning sample number improves the recognition rate. But learning all type patterns leads to 55% recognition, so learning single type pattern leads to better recognition rate.

Patterning isolated trenches for bright field layers such as the active layer has always been difficult for lithographers. This patterning is even more challenging for advanced technologies such as the 45-nm node where most of the process optimization is done for minimum pitch dense lines. Similar to the use of scattering-bars to assist isolated lines structures, we can use inverse Sub Resolution Assist Features (SRAF) to assist the patterning of isolated trenches structures. Full characterization studies on the C45 Active layer demonstrate the benefits and potential issues of this technique: Screen Inverse SRAF parameters (size, distance to main feature) utilizing optical simulation; Verify simulation predictions and ensure sufficient improvement in Depth of Focus and Exposure latitude with silicon process window analysis; Define Inverse SRAF OPC generation script parameters and validate, with accurate on silicon, measurement characterization of specific test patterns; Maskshop manufacturability through CD measurements and inspection capability. Finally, initial silicon results from a 45nm mask are given with suggestions for additional optimization of inverse SRAF for trenches.

Lithography models, including rigorous first principle models and fast approximate models used for OPC, require calibration using measured linewidth data. For models that predict process window behavior, the basic calibration data is linewidth versus focus and exposure over a range of feature sizes and types. The most common numerical method of finding the best fit model parameters is standard least-squares regression. While simple, this approach suffers from a number of well known problems. First, least-squares regression in not robust, meaning that even one bad data point can make the fit meaningless. Thus, outlier rejection becomes an important part of this approach. Both outlier rejection strategies and the use of robust fitting methods will be discussed. Second, standard least-squares may weight the data using the uncertainty in the measured linewidths, but uncertainty in the input variables, focus and exposure, is ignored. Often, at the extremes of focus and dose, errors in focus and dose actually dominate the resulting uncertainty in the measured linewidth. This can be accounted for using total least-squares regression. While often computationally difficult, in this paper an extremely fast and simple method for total least-squares regression will be presented for focus-exposure linewidth data. Finally, uncertainty in nominally fixed parameters, such as the linewidths of the features on the photomask used in the calibration, can lead to significant uncertainty in the resulting model parameters. The two standard approaches for dealing with this would be to leave these parameters fixed, or allow them to 'float' and be adjusted for best fit. Neither approach is satisfying. A better solution is to use Bayesian fitting, where a priori estimates of the mask feature widths and their uncertainties are used in the fitting merit function.

Mask topography has effects on important components of optical image formation at 45nm node and beyond, and therefore, the lithography simulation model required for hotspot-based mask quality assurance has to incorporate mask topography effects. Since calculation of mask topography effects involves physical phenomena different from those encountered in resist processes, we propose the concept of the mask & resist dual fitting method that splits the general experimental model into the experimental resist model and the experimental mask model. To realize mask & resist dual fitting, we have developed an experimental mask model, namely, the mask topography approximate model. The mask & resist dual fitting method can improve model fitting accuracy and improve prediction accuracy at hotspots.

The purpose of this work was to find the specific effects of hole patterns in 32nm node logic by analyzing in the Fourier domain and to clarify the mechanism of mask topography effects. Our focus patterns extend from the lines and spaces (LS) to the contact hole (CH). We also attempt to perform factor analyses of mask topography effects. Intensities of LS and CH patterns are simulated using three mask models. For each of the three models, the method of approximating the mask topography effect is different. As a result, a serious difference among the three mask models has been found with respect to the intensity profile for 32nm node and beyond, though the mask sizes for all models are the same. As the accuracy of mask model improved, it was found that the image contrast tends to decrease on LS patterns while increasing on CH patterns. The qualitative interpretation of the trend of contrast variations can be described by analyzing in the Fourier domain. The mask topography effects can be separated into waveguide and shadowing effects using scatter graphs. It is concluded from the result that one of the major differences between LS and CH is attributable to phase differences between 0th order and 1st order diffractions, because the size of effects for CH have been larger than that for LS.

Water-based ArF Immersion Lithography has overcome obstacles and enabled the 45nm node of mass products. Canon has developed immersion exposure system the FPA7000 AS7 for 45nm node. The new platform, the FPA-7000, is designed to cover multiple generations. The lens performance about wavefront aberration of the FPA-7000AS7 is predicted to be less than 4m&lgr;. The illumination performance meets the target required for the 45nm node. A solution tool for optimization is introduced to be connected with the FPA-7000. Moreover, latest studies of immersion, such as nozzle pressure, temperature control and defect inspection result are reported, and also discusses the possibility of high-refractive-index immersion.

Contribution of mask line edge roughness (LER) to resist LER on wafers was studied both by simulations and experiments. LER transfer function (LTF) introduced by Naulleau and Gallatin was generalized to include the effect of mask error enhancement factor (MEEF). Low spatial frequency part of LTF was enhanced by MEEF while high spatial frequency part was suppressed due to the numerical aperture limit of a stepper. Our model was experimentally verified as follows. First LER of a mask was measured by a scanning electron microscope. Then the mask LER was multiplied by LTF to simulate the aerial image LER on wafers. It was confirmed that the simulated LER agreed well with the LER measured by AIMS^TM. Based on our model the contribution of the mask LER to the resist LER on wafers was estimated. According to our estimation the requirement of the mask LER should be as tight as that of the resist LER on wafers.

The optical resolution of Binary mask (BIN) surpasses that of phase shift mask (PSM) when the node size is smaller than 45nm. Therefore, resolution enhancement technology (RET) of the binary mask has become more important in order to realize 45nm node lithography. In this paper, we present a unique way to improve the resolution of conventional binary mask simply by depositing a thin oxide film on the patterned side of the mask. The improvement has been proven by 3D rigorous simulation and real experiment. The simulation result predicts that the binary mask with a thin oxide layer would show increased normalized image log slope (NILS) by more than 10 %, compared to the conventional binary mask. The real experimental evaluation shows even further improved NILS when a thin oxide layer is deposited on the binary mask. The mask structure with a thin oxide layer turns out to have advantages over the conventional binary mask in terms of not only improved NILS but also DOF margin aspects. We further investigated resolution enhancement of the mask structure with a thin oxide layer depending on different duty ratios of the mask pattern.

This paper proposes a new virtual lithography system to improve the productivity of high-mix / low-volume production. In the case of the conventional technique, product mask and wafer are used to determine a focus-exposure-matrix (FEM) exposure condition. The conventional technique is a "send-ahead" process involving exposure, metrology and data analysis that decreases productivity of manufacturing. In the case of low-volume/high-mix ASIC manufacturing, such a send-ahead process is particularly time-consuming and costly. Moreover, the exposure condition setting imposes a huge workload that is desirable to be avoided from the viewpoints of cost and TAT. Thus, a new methodology to determine exposure dose conditions for each mask in high-mix / low-volume production is required. In this paper, we propose a virtual lithography system to eliminate send-ahead exposure. Firstly, to improve wafer CD prediction accuracy, we rebuild the system, thereby transforming it from a training-based system to a simulation-based system. To make simulation models, we use a golden mask, which is not a product mask. Secondly, exposure conditions are determined by considering 2D patterns including hotspot patterns. Thirdly, the lithography simulation is carried out for each exposure tool. Using the golden mask, we calibrate simulation models for each exposure tool^1-3. Various patterns including hotspots likely to become fatal errors for circuit reliability due to process proximity effects are considered. The virtual system provides optimal exposure parameters according to product and layer, considering long-term variation of exposure tool conditions. By developing this system, TAT and cost for the determination of exposure parameters will be improved. Elimination of send-ahead wafers can reduce TAT from mask delivery to exposure condition setup in high-mix / low-volume production. Drastic cost reduction is realized in high-mix / low-volume production.

Low pass filtering taking place in the projection tools used by IC industry leads to a range of optical proximity effects resulting in undesired IC characteristics. To correct these predicable OPEs, EDA industry developed various, model-based correction methodologies. Of course, the success of this mission is strongly dependent on how complete the imaging models are. To represent the image formation and to capture the OPEs, the EDA community adopted various models based on simplified representations of the projection tools. Resulting optical proximity correction models are capable of correcting OPEs driven by the fundamental imaging conditions such as wavelength, illuminator layout, reticle technology, and lens numerical aperture, to name a few. It is well known in the photolithography community that OPEs are dependent on the scanner characteristics. Therefore, to reach the level of accuracy required by the leading edge IC designs, photolithography simulation has to include systematic scanner fingerprint data. These tool fingerprints capture excursions of the imaging tools from the ideal imaging setup conditions. They quantify the performance of key projection tool components such as illuminator and lens signatures. To address the imaging accuracy requirements, the scanner engineering and the EDA communities developed OPC models capable of correcting for imaging tools engineering attributes captured by the imaging tools fingerprints. Deployment of immersion imaging systems has presented the photolithography community with new opportunities and challenges. These advanced scanners, designed to image in deep sub-wavelength regime, incorporate features invoking the optical phenomena previously unexplored in commercial scanners. Most notably, the state of the art scanners incorporate illuminators with high degree of polarization control and projection lenses with hyper-NAs. The image formation in these advanced projectors exploits a wide range of vectorial interactions originating at the illuminator, on the pattern mask, in the projection lens and at the wafer. The presence of these, previously subdued phenomena requires that the imaging simulation methodologies be refined, increasing the complexity of the OPE models and optical proximity correction methodologies.

It is suggested that stray-light (SL, also called flare, scattered light) impact can be compensated by modifying standard OPC method. Compared to traditional optical proximity effect caused by diffraction limit, stray light leads to extremely long range (~ 100 micrometer ~ 10 millimeter) proximity effect. Appropriate approximation is introduced for stray-light implemented OPC in such a large scale. This paper also addresses other practical problems in the stray-light OPC and presents how to solve the problems.

Traditional approach to model based optical proximity correction method is to collect a set of 1-D and 2-D test pattern data, calibrate a scalar or vector model at constant or variable threshold and modify the physical layout to obtain the desired layout. Optical proximity corrected layout is obtained by minimizing the error between the target and the printed image iteratively using a calibrated single model to generate a simulated print image of mask pattern of variety of field polarity. A similar approach can be extended to incorporate the final silicon image using a lumped model or tandem photo-resist development and etch process models. Recently, some have begun to incorporate differing models at specific regions of the layout. The basic underlying assumption of a model-based OPC requires one to generate a simulated contour that provides close approximation of wafer image using a calibrated model. During iterative OPC procedure, not all of the regions of OPC polygons are simulated. That is, sparse sampling of each polygon is performed to reduce the number of error calculations required and such calculation points are referred to as an evaluation site. A careful selection of sampling site must be performed to capture optical proximity effect and obtain the desired OPC. In this paper, utilization of multiples models to generate contour to accurately define the 2D pattern locally, and implementation of its models throughout the layout is presented in order to improve accuracy of variety of contact pattern types present in a layout. Hence, the basic concept is to apply differing models at localized region and achieve greater OPC accuracy than a single calibrated model. In particular, a target layout may contain a contact and bar-type structures for the purpose of device fabrication process step simplifications. Essentially, two different pattern types need to be OPCed, and in order to perform model based OPC on such a layout, a model for each contact type is generated separately using a best-fit adaptive search method of optical illumination conditions, aerial image diffusion parameter and double Gaussian mask loading terms as a main regression parameters. As it terms out, it is difficult to generate a single model that calibrates to both the contact and bar-type structures and a distinct shift in empirically calibrated threshold levels exists, and a preferred method is to generate models suited for contact and bar-type structures separately in order to improve the model and OPC accuracy. However, each model type needs to be applied at specific locations of a pattern, and a proper OPC recipe for handling biasing of each pattern type is needed as well as correction scheme suitable for each pattern type is required. In this paper, we describe an OPC methodology for merged direct contact layout using a proposed pattern specific modeling and correction technique, and the experimental results indicate that this methodology provides ADI 3s target skew value of 14 nm and ACI 3σ target skew value of 17 nm on a 60 nm half pitch node.

The achievement of current critical feature sizes of 65nm and near future sizes of 45nm and 32nm using 193nm wavelength requires many innovations. A "correction" of a mask design is only as good as its ability to be printed. A new method to account for the various aspects of the lithographic systems has been developed and implemented. It includes a very fast computation of the latent image in the resist including immersion (of water or any other fluid), BARC, a variety of illuminators, acid production and diffusion as well as reaction that delivers soluble resist concentration after PEB (Post Exposure Bake). This goal is achieved by solving the Maxwell equations followed by the reaction-diffusion system typical of currently used chemically amplified resists. Then the printable contour on the printed micrographs (SEM) is extracted and placed on each plane in the resist in order to select the best representative of the process. A sophisticated optimization methodology has been developed and implemented so all parameters are calibrated to yield optimal imaging. The imaging and the corresponding processing are obtained at machine accuracy. Once the simulation system is properly calibrated, becoming a true representative of the imaging in the specific manufacturing environment, the design's hierarchy is modified according to the proximity of each polygon on the wafer. This process enables defect detection and OPC to be done on the modified hierarchy and avoids the need to flatten the design resulting in much faster processing, indeed one that can now be performed on a laptop. OPC using the combination of the "proximity analysis" and the printability simulation is carried out in a few simple steps. Imaged is accomplished in the resist and the printable contour is extracted. The contour is compared to the design and the "CDLOSS" is obtained. The design is segmented according to the proximity details and a movement assignment is determined. This algorithm completes the first iteration. The process is repeated until it achieves the required tolerance or exits with "unable to correct" if OPC fails. The final result is returned to the design-stream in its place in the hierarchy. This OPC system is very fast, stable, and accurate. Explicit examples are given in the figures presented below.

As design rule has decreased, blank type or photo resist, which meets requirement of resolution, has been developed. HT PSM mainly used to pattern small line width has no longer advantages for immersion wafer process. It makes binary mask to be gradually used for mask production. Comparing to HT PSM, the production of binary mask has a relatively simple process. However, we may consider optical density, PR or Cr thickness, etch selectivity, and ID bias related to linearity for applying binary mask below sub-45nm. In this paper, we will compare and analyze difference between actual manufacture and theoretical optic level such as optical density. Finally, based on our experiment, optimal combination of photoresists and blanks which can realize sub-45nm node will be discussed.

Previous work has shown that photomask blank flatness as well as photomask patterning and pelliclization all play an important role in finished photomask flatness. Other work has shown that pellicle mounting techniques and pellicle adhesives play a role as well. In this work, a comparison of the impact of various pellicle types, frame flatness, frame shape and pellicle mounting tools on final photomask flatness will be shown. Pellicles with various adhesives, frame shapes and flatness were mounted on blanks and completed photomasks using several mounting tools and the pellicle induced flatness change was measured. These data will be discussed with the objective of demonstrating the effects of pellicle type and mounting tool on photomask flatness.

As pattern size is shrinking, required mask CD specification is tighter and its effect on wafer patterning is more severe. To enhance the device performance, wafer CD uniformity should be enhanced and controlled by mask global CD uniformity. Mask global CD uniformity usually can be enhanced by mask process and optimal fogging effect correction. To enhance the mask global CD uniformity on mask, resist process and FEC (Fogging Effect Correction), reliable CD measurement tool and methods are necessary. Recently, group CD using OCD(Spectroscopic Ellipsometer) or AIMS(Aerial Image Measurement and Simulation) is used to represent global CD variation on mask. These methods are removing local CD variation on mask. Because local CD variation on wafer is large compared with the effect of local CD variation of mask, global CD uniformity can be measured with suppressed local CD variation [1]. In this paper, local CD variation of mask and wafer is evaluated, and area CD and smoothing methods are used to measure CD on mask and wafer, and the correlation of global CD of mask and field CD of wafer are evaluated. By these methods, CD measurement repeatability can be enhanced to get closer correlation of mask and wafer. Close correlation makes fine CD correction on mask to get better field CD uniformity on wafer. And the repeatability of field to field CD uniformity of wafer is evaluated according to measurement tool of CD-SEM and scatterometry.

We have proposed and modified a model of drying process of polymer solution coated on a flat substrate for flat polymer film fabrication and have presented the fruits through Photomask Japan 2002, 2003, 2004, Smart Materials, Nano-, and Micro-Smart Systems 2006 and so on. And for example numerical simulation of the model qualitatively reappears a typical thickness profile of the polymer film formed after drying, that is, the profile that the edge of the film is thicker and just the region next to the edge's bump is thinner. Then we have clarified dependence of distribution of polymer molecules on a flat substrate on a various parameters based on analysis of many numerical simulations. Then we did a few kinds of experiments so as to verify the modified model and reported the results of them through Photomask Japan 2005 and 2006. We could observe some results supporting the modified model. But we could not observe a characteristic region of a valley next to the edge's bump of a polymer film after drying. After some trial of various improved experiments we reached the conclusion that the characteristic region didn't appear by reason that water which vaporized slower than organic solvent was used as solvent. Then, in this study, we adopted organic solvent instead of water as solvent for experiments. As a result, that the characteristic region as mentioned above could be seen and we could verify the model more accurately. In this paper, we present verification of the model through above improved experiments for verification using organic solvent.

In photolithography, haze prevention is of critical importance to integrated circuit chip manufacturers. Numerous studies have established that the presence of ammonia in the photolithography tool can cause haze to form on optical surfaces resulting in permanent damage to costly deep ultra-violet optics. Ammonia is emitted into wafer fab air by various semiconductor processes including coating steps in the track and CMP. The workers in the clean room also emit a significant amount of ammonia. Chemical filters are typically used to remove airborne contamination from critical locations but their lifetime and coverage cannot offer complete protection. Therefore, constant or periodic monitoring of airborne ammonia at parts-per-trillion (ppt) levels is critical to insure the integrity of the lithography process. Real time monitoring can insure that an accidental ammonia release in the clean room is detected before any optics is damaged. We have developed a transportable, highly accurate, highly specific, real-time trace gas monitor that detects ammonia using Cavity Ring-Down Spectroscopy (CRDS). The trace gas monitor requires no calibration gas standards, and can measure ammonia with 200 ppt sensitivity in five minutes with little or no baseline drift. In addition, the high spectral resolution of CRDS makes the analyzer less susceptible to interference from other gases when compared to other detection methods. In this paper we describe the monitor, focus on its performance, discuss the results of a careful comparison with ion chromatography (IC), and present field data measured inside the aligner and the reticule stocker at a semiconductor fab.

Haze generation has been serious issue on wafer lithography process, as illumination wavelength become shorter with 248nm and 193nm. Several published papers have been reported that ammonium and sulfate residual ion on mask surface is major source of haze generation. These ions are come from conventional photomask cleaning process. PKL have been studied new cleaning process to minimize haze generation and found cleaning process condition. Also, PKL found that residual ammonium ion is major source of haze generation than residual sulfate ion. New cleaning process improved residual ammonium ion concentration to less than 45 ppb from 900 ppb with conventional RCA cleaning. And illumination doses generating haze have been tested on five residual ammonium ion, 1500 ppb, 900 ppb, 160 ppb, 70 ppb, 45 ppb, respectively. In house designed Haze Acceleration Test Bench (HATB) was used to expose masks. Haze were not generated until from 25 kJ to 100 kJ, on 160 ppb to 45 ppb of ammonium ion concentration, respectively. And the residual of sulfate ion and its haze generation dose did not correspond. Residual ammonium ions need to be controlled tightly than sulfate ion. PKL concentrated on minimizing ammonium residual with new cleaning process and found the optimized cleaning process for preventing 100kJ of cumulative energy on ArF embedded attenuated PSM (EAPSM).

The crystal growth and haze formation on the reticle continue to be significant problems for the semiconductor industry. Recently, a pattern size has gradually reduced to enhance the integration of semiconductor device. As minimum linewidth has shrunk, the exposure wavelength has also progressively shrunk. The exposure wavelengths have been reduced progressively from g-line (436 nm), i-line (365 nm), KrF (248 nm), to ArF (193 nm). However, expose wavelength shrink caused some serious problems. One of the problems to be solved is growing defect in the reticle during the process. This growing defect on the reticle is called the haze. The haze is formed on both sides of the reticle, on the quartz side of the mask and on the chrome side of the mask. In this investigation, we varied the local haze defect size and the characteristics of the haze defect. And we get the critical dimension and the exposure latitude variation as the haze transmission changes and the haze phase shifts.

This paper presents an experimental study of resist heating effect in mask making with a variable shaped electron beam mask writer. Experiments were performed at current densities of 40 and 80 A/cm² on mask blanks with a chemically amplified resist. At these levels of current density, the critical dimension change due to resist heating effect was obvious. The critical dimension change was reduced with a checkerwise writing method, in which sub-fields were arranged in main fields in an alternate fashion so that the average incoming heat per unit area due to beam exposure could be reduced. The reduction factor was 2 or more.

The optical lithography still remains to be the mainstream coupled with RETs (resolution enhancement techniques) because of the various and serious difficulties other NGL candidates (Electron beam direct writing, EUV and etc.) are facing now. Development of OPC have made pattern data complexity large so that increasing rate of pattern data volume is higher than the number of transistors in a chip. We studied key issues of development of mask writer especially for throughput.

Heating effect was evaluated for EBM-6000 which is operated at high current density of 70A/cm² and acceleration voltage of 50kV. FEP171 as widely used for current productions and lower sensitivity resists are tested. Lower sensitivity resist is one of key items to achieve highly accurate Local critical dimension uniformity (LCDU) because of shot noise reduction. CD variations in experiment are compared with simulated temperature changes induced by heating effect. Then, the ratio, ΔCD/ΔT, is found mostly constant for every resist, 0.1 nm/C°. Writing conditions are estimated to meet CDU spec of hp45 generation for a worst case pattern, i.e. 100% density pattern. For FEP171, the maximum shot size of 0.85 μm shot size at 2pass writing mode is sufficient. It should be reduced to 0.5 μm at 2pass writing mode for every lower sensitivity resist. When 4pass writing mode is used, the maximum shot size of 0.85 μm is available. Writing conditions and writing time for realistic patterns are also discussed.

Particle beams with collimated discrete charged carriers such as electrons have been employed to lithographically transfer design patterns onto the photoresist for fabrication of devices, such as photomasks. In this paper, we use a single standard deviation σ of total blur based on Gaussian convolution kernel to address the limit of ebeam lithography, where the total blur is constituted of several mechanisms, including space charge effect within the ebeam, shot noise, resist diffusion, and photoacid fluctuation, etc. Based on the Gaussian blur imaging formalism including both electron forward scattering and backward scattering, we derive a fundamental principle based analysis to address the patterning resolution limit, local pattern density (LPD) dependent critical dimension (CD) proximity bias, CD non-linearity, image edge-slope, 2D corner pull back and 2D touch corner structures. Assuming a minimum normalized image log slope of NILS >= 1 across all LPD is required for high volume manufacturability, the requirement of maximum total blur can be derived as σ≤CD/2.4 for a given exposed feature size targeted to pattern. The objective of this paper is to establish a predictive model with simplicity for fundamental limit of ebeam lithography, and accordingly to define the requirement of blur reduction for meeting technology roadmap spec. The key emphasis of this paper is to highlight that mask patterning capability is becoming resolution limited with equipment and material available today. This is an inflection point! An integrated plan for total blur reduction is urgently needed for ebeam lithography to continue enabling technologies moving beyond 45nm and 32nm nodes.

The tight MTT control is required for the mask process of sub-50nm design node due to the complex OPC and insufficient process margin. The MTT below 5nm is already required for the critical layers. Below 4nm is required for sub-50nm node. In the viewpoint of this requirement, the MTT control is important for the mask fabrication. According to the shrinking design node, the linearity is the main issue to satisfy MTT required. In the electron beam (ebeam) lithography, the linearity results are strongly related to the resolution of the mask process. Isolated and dense patterns have the different linearity behaviors due to the different contrast mainly caused by the backward scattering contribution and develop process. Because of this reason, the conventional method of proximity effect correction (PEC) optimization is unlikely to satisfy the MTT requirement. New PEC optimization is necessary for sub-50nm node. In this report, new PEC optimization method is proposed. This method reduces the PEC error of conventional optimization method known as a few nm. Because of the linearity, the error of conventional PEC optimization is amplified according to the shrinking design. Therefore, the PEC error of conventional method is larger than the MTT requirement for sub-50nm node. This new method is designed to overcome this problem. It takes into account for the properties of each layer. Based on the analysis of composition of each layer, the different PEC optimization to fit the each layer and design node is applied. It is able to be applied for the mask fabrication of sub-50nm memory device. The improvement of MTT is achieved by the reduction of the PEC error with new PEC optimization.

Mask metrology has long been separated into critical dimension (CD) vs. pattern placement (Registration) in terms of both the parametric definitions as well as measurement techniques applied. The combined effect of measured CD and placement errors on mask-to-mask overlay (OL) is hard to model let alone calculate in definitive terms. As device size continues to shrink, novel lithography solutions being considered for 45nm technology node and beyond such as double exposure and patterning techniques are projected to tighten the overlay requirement much faster than originally anticipated. Electron optics is generally the preferred solution for small feature size in-die sampling by virtue of its high image resolution, measurement precision, low cross-field distortion and absence of tool induced shift. In this paper we propose to examine and identify the key elements of a new approach in applying electron optics to a mask metrology system that combines CD and pattern placement. We will then present the results from our experiments with a prototype wide field scanning electron microscope (WFSEM) using reticle with optical proximity correction (OPC) features.

A scanning probe microscopy is applied to measure high adhesive energy between Cr or MoSi patterns and quartz substrates by using probes with high stiffness cantilevers. Line patterns with the widths of ~100 nm are peeled from the interface by strain energy stored in the probe, and no residue was observed after peeling. The strain amount has good linear relationship with sensor outputs, and is quantified as a displacement of cantilevers. As a measurement result, adhesive energy of MoSi patterns on the substrate is larger than that of Cr patterns. In addition, adhesive energy of line patterns is sensitive to the pattern width which is parallel side to scan direction, and decreases with pattern width reduction. The method is effective to measure strong adhesion, like chemical bonds, of micro patterns, and will contribute process development for micro fabrication in photomask and wafer fields.

Critical Dimension uniformity (CDU) is one of the most critical parameters for the characterization of photomasks. For years the understanding was that CDU describes a rather random fluctuation of the CD across the mask. With more advanced CD tools and mask processes the local short-range CD variation (on a length scale of micrometre) can be distinguished from the global CD signature (typically on a length scale of centimetre). Recent developments in the pattern generator sector allow correcting for such global CD signatures. This triggers the current challenge to find stable methods to characterize the global signature of photomasks. In our work we present matching results of a technique that calculates the CD signature using exponentially weighted surrounding points. We investigated different CD SEM tools of different technology generations. We show that our method allows determination of the CD signature independently of the measurement tool with low uncertainty and moderate measurement effort. This holds even true when the CDU value is mainly dominated by the measurement error. Thus our method provides a tool to extend the utilization of older generation metrology tools as well as the possibility to improve the measurement capability for CD signature of current tools.

The photomask is a critical element in the lithographic image transfer process from the drawn layout to the final structures on the wafer. The non-linearity of the imaging process and the related MEEF impose a tight control requirement on the photomask critical dimensions. Critical dimensions can be measured in aerial images with hardware emulation. This is a more recent complement to the standard scanning electron microscope measurement of wafers and photomasks. Aerial image measurement includes non-linear, 3-dimensional, and materials effects on imaging that cannot be observed directly by SEM measurement of the mask. Aerial image measurement excludes the processing effects of printing and etching on the wafer. This presents a unique contribution to the difficult process control and modeling tasks in mask making. In the past, aerial image measurements have been used mainly to characterize the printability of mask repair sites. Development of photomask CD characterization with the AIMS^TM tool was motivated by the benefit of MEEF sensitivity and the shorter feedback loop compared to wafer exposures. This paper describes a new application that includes: an improved interface for the selection of meaningful locations using the photomask and design layout data with the Calibre^TM Metrology Interface, an automated recipe generation process, an automated measurement process, and automated analysis and result reporting on a Carl Zeiss AIMS^TM system.

In the semiconductor process field, the control of the critical dimension (CD) is a major task, especially in the processes of mask manufacturing and wafer exposure. One of the difficult problems is that sometimes the linewidth variation on wafer is out of specification even though the linewidth on mask is in specification. The linewidth discrepancy may come from the process control during the chrome film etching, which will influence the sidewall profile of the chrome film pattern. The investigation begins with the analysis of the cross-section of the masks used in the 130-nm technology node regarding the angular variation of the profile. Through the simulation done with AIMS fab 248 exposure system, the optical energy distribution on the photoresist, affected by the sidewall angular variation of the mask, is analyzed with the intensity distribution across the simulated exposure images. The result enables us to establish the process window of the exposure latitude and the depth of the focus (DOF) for the acceptable linewidth variation (less than 4 nm.) The established process window can help the engineers to avoid the linewidth discrepancy between the wafer and the mask, even with the inevitable chrome sidewall angular variation of the mask.

Transmitted Light (ddT or dbT) pattern inspection and STARlight-2^TM (SL2) contamination inspection are widely employed by mask makers in order to detect pattern and contamination defects on photomasks during the mask inspection process. However, such an approach needs a two-pass inspection to detect pattern defects and contamination defects separately. In this paper we introduce the 'Fast Integrated T+R and SL2' capability and investigate the properties of this combination of Transmitted (T) and Reflected (R) light inspection on die areas and STARlight-2^TM(SL2) on scribe areas. 'Fast Integrated T+R and SL2' has the capability to reduce a two-pass inspection to a single set-up and single pass inspection resulting in a substantial saving of inspection time. In addition to a throughput enhancement, 'Fast Integrated T+R and SL2' is able to compliment the pattern T inspection by providing additional sensitivity to detect challenging defects. During this study we collect and analyze inspection data on a critical layer provided by the Advanced Mask Technology Center. Compared to the 2-pass individual mode pattern T and contamination SL2 inspections, a single scan 'Fast Integrated T+R and SL2' demonstrates the capability to capture additional real defects, improves reticle inspectability and first time success rate, and results in a significant enhancement in productivity. Based on empirical data collected in this study, the Fast Integrated T+R and SL2 inspection is able to improve inspection throughput approximately 45% at P90.

As the photomask design rules continue to shrink towards 45nm and below, the defect classification criteria is becoming more challenging to be set accurately. Pattern fidelity issues and masks defects that were once considered insignificant or merely nuisances are now yield-limiting. On the other hand, there are still cases of small defects captured during reticle inspection but will not print on the wafer. In addition, in a production setting environment it is critical to ascertain quickly and efficiently the true lithographic effect of reticle defects in order to avoid yield and cycle time impacts. As a starting point, it is best to inspect the reticle at the highest sensitivity to find all defects and anomalies. From there, fast and efficient means to sort and prioritize defects are necessary for inspection operators' and engineers' convenience. Then, it is critical to model all the defects accurately for their lithographic impact. Finally, an accurate lithography-based set of reticle defect disposition criteria can be developed for the manufacturing process flow. The focus of this study is on contact or hole patterns since the issues regarding capture of defects on such patterns are typically more complex than the ones on line and space patterns. The intent is to assess and devise defect disposition criteria for contact hole layers utilizing KLA-Tencor's 5X6 DUV inspection system with both standard die-to-die and Litho2 algorithms and the Automated Mask Defect Disposition (AMDD) system. AMDD lithographic printability results will be compared to AIMS results and printed results on wafer.

The application of aggressive optical proximity correction (OPC) has permitted the extension of advanced lithographic technologies. OPC is also the source of challenges for the mask-maker. Sub-resolution features, small shapes between features and highly-fragmented edges in the design data are difficult to reproduce on masks and even more difficult to inspect. Since the inspection step examines every image on the mask, it is required to guarantee the total plate quality. The patterns themselves must be differentiated from defects, and the ability to recognize small deviations must be maintained. In other words, high inspectability at high defect sensitivities must be achieved simultaneously. This must be done without restricting necessary OPC designs features. Historically, transmitted light has been deployed for mask pattern inspection. Recently, the inspection challenge has been both enhanced and complicated by the introduction of reflected light pattern inspection. Reflected light reverses the image contrast of features, creating a new set of design limits. This paper introduces these new reflected inspection limits. Multiple platform capabilities will be incorporated into the study of reflected and transmitted inspection capability. The benefits and challenges of integrating a combination of transmitted and reflected light pattern inspection into manufacturing will be explored. Aerial Image Measurement System (AIMS) analysis will be used to help understand how to leverage the enhanced inspection capability while avoiding unnecessary restrictions on OPC.

The advent of device miniaturization necessitates sub-half-micron features delineated on reticles where photomask quality, more so than ever, exerts remarkable yield impact on 65 nm node and below. The introduction of advanced reticles considerably augments the mask error enhancement factor (MEEF) in the non-linear regime ensuing aggressive OPC features. The increased MEEF leads to tightened defect capture criteria, in which many of the previously insignificant defects become of interest and may have substantial yield impact. To provide desired sensitivity, a high resolution inspection is a must; it also effectively monitors mask reliability. However, the productivity of such inspection greatly depends on defect disposition efficacy in sorting out critical defects from the large population detected on contaminated masks [1-3]. Anchoring high resolution reticle inspection, wafer fabs are in a relentless pursuit of optimal defect disposition method to meet the throughput demand. In particular, progressive defects or haze, induced by repeated laser exposure, continue to be a source of reticle degradation threatening device yield. Early detection of these defects to circumvent the printability impact becomes vitally important yet challenging. In addition to its size, the defect criticality also largely depends upon defect optical transmittance, residing surface, its proximity to a printing pattern as well as lithography parameters such as NA and sigma [4-6]. A MEEF-driven lithographic detector named "Litho3" has been designed that can be used run-time during mask inspection to effectively group the critical defects into a single bin based on their potential yield impact. The coordinates of these critical defects, identified by the above Litho3 detector, can then be transferred from reticle to wafer and subsequently subject to printability validation, upon which defective sites can be analyzed thoroughly on reticle or wafer review tools. Such capability reduces inspection cycle time by improving defect disposition efficacy, also assists in determining lithography process window and a further comprehension of defect progression mechanism.

IC manufacturing fabs are experiencing mask reliability issues caused by progressive mask defects, such as crystal growth, haze and etc. with the increase of the usage of DUV, especially 193nm lithography on 90nm technology node and beyond. 193nm lithography has triggered an increasing demand for mask re-qualification in those manufacturing fabs which process 90nm technology node wafers in mass production. Due to dramatic increase in re-qualification demand, the capacity of mask inspection becomes constrain of the manufacturing output. In this paper authors employed widely used KLA SLF inspection systems and investigated inspection scan modes (Fastscan mode and Normal scan mode) and algorithms to optimize recipes on STARlight. Economically and practically, it is important for wafer fabs to optimize mask inspection recipes and improve throughput in order to extend the capacity of mask inspections without additional equipment investment. The Fastscan mode has the capability to move reticle stage as fast as twice of the Normal scan mode in x-direction resulting in a substantial saving of inspection time. Even faster stage move causes slightly reduction on the sampling of contamination defects, the overall defect inspection maintains the same quality as the Normal scan mode in terms of early warning of mask re-qualification. During the study we collect and analyze inspection data on two production masks and a standard test mask Orion5B. Based on empirical data collected in the study, the Fastscan inspection mode is able to reduce inspection time approximately 28% to 38% at P150.

Recently, extremely-high-quality-quartz substrates have been demanded for advancing ArF-lithography. HOYA has developed a novel inspection method for interior defects as well as surface defects. The total internal reflection of the substrate is employed to produce an ideal dark field illumination. The novel inspection method can detect a "nano-pit" of 12nm-EDS, the Equivalent of the Diameter of a Sphere (EDS). It will meet the sensitivity for 32nm node and beyond. Moreover, a type of unique defect is detected, which induces Serious Transmittance Error for Arf-LiTHography. We call it the "STEALTH" defect. It is a killer defect in wafer printing; but it cannot be detected with any conventional inspection in the mask-making process so far. In this paper, the performance of the novel inspection method for quartz substrates and the investigation of "STEALTH" are reported.

Recently, technologies of ArF laser exposure tools and alternating phase shifting masks (Alt-PSM) are expected to be used in actual production. To utilize such newly developed technologies, it is inevitable to develop a mask inspection technology to check them properly. But it is currently difficult to check them precisely because sufficient image contrast is hard to obtain with any conventional mask inspection tools. It is not well understood whether we can get sufficient sensitivity with conventional optical setups and wavelength with the assistance of some kind of resolution enhancement techniques (RET), or we should move toward inspection using revolutionary new optics or shorter inspection wavelength. To study precisely the sensitivity of inspection optics for common types of defects, we have made a captured image simulator based on the RCWA (Rigorous Coupled Wave Analysis) method with which we can take into account the effect of the three-dimensional structure of a mask. We tried to calculate captured images for some mask structures at two different wavelengths, namely 199 nm and 257 nm. We made certain that no significant differences were observed for larger scale defects, but that a considerable difference of image contrast was observed for small scale defects around 50 nm in size. Thus we confirmed that this simulator is effective for evaluating and designing optical systems of mask inspectors, in order to achieve a high sensitivity for the detection of small defects in Alt-PSMs.

Although photomask defect repair tools based on FIB, AFM and pulsed laser are mainly used in current production lines, there is a possibility they will not meet the requirements of 45nm generation photomasks. The EB repair tool is one of the candidates that has a possibility of meeting those requirements. The EB repair tool, MeRiT-MG^TM, has already been announced by Carl Zeiss GmbH. The basic performance of this tool has been reported.¹⁾ Recently MoSi mask is most commonly used in leading edge devices, and defects are mainly opaque type. For this reason, the performance of EB-repair tool for MoSi etching should be investigated. In this paper, we will report the evaluation results of MeRiT-MG^TM and consider whether this tool has a possibility of meeting the requirements of 45nm generation photomasks. In order to evaluate the performance of MeRiT-MG^TM, we prepared 180nm half pitch line & space pattern of ArFatt. PSM with programmed defects. These programmed defects are not only simple extrusion shape but also of various shapes and sizes. By using these defects, we made practical experiment which would happen in real production line.

In this paper we describe the early stages of introduction of the inspection and metrology capabilities for the large area mask repair tools. Commercially available MRT platform was used as a basis for integration of defect repair, metrology, review, inspection, and verification functions into a single MiRT prototype system. This system was designed for large area LCD/PDP photomasks of Generation 7 and beyond. Advanced DUV femtosecond laser technology was developed for repair of both clear and opaque defects on Chrome-on-Glass masks using laser CVD and laser ablation. Specifics of the system design and architecture is discussed. Laser processing module was based on the projection optics with imaged aperture. Image formation in such optical system is reviewed and outcome of the computer simulation is compared with the experimental data. For the first time, we report results of the feasibility study of grayscale photomask repair using laser CVD technology. By carefully controlling process parameters, we were able to deposit films with different thickness and therefore variable transmittance. We also discuss die-to-database inspection of half-tone masks and capabilities of the integrated metrology and review of the repaired photomask sites. Proprietary die-to-database inspection and verification algorithms combined with distributed super-fast computer architecture allowed effective process control with accurate, repeatable, and timely measurements. Different subsystems that enable integration of repair, metrology, and inspection functions into the MiRT system are discussed.

Recently, mask design has been becoming more complex with the increase of data volume. Therefore, it requires more functionality and portability in the mask specification and layout definition for the efficient data handling together with industry standard. SEMI-P10 order format has universal layout definition for the all sorts of mask specifications. We expect OASIS^TM (Open Artwork System Interchange Standard; SEMI standard P39) instead of conventional GDS-II to come into wide use as a more compressive stream format for 45nm node and beyond. The OASIS format is suitable for the enormous pattern file size and sub-nanometer design grid. Although SEMI-P10 is convenient to achieve all of our requirements, its complete definition is very complicated and is difficult to set up full parameters in the primary stage of mask design for production chips. In this work, we focused on minimum syntax of the chip location information from portion of SEMI-P10. And we define P10-JOBDECK as a subset of whole SEMI-P10 regulations. So, by use of P10-JOBDECK and OASIS data format, we have built up the new data handling infrastructure such as data file transfer and pattern layout viewing for the high-end mask manufacturing. In this system, the coordinates of P10-JOBDECK are described in 4X image with mirror inversion and tone reversal parameters. We use 1X coordinates in P10-JOBDECK for the pattern data files because they are the dimensions familiar to the designer, and the transformation for the mask shop is handled automatically. This style is effective for shortening the data conversion time and preventing mishandling of data. We also developed the additional viewer functions of HOTSCOPE® to confirm the pattern layout on the digital display. It is possible to add mask DFM information (design information for mask manufacturability) by the extension to the full SEMI-P10 syntax and by the use of built-in OASIS properties in the future. In this paper, we will discuss the practical application of P10-JOBDECK and the performance results of HOTSCOPE.

The OASIS (Open Artwork System Interchange Standard) format is a new standard format for describing LSI layout data and it has begun to be used for photomask data. One of the greatest features of OASIS format is its conciseness of expressing pattern data and it has been proven that the size of GDS2 files can be significantly reduced down by converting them to OASIS format. It is widely believed that OASIS will replace the position of GDS2 format which is currently most frequently used. In general, OASIS has two aspects for the mask industry. One is OASIS format as a new replacement of GDS2. The other is OASIS.VSB, which is a unified format to be defined for the description of fractured EB data. However, the mask industry has not shifted completely into OASIS and sometimes software operation for both OASIS and GDS2 is required. In the environment of OASIS and GDS2 mixture, bi-directional data conversion between OASIS and GDS2 is a key issue. When GDS2 data is converted to OASIS format, the file size always gets smaller and there is no file size problem. But when OASIS data is converted to GDS2 format, the file size can be more than one hundred times larger than the OASIS file, which sometimes causes hard disk space problems. In order to cope with this problem, we have developed a file size estimation tool for OASIS to GDS2 conversion. The name of the tool is "o2gest" and it is a member of SmartOASIS, which provides comprehensive practical functions to enable easy transition of data processing flow from conventional GDS2 or EB formats to OASIS. The processing speed and the calculation accuracy is a key issue for an estimation tool.

Photomask pattern writer requires high-speed data processing that is conducted concurrently with the variable shaped beam (VSB) writing. As input electron beam (EB) mask data, trapezoid data format is generally used for EB writing because of the easier handling than polygon data format. Recent years, volume of photomask pattern data is growing as the increase of pattern density that is caused by additional various subsidiary patterns of optical proximity correction (OPC). OPC in design rules of 65nm and below is getting approximately 1.5 times more complex than that in the former generation, which increases the photomask pattern data volume approximately 3 times larger. VSB writing time is accurately estimated by counting the total number of "shots" which are primitive figures generated in the data processing of EB writer from the trapezoid patterns in EB mask data. However, no feedback and layout modification can be taken to LSI designs and OPC, even though problems regarding mask manufacturability such as explosion of EB writing time is recognized after starting EB writing process. We developed a simulator that estimates the number of "shots" in VSB EB writing by original shot division method using design data GDSII instead of EB mask data. This simulator outputs total counts and density map of shots of EB writing in photomask layout as well as chip layout in a short time using multi-processing. We can use this software as a core function in our Mask-DFM solutions offering to LSI designers and CAD engineers in order to estimate mask manufacturability before they finish mask data tape-out, and this work can reduce cost and improve TAT in mask manufacturing.

In the UDSM regime of 65 nm and below, a majority of mask layers require Resolution Enhancement Techniques (RET) to enhance their printability on the wafer. The RET has a huge amount of impact on the layout data both in terms of size and the polygonal data characteristics. The Optical Proximity Correction (OPC) step would reduce the original layout hierarchy by a large extent. Moreover, OPC would either add a large number of geometries to the layout data or would split the original edges in the layout geometries into segments. As a result, the size of the layout data file would increase manifold which could be several hundreds of gigabytes for a single mask layer. The growth in layout data size along with more complex polygons introduced during OPC necessitates that the fracturing tool produce higher quality fracturing with less turn-around-time (TAT) during Mask Data Preparation (MDP) as well as actual mask-write by the EB machine. The VSB (Variable Shaped Beam) machine differs from traditional raster based e-beam machines in many ways. The VSB machine writing time as well as the quality of the masks written by it is significantly affected by the quality of fracturing compared to a raster based mask writer. The two requirements, namely, of reducing the TAT for MDP and increasing the quality of the mask written by mask writer usually counteract with each other. In this paper, we propose a scheme that addresses both the issues.

We consider a memory device that is printed by double patterning (litho-etch-litho-etch) technology wherein positive images of 1/4-pitch lines are printed in each patterning step. We analyze the errors that affect the width of the spaces. We propose a graphical method of visualizing the many-dimensional process-window for double patterning. Controlling the space-width to ±10% of half-pitch is not possible under the worst combination of errors. Statistical analysis shows that overlay and etch bias are the most significant contributors to the variability of spaces. 3σ[space-width] = 17% and 11% of nominal space can be achieved for 3σ[Overlay] = 6 nm and 3 nm, respectively, for a 40-nm half pitch array printed using NA=0.93.

The upcoming 45nm and 32nm device generations will continue the familiar industry lithography trends of decreased production K1 factor, reduced focus error tolerances and increased pattern density. As previous experience has shown, small changes in the values of lithographic K1, focus tolerance and pattern density for the process-design space can lead to large required changes in OPC and RET solutions. Therefore, significant improvements in utility and speed are needed for these new device generations. In this paper we highlight significant new functionality and performance capabilities using existing Field-based OPC and RET methods. The use of dense grid calculations in Field-based methods is shown to provide a software platform for robust and fast implementation of new model-based RET techniques such as model-based assist feature placement and tuning. We present the performance and capability increases for model-based RET methods. Additionally, we have studied and present the performance of production 45nm generation field-based OPC and RET software across several different multiple-purpose hardware platforms. Significant improvements in runtime (for approximately the same hardware cost) are observed with new general purpose hardware platforms and with software optimization for this hardware.

An accurate process model has always been the key for successful implementation of model-based Optical Proximity Correction (OPC). As CD control requirements become severe at the 45nm and 32nm device generations, process model accuracy requirements become more stringent. In previous generations, certain systematic process and tool fingerprints could be safely ignored. For example, lens apodization and mask pellicle film induced transmission loss, lens vectorial fingerprint(i.e. Jones pupil), illuminator polarization profile, and etc were ignored in conventional OPC modeling approaches. These effects are now playing a more important role in OPC modeling as technology scales down. Using conventional OPC model may lead to under-correction of the design layout during OPC, and this will result in large number of post-OPC layout hot spots which have patterning issues when the OPCed layout is exposed on the scanner. We designed an OPC correction and verification flow which can efficiently capture the post-OPC layout hot spots due to under-correction using traditional OPC model, and this flow further fixes these detected hot spots. Our simulations demonstrated that this proposed flow is able to achieve an OPC performance of 2.25nm CD error range and 0.26nm CD error standard deviation on poly gate layer for 45nm SRAM design. And this validated the efficiency of the proposed flow.

For immersion technology the mask is illuminated under large angles and the features sizes are approaching the illuminating wavelength. At such operating conditions, several publications have shown rigorous diffraction effects having a noticeable effect on the aerial image. For the Kirchhoff assumption, which is commonly employed in lithography simulation, the mask is assumed to be an infinity thin transparency. This assumption implies the diffracted spectrum to be independent of the incident illumination angle and no coupling between polarization states occurs. This work is a fundamental study to deepen the understanding of rigorous off-axis effects for current and future mask technologies. This paper will show simulation studies for standard attenuated- and alternating mask gratings, which look at the diffracted spectrum of a mask grating with respect to polarization orientation and off-axis angle of the illuminating wave.

Coupled eigenmode (CEM) theory is presented and applied to the 3D modeling of a line-space reticle. In this approach, the electric field inside a line-space reticle is described in terms of an orthogonal set of eigenmodes of Maxwell's equations. The diffraction of light by the reticle can then be expressed as a coherent sum of diffraction orders produced by each eigenmode independently. Fresnel transmission, overlap of eigenmodes with diffraction orders and propagation through the mask are shown to be the interactions that determine the complex amplitude of the diffraction orders produced by each mode. CEM is then applied to the cases of a binary mask and an att-PSM under dipole illumination. It is shown that the behavior of contrast with pitch and mask bias is primarily affected by the propagation loss of the eigenmodes, which increases for smaller trench widths. In the case of the binary mask, this attenuation causes one eigenmode to become dominant and the resultant image approaches the perfect imaging of a single eigenmode. In the case of att-PSM, this attenuation causes a detuning of the transmission and phase, and thus, the image contrast is degraded.

The double dipole lithography (DDL) has been proven to be one of the resolution enhancement technologies for 45 nm node. In this paper, we have implemented a full-chip DDL process for 45nm node using ArF immersion lithography. Immersion exposure system can effectively enlarge the process DoF (depth of focus). Combining with dipole illumination can help us to reach smaller k1 value (~0.31) and meet the process requirements of poly and diffusion layers on 45nm node by using only 0.93 NA exposure tool. However, from a full-chip processing point of view, the more challenging question should be: how to calibrate a good model from two exposure and decompose original design to separate mask sets? Does the image performance achieve a production worthy standard? At 45nm node, we are using one-fourth of the exposure wavelength for the patterning; there is very little room for error. For DDL full-chip processing, we need a robust application strategy to ensure a very tight CD control. We implemented an integrated RET solution that combines DDL along with polarization, immersion system, and model based OPC to meet full-chip manufacturing requirement. This is to be a dual-exposure mask solution for 45nm node - X-dipole exposure for vertical mask and horizontal for Y-dipole. We show a process design flow starting from the design rule analysis, layout decomposition, model-based OPC, manufacturing reliability check, and then to the mask data preparation. All of the work has been implemented using MaskWeaver^TM geometry engine. Additionally, we investigated printability for through-pitch line features, ASIC logic, and SRAM cell design patterns. Different circuit layout needs dedicated special OPC treatment. To characterize the related process performance, we use mask enhancement error factor (MEEF), process window (PW), and critical dimension uniformity (CDU) to analyze the simulation data. Since we used the tri-tone Att-PSM, the mask making flow and spec was also taking into consideration. The device electrical performance was examined for production feasibility. We conclude that the DDL process is ready for 45nm node and is well within reach to be used on next generation production environment.

We have much difficulty to control critical dimension (CD) uniformity for contact layer by optical proximity effect correction (OPC) from 65nm node and below. High mask error enhancement factor (MEEF) in contact layer causes much influence to surrounding layout pattern edges, resulting in long turn-around-time (TAT) from numerous iterations. Methods using nominal OPC cause CD uniformity to get worse depending on pattern layout because MEEF is not considered. Some solutions to this problem may be to calculate MEEF at each pattern edge in order to OPC, and then decide final correction value by using the weight of this MEEF, but additional calculation causes more TAT. We have developed a new OPC method that could optimize pattern layout for contact layer with short TAT because no calculation of each MEEF is necessary. We used our new OPC method to 65nm node LSI. With this method, we were able to control CD uniformity and get good results with no hotspots. Our new OPC method is much useful to OPC for 65nm node and below.

Double patterning technology (DPT) is one of candidates to achieve 45nm or 32nm half-pitch and is getting popular as ITRS2006update⁽¹⁾. ITRS2006update specifies the tight specification of image-placement and the difference of CD mean-to target of two masks, and they are also evaluated and reported⁽²⁾. From photomask fabrication viewpoint or just even employing actual wafer exposure experiment, it's much difficult to evaluate actual impact on wafer using DPT. Because what observed on wafer is mixture of not only photomask-property but also exposure's one and new topic of hard-mask process'. In this paper, one evaluation procedure will be proposed using actual two photomasks and the DPT impact on wafer just from two photomasks will be demonstrated. Then the approach of wafer image composing procedure with photomask-SEM image, photomask measurement and exposure simulation will be discussed

The ArF water immersion is one of the most promising candidate technologies for 45-nm node lithography. But it have been predicted that the realization of 32-nm node (minimum half pitch 45nm) is very difficult when using the water immersion of 1.35 NA and single mask exposure. Therefore, some double-exposure technologies are expected for 32-nm node logic device. However, the single mask exposure would be expected because it has very big advantage of short process time and/or cost etc., compared to other double-exposure methods. In this research, we evaluated two NA setting of ArF immersion as the models and the required structure and error budget of photomasks. One is the maximum NA of water immersion (= 1.35) and another is using high refractive index materials with NA of 1.55. The lithographic performance was evaluated for line and space pattern through various pattern pitches with optical proximity correction (OPC). The evaluation items of printing performance are CD-DOF, contrast-DOF and MEEF, etc. The suitable kind of mask and structure are also considered with effect of several kinds of mask topography error. The limit of single mask exposure will be examined by setting the restriction such as minimum half pitch and so on.

As the leading edge semiconductor technology development, the gate critical dimension (CD) shrinks below 90nm. The microlithography capability is limited by the exposure utility. The development of scanner is focusing on low k that is implying that the high NA scanner is the main stream in the future. In addition, the high NA reticle requirement is stricter than previous one. In aspect of mask manufacturing, reducing mask topography effect is one of the various solutions, which is like lower mask blank flatness, should be lower than 1T flatness type or else. Unless the mask flatness, the absorber profile also could be a considerate effect element, which is local topography effect contribution in wafer print window. The main purpose of this study is verifying how much wafer prints window discrepancy between different absorber profiles. The experiment pattern is designed for five kind of MoSi sidewall angle (SWA) on the same mask, which could simultaneously gathers the wafer print window data. In addition, the other purpose is getting exactly the same process condition of five kinds MoSi profile in both mask house and lithography of wafer manufacturing Fab. The mask layout pattern is poly layer of logical 90 nm generation that is more critical among all of lithography and was exposed by 193nm ArF.Then, we offer the effected level between absorber profile and lithography process window. The process window of different SWA pattern will be compare to check the relationship between process windows and mask profile. We also investigate how the profile affects the optical proximity behavior.

Several criteria are applied to optimize the best illumination and bias condition for a layer. Normalized image log-slope (NILS) and mask error enhancement factor (MEEF) are promising candidates to simply decide the optimized condition. NILS represents imaging capability and MEEF represents the mask uniformity influence on wafer image. MEEF has inversely relationship with NILS, but the optimized point of NILS does not exactly coincide with that of MEEF. Besides NILS and MEEF, the depth of focus (DoF) is an important factor for defining the process margin. The process window (PW) is expressed by DoF and exposure Latitude (EL). PW is general parameter used to determine the best lithographic condition. Large EL can be obtained at the condition with good image performance. In order to include mask uniformity effect in PW analysis, the common PW overlapping the final layout with positive and negative biased layouts is adopted. Starting with the minimum NA, sigma and threshold, OPC is performed to satisfy the target layout using aerial image model, and the final OPCed layout is obtained. The positive and negative biased layouts are generated from the final OPCed layout. The bias limit is determined considering mask uniformity. The common PW obtained by overlapping the final layout with positive and negative biased layouts is calculated. Then, NA, sigma and threshold are increased until the maximum values are reached. The common PW at each NA, sigma and threshold value is obtained using the same flow sequence. Comparing among calculated PWs, the NA, sigma and threshold of the maximum PW can be chosen as the best illuminator and bias condition. In this paper, the optimized illumination and bias condition is determined using PW for 60 nm memory device. The process flow is implemented by an OPC tool. By using the OPC tool for the illuminator optimization, the actual layout and multiple monitoring points can be measured. In spite of a large number of calculations, the fast calculation speed can be obtained by using the distributed process.

In this paper, we present the Luminescent's ILT approach that can rapidly solve for the optimal photomask design. We will discuss the latest development of ILT at Luminescent in the areas of sub-resolution assist feature (SRAF) generation, process-window-based ILT and mask rule compliance (MRC). Results collected internally and from customers demonstrate that ILT is not only an R&D tool, but also a tool quickly maturing for production qualification at advanced technology nodes. By enforcing the proper constraints while optimizing the masks, ILT can improve process windows while maintaining mask costs at a reasonable level.

The availability of defect-free masks remains one of the key challenges for inserting extreme ultraviolet lithography (EUVL) into manufacturing. Evidently, the success of the industry's mask blank defect reduction effort will critically depend on the timely availability of defect inspection tools that can find ever smaller defects. The first generation of defect inspection tools enabled SEMATECH's Mask Blank Development Center (MBDC) to reduce mask blank defects to a level sufficient for use in EUV alpha tools. The second tool generation is currently enabling the MBDC to meet EUV pilot line requirements by the end of 2007. However, to meet high volume manufacturing (HVM) mask blank defect requirements for 32 nm half-pitch (hp) patterning, the industry needs a third generation of defect inspection tools. This next EUV inspection tool generation must be able to find defects of ≤ 20 nm on mask blanks with a high capture rate and high blank throughput. In addition, these tools will also need to support extendibility assessments of low defect deposition technologies and the associated infrastructure towards meeting 22 nm half-pitch defect specifications. While visible light inspection is likely to support defect inspection needs for mask substrates over several technology nodes, the industry must explore other options for mask blanks and patterned masks. Evaluating the use of inexpensive printing tools and wafer-based inspection to search for repeating defects must be part of an overall strategy to address mask blank and patterned mask defect inspection.

Temperature of EUV mask surface under inspection laser beam irradiation is modeled and simulated. Various conditions including beam power, beam size, irradiation time, and wavelength are considered. Calculation program for this study has two components: at first, average power passing through the film is calculated from optical properties of materials, and then heat transfer equations are solved using finite difference method. Temperature of multilayer below the absorber depends on the optical properties of absorber film surface. At the wavelength of deep ultraviolet region, temperature of multilayer below the absorber rises higher than in the temperature of multilayer directly exposed to the beam.

EUVL will be a most likely candidate for the next generation lithography beyond 32nm node. The proper material of Extreme Ultraviolet (EUV) mask absorber is crucial. Many researches indicated that tantalum-nitrogen (TaN) and chromium (Cr) are the better candidates. However, these studies mainly focus on the optical performance. Researchers pay little attention to the influence of absorber material on mask fabrication by Electron Beam Lithography (EBL). In this paper, using an EBL module of in house software MicroCruiser, the study of comparison of the influence of TaN and Cr absorber on EUV mask fabrication is presented from the perspective of the backscattering coefficient, the energy deposition of BE in resist, the line edge roughness of patter profile, and the side wall angle of the pattern profile, respectively. An EBL module of MicroCruiser is developed including complex inelastic scattering and relativistic correction of high energy electron which were not considered in previous simulation software of EBL.

Extreme Ultraviolet Lithography (EUVL) is the favourite next generation lithography candidate for IC device manufacturing with feature sizes beyond 32nm. Different absorber layers and manufacturing concepts have been published for the fabrication of reflective EUVL masks. A mandatory step in the EUVL mask making is the patterning of sub 100nm features. The layer composition of such a TaN absorber consists of an anti reflective coating (ARC) on top of a base layer. We investigated the dry etch behaviour of TaN based absorbers with four different top ARC layers. Our focus was to determine a dependency of patterning criteria e.g. etch selectivity, minimum resolution, CD uniformity and linearity on the different ARC layers. Before, the deposition parameters of the top ARC layers have been optimized by SCHOTT Lithotec towards minimum stress and the appropriate reflectance property at the 257nm inspection wavelength. The mask blank exposure was done on a 50kV Vistec SB350 MW variable shaped e-beam writer using a 300nm thick Fuji FEP171 resist film. Our test pattern covered a quality area of 132mm x 132mm and comprised dense/iso line structures and contacts from 60nm-1200nm. Testmasks with the four different TaN based absorbers have been dry etched on an Oerlikon mask etcher III. The dry etch recipe and parameters have been kept constant for the different absorber testmasks. Line and contact hole patterns with a minimum feature size of ~70nm and perpendicular profiles have been realized. CD uniformity on 180nm L&S and linearity measurements on dense and iso features from 100nm-1200nm havbe been carried out. Overall, a TaN based absorber including dry etch process has been developed, able to fulfill the requirements for IC device manufacturing with feature sizes down to 22nm - suitable for EUV-Lithography.

Etching of TaBO/TaBN absorbers on EUVL masks was studied. The self-mask strategy and etch selectivity optimization were used for obtaining the best etch CD performance. Gibbs Energy Minimization was used for determining etch gas selection and product volatility. Calculated results suggest the use of a two-step etch process, i.e. using fluorinecontaining gas to etch the antireflective (AR) layer and using chlorine-containing gas to etch the bulk absorber beneath AR. High selectivity of TaBN-to-TaBO was obtained and the AR hard mask function was proven. By using this method, one EUVL mask can be used many times by selectively exposing portions of a mask during etch. A profilometer was used for etch product characterization and etch CD results were verified by using CD SEM measurement. Optimal conditions developed on the Applied Materials Tetra Mask Etch System by using just one mask gave etch CD bias of 3 nm, etch CD uniformity of <3 nm, excellent sidewall profile, and high selectivity of absorber layer to resist and absorber to buffer layer. Etch effects on the backside chrome coating were also examined. No arcing on the backside during EUVL absorber and buffer etching was identified.

We evaluated the capability of a commercially available DUV system equipped with reflective inspection optics with the shortest inspection wavelength of 199nm in detecting pattern defect on EUVL mask of hp45nm programmed defect pattern. The sensitivity of the system for opaque extension defects for hp45nm node was quite acceptable but for clear extension defects the sensitivity of the system was rather poor. In this paper, the influence of base pattern size on inspection sensitivities for opaque and clear extension defects is discussed.

We have developed a mask protection engineering tool (MPE Tool) that simulates various types of tests during the transfer of a mask or blank in air and in vacuum. We performed mask transfer experiments to investigate particle-free mask handling techniques using the MPE and mask inspection tools. We measured the number of particles accumulated during the transfer of the mask blanks. Less than 0.3 particles were added over a path from a load port (in air) to an ESC chamber (in vacuum) and more than half the particles accumulated appeared during the pumping down and purging steps in the load-lock chamber. Consequently, we consider that pumping down and purging are the most important steps for particle-free mask handling.

Nano-imprint lithography (NIL) has been counted as one of the lithography solutions for hp32nm node and beyond. Recently, the small line edge roughness (LER) as well as the potentially high resolution that will ensure no-OPC mask feature is attracting many researchers. The template making is one of the most critical issues for the realization of NIL. Especially when we think of a practical template fabrication process on a 65mm square format that is going to be the industry standard, the resolution of the template making process showed a limitation. We have achieved for the first time an hp22nm resolution on the 65nm template format. Both line and space patterns and hole patterns were well resolved. Regarding dot patterns, we still need improvement, but we have achieved resolution down to hp28nm. Although so far we cannot achieve these resolution limits of various pattern category at the same time on one substrate, an intermediate process condition showed sufficient uniformity both in lateral CD and in vertical depth. Global pattern image placement also showed sufficient numbers at this stage of lithography development. A 20nm feature (with a pitch of 80nm) showed sufficient imprint result.

Nanoimprint lithography is a candidate for lithography for the hp32nm and hp22nm nodes. Molds or templates for it are being developed on the basis of the process of making phase-shift photomasks. The combination of a 50 kV-VSB (variable shaped beam) EB writer and a chemically amplified resist (CAR) does not have a resolution sufficient for 1X patterning. On the other hand, a combination of a 100 kV-SB (spot beam) EB writer and a non-CAR satisfies the resolution requirement, but this combination leads to an extremely low throughput due to low resist sensitivity. To increase the throughput, we have examined double patterning and double exposure with hybrid use of two different types of writers, a 50 kV-VSB writer, JBX-9000MV, for delineating fine features and a 100 kV-SB writer, JBX-9300FS, for delineating rough features. Overlay accuracy is a key item in such hybrid writing. The results of an overlay accuracy evaluation together with a throughput improvement will be reported in this paper. An estimation of the time for writing a gate layer has given a good example; the writing time for hybrid writing is reduced to about half of the time for 100kV-SB writing. The overlay accuracy for double patterning is found to be 20nm (3σ). However, we are confident that we will be able obtain an overlay accuracy of 10nm (3σ) by improving the image placement accuracy of the JBX-9300FS. An example of double exposure is also shown.