This PDF file contains the front matter associated with SPIE Proceedings Volume 6730, including the Title Page, Copyright information, Table of Contents, Introduction, Conference Committee listing, and the Friday Special Session summary and schedule.

Microelectronics industry leaders routinely name the cost and cycle time of mask technology and mask supply as top critical issues. A survey was created with support from SEMATECH and administered by SEMI North America to gather information about the mask industry as an objective assessment of its overall condition. The survey is designed with the input of semiconductor company mask technologists, merchant mask suppliers, and industry equipment makers. This year's assessment is the sixth in the current series of annual reports. With ongoing industry support, the report can be used as a baseline to gain perspective on the technical and business status of the mask and microelectronics industries. The report will continue to serve as a valuable reference to identify the strengths and opportunities of the mask industry. The results will be used to guide future investments pertaining to critical path issues. This year's survey is basically the same as the 2005 and 2006 surveys. Questions are grouped into categories: General Business Profile Information, Data Processing, Yields and Yield Loss Mechanisms, Delivery Times, Returns and Services, Operating Cost Factors, and Equipment Utilization. Within each category is a multitude of questions that create a detailed profile of both the business and technical status of the critical mask industry.

With the stringent requirements on image placement (IP) errors in the sub-65-nm regime, all sources of mask distortion during fabrication and usage must be minimized or corrected. For extreme ultraviolet lithography, the nonflatness of the mask is critical as well, due to the nontelecentric illumination during exposure. This paper outlines a procedure to predict the IP errors induced on the mask during the fabrication processing, e-beam tool chucking, and exposure tool chucking. Finite element (FE) models are used to simulate the out-of-plane and in-plane distortions at each load step. The FE results are compiled to produce a set of Correction Tables that can be implemented during e-beam writing to compensate for these distortions and significantly increase IP accuracy. A previous version of this paper appeared in the Proceedings of the European Mask and Lithography Conference (EMLC), SPIE, 6533, 653314 (2007). The paper has been updated, retitled, and published here as a result of winning the Best Paper Award at the EMLC.

As part of the technical program in Photomask Japan 2007, we held a panel discussion to discuss challenges and solutions for the double exposure and double patterning lithography technique for 32nm half-pitch design node. 4 panelists, Rik Jonckheere of IMEC (Belgium), Tsann-Binn Chiou of ASML Taiwan Ltd. (Taiwan), Judy Huckabay of Cadence Design Systems Inc. (USA) and Yoshimitsu Okuda of Toppan Printing Co., Ltd. (Japan) were invited to represent each key technical area. We also took a survey from the PMJ attendees prior to the panel discussion, to vote which key technical area they think the challenge exists for the 32nm half-pitch DE/DP lithography. The result of the survey was also presented during the panel discussion. One would intuitively think that by using a DE/DP technique you're relaxing the design rule by 2x, thus for 32nm node it's essentially the 65nm process- you're just repeating it 2 times. Well, not exactly, as identified by the panelists and the participants in the discussion. We recognized the difficulties in the LSI fabrication process steps, the lithography tool overlay, photomask CD and registration, and the issue of data splitting conflict. These difficulties are big challenge for both LSI and photomask manufactures; however, we have confirmed some solutions are already examined by the theoretical and experimental works of the people in research. Despite these difficulties, we are convinced that the immersion lithography with double exposure and double patterning techniques is one of the most promising candidates of the lithography for 32nm half pitch design node.

One of the most important parameters of Attenuated Phase Shift Masks (APSM) is the uniformity of the phase over the active area of the mask. Phase uniformity is an important component of lithographic process window stability. Typically, an APSM blank consists of a quartz substrate upon which a Molybdenum Silicide (MoSi) attenuating film and a Chromium (Cr) film have been deposited to act as a hard mask for the MoSi etch. There are many factors that contribute to phase non-uniformity of the final mask: thickness non-uniformity of the films, non-uniformity of the Cr etch and MoSi etch, and non-uniformity of the MoSi overetch into the quartz substrate. Phase of a completed mask is routinely measured, but quantifying how these individual components contribute to the overall phase non-uniformity is challenging. This report focuses on understanding how MoSi etch contributes to phase non-uniformity. Phase uniformity is compared for three different MoSi etch processes.

As the design rule of the semiconductor circuit shrinks, the specification for photomask becomes tighter. So, more precise control of CD MTT (Critical Dimension Mean to Target) is required. We investigated the CD MTT control of the attenuated PSM (Phase Shift Mask) by additional Cr dry etch. In conventional process, it is difficult to control CD MTT precisely because about 5 factors - Blank Mask, E-beam writing, Resist develop, Cr dry etch, MoSiN dry etch - affect CD MTT error. We designed the new process to control CD MTT precisely. The basic concept of the new process is to reduce the number of factors which affect the CD MTT error. To correct CD MTT error in the new process, we measured CD before MoSiN dry etch, and then additional corrective Cr dry etch and MoSiN dry etch was performed. So, the factors affecting CD MTT error are reduced to 2 steps, which is additional corrective Cr dry etch and MoSiN dry etch. The reliability of CD measurement before MoSiN dry etch was evaluated. The generable side-effect of the additional corrective Cr dry etch was analyzed. The relationship between 'CD shift' and 'additional corrective Cr dry etch time' was found for various patterns. As a result, accurate CD MTT control and significant decrease of CD MTT error for attenuated PSM is achieved.

As mask feature size decreases, etch bias control during Cr and shifter etch becomes more critical factor in Embedded Phase Shifter Mask (EPSM) mask making processes. Since the etching characteristics of the shifter materials, Molybdenum Silicide (MoSi), are sensitive to etching surface condition, Critical Dimension (CD) performance of the shifter layer strongly depends on incoming surface condition from Cr etch. In this paper, lateral etch component of MoSi etch was investigated as a function of various substrate conditions so that a new in-situ plasma treatment was suggested to control the CD bias during MoSi etch. The CD performance was characterized within the surface treatment plasmas and also correlated with some plasma parameters and substrate temperature. As a result, it was found that plasma surface modification could be an in-situ technique to better control the shifter CD in EPSM process and an essential option for redundancy tools in mask production environment.

With the introduction of ArF laser, its high photon energy affects the pellicle degradation in direct. The components outgassed from the damaged pellicle have the effect on the CD variation of reticle. In order to resolve this new inevitable problem, the method of dry gas purge has been proposed among the various solutions recently. Dry gas purge method is generally applied to two applications. It can be applied to a storage environment such as reticle stocker, reticle SMIF pod and reticle library in scanner and to the exposure chamber inside of a scanner during ArF laser exposure phase directly. In this case, it is quite important technologically that which gas is determined as dry purge gas, pure nitrogen or CDA (clean dry air). In this study, the effects of exposure environment on pellicle degradation according to dry purge gas and their mechanism has been investigated to propose strategies and solutions of dry gas purge technology.

As optical lithography is extended for use in manufacturing 45 nm devices, it becomes increasingly important to maximize the lithography process window and enable the largest depth of focus possible at the wafer stepper. Consequently it is very important that the reticles used in the wafer stepper be as flat as possible. The ITRS roadmap requirement for mask flatness for 45 nm node is 250 nm. To achieve this very tight reticle flatness requirement, the stress of each film present on the mask substrate must be minimized. Another key reticle specification influenced by film stress on the mask blank is image placement. In this paper, we will describe the development and detailed characterization of a new low stress Molybdenum Silicide (MoSi) film for use in manufacturing 45 nm node critical level attenuated phase shift masks to be used in 193 nm immersion lithography. Data assessing and comparing the cleaning durability, mask flatness, image placement, Critical Dimension (CD) performance, dry etch properties, phase performance, and defect performance of the new low stress MoSi film versus the previous industry standard A61A higher stress MoSi attenuator film will be described. The results of our studies indicate that the new low stress MoSi film is suitable for 45 nm mask manufacturing and can be introduced with minimal changes to the mask manufacturing process.

The purpose of paper is to investigate the impact of mask blank flatness on critical dimension uniformity (CDU) and depth of focus (DOF) in the wafer printing process with a test pattern designed for 65nm node technology. In this experiment we use 3 test masks with different flatness (0.3T, 0.5T and 1T), and the same test pattern array. The mask flatness was measured with a Tropel® UltraFlat^TM 200, and the focus error is extracted from the CD data of the focus and energy matrix (FEM) analysis. The goal of the study is to quantify the mask flatness influence on the high-numerical aperture (NA) lithographic process.

Critical to the success of imprint lithography and Step and Flash Imprint Lithography (S-FIL^®) in particular is the manufacturing 1X templates. Several commercial mask shops now accept orders for 1X templates. Recently, there have been several publications addressing the fabrication of templates with 32nm and sub 32nm half pitch dimensions using high resolution Gaussian beam pattern generators. Currently, these systems are very useful for unit process development and device prototyping. In this paper, we address the progress made towards full field templates suitable for the fabrication of CMOS circuits. The starting photoplate consisted of a Cr hard mask (≤ 15nm) followed by a thin imaging layer of ZEP 520A. The EBM-5000 and the EBM-6000 variable shape beam pattern generators from NuFlare Technology were used to pattern the images on the substrates. Several key specifications of the EBM-6000, resulting in improved performance over the EBM-5000 include higher current density (70 A/cm²), astigmatism correction in the subfields, optimized variable stage speed control, and improved data handling to increase the maximum shot count limitation. To fabricate the template, the patterned resist serves as an etch mask for the thin Cr film. The Cr, in turn, is used as an etch block for the fused silica. A mesa is formed by etching the non-active areas using a wet buffered oxide etch (BOE) solution. The final step in the template process is a dice and polish step used to separate the plate into four distinct templates. Key steps in the fabrication process include the imaging and pattern processes. ZEP520A was chosen as the e-beam resist for its ability to resolve high resolution images. This paper documents the resolution and image placement capability with the processes described above. Although ZEP520A is slow relative to chemically amplified e-beam resists, it is only necessary to pattern 1/16^th the area relative to a 4X reduction mask. Write time calculations for 1X templates have also been performed, and are compared to 4X photomasks.

Imprint lithography has been shown to be an effective method for the replication of nanometer-scale structures from a template mold. Step and Flash Imprint Lithography (S-FIL^®) is unique in its ability to address both resolution and alignment. Recently overlay across a 200 mm wafer of less than 20nm, 3σ has been demonstrated. Current S-FIL resolution and alignment performance motivates the consideration of nano-imprint lithography as Next Generation Lithography (NGL) solution for IC production. During the S-FIL process, a transferable image, an imprint, is produced by mechanically molding a liquid UV-curable resist on a wafer. The novelty of this process immediately raises questions about the overall defectivity level of S-FIL. Acceptance of imprint lithography for CMOS manufacturing will require demonstration that it can attain defect levels commensurate with the requirements of cost-effective device production. This report specifically focuses on this challenge and presents the current status of defect reduction in S-FIL technology and will summarize the result of defect inspections of wafers patterned using S-FIL. Wafer inspections were performed with a KLA Tencor- 2132 (KT-2132) automated patterned wafer inspection tool. Recent results show wafer defectivity to be less 5 cm^-2. Mask fabrication and inspection techniques used to obtain low defect template will be described. The templates used to imprint wafers for this study were designed specifically to facilitate automated defect inspection and were made by employing CMOS industry standard materials and exposure tools. A KT-576 tool was used for template defect inspection.

A 3D template fabrication process has been developed, which enables the generation of high resolution, high aspect pillars on top of lines. These templates will be used to print both vias and metal lines at once for the dual damascene technology. Due to the complexity of state of the art CMOS designs only a variable shape e-beam (VSB) writer combined with chemically amplified resists (CAR) can be considered for the patterning process. We focused our work especially on the generation of high aspect pillars with a diameter below 50nm and the development of suitable overlay strategies for getting a precise alignment between the two template tiers. In this context we investigated the influence of exposure strategies on the overlay result across the entire imprint area of 25mm × 25mm. Finally, we realized templates according to the MII standard with different test designs and confirmed printability of one of them on a MII tool.

As the design rule has decreased in semiconductor manufacturing, the ITRS roadmap requires significantly tighter critical dimension control. Especially, CD error caused by develop loading become significant in the overall error budget and has approached to over 5nm. It is very difficult to control dissolution product making the change of dissolution rate by chemical flow direction in develop process. These days, the study of develop loading within global area has significantly progressed. However, we will focus on CD error in mid-local area by using a detailed analysis. And we evaluate these phenomenon caused by pattern density difference, called chemical flare. Even though using several developer types, CD error appears at the chip to chip boundary. It is impossible to correct CD error in this area by electron beam correction. Therefore, this paper analyzed about CD error in a value of several tens ~ hundreds nm. In view of develop loading, we will optimize develop process for improvement of CD error.

ALTA4700 DUV laser pattern generator employs chemical amplified resist to get better resolution. The capability of ALTA4700 for 130nm technology node mask production is obviously. Further improvement on ALTA4700 was performed to meet the state-of-the-art mask requirement. System optimization eliminates unusual critical dimension (CD) points and then reduces the range of uniformity. Appropriate post-exposure baking (PEB) temperature gets larger mask printing window and better CD linearity. ALTA4700 incorporate NTAR7 blank with particular dry etch recipe, the mask CD uniformity reduced from 25 to 15nm (range). Good Cr layer profile also obtains.

Positive chemically amplified resist (CAR) is widely used because of its benefit to high resolution in the semiconductor industry. Recent numerous studies have reported that resist pattern error such as resist scum and adhesion fail at the interface between substrate and positive CAR is caused by substrate dependency. Hence resist pattern error must be minimized. In this study we have observed the phenomena at the positive CAR coated mask blanks. And then we applied various surface treatments to the Cr film to minimize resist pattern error. Firstly, resist pattern error was occurred by the substrate dependency in the positive CAR coated mask blanks. We have investigated the root causes of this pattern error, we found that nitrogen radical and OH radical in the Cr film could combine with proton in the positive CAR easily. So various surface treatments were applied to minimize detrimental effects of substrate dependency to the positive CAR. And the behavior of substrate dependency was observed by various analyses to verify the effect of surface treatment method. The results showed that substrate dependency could be controlled by surface treatment in the positive CAR coated mask blanks.

As the specification for photomask becomes tighter, it is strongly demanded for achieving precise CD MTT (critical dimension mean to target) and enhanced defect controllability in photomask fabrication. First of all, it is necessary that reducing the factors of CD MTT error and introducing the reliable method to correct CD error for accurate CD requirement of attenuated PSM (phase shift mask). From this point of view, one of CD correction methods which consist of Cr CD measurement step after resist strip (strip inspection CD: SI CD) and additional corrective Cr dry etch step was developed. Previous SI CD correction process resulted in accurate CD control within the range of CD MTT. However it was not appropriate for defect control due to additional resist processes for selective protection of Cr pattern during CD correction process. In this study, the method for achieving precise CD MTT by correcting CD error without any resist process is investigated. It is not suitable for the CD correction process to control CD MTT precisely that Cr etched resist (etch inspection CD: EI CD) is very vulnerable to E-beam scanning during CD measurement. Otherwise, photoresist after Cr etch selectively shrinks via UV irradiation under ozone (O3) condition, which drives a reduction of CD MTT error as a result of accurate CD measurement (UV-irradiation inspection CD: UI CD). Moreover, it is not necessary any resist process for Cr protection due to UV irradiated resist as enough for a etch barrier. It is a strong advantage of novel CD correction method. This strategy solves the problems such as both CD measurement error on the EI CD correction method and defects originated from resist process on the SI CD correction method at once. For the successful incorporation of UI CD correction method, several items related with CD should be evaluated: accuracy and repeatability of CD measurement under UI CD, control of CD MTT and CD uniformity, additional corrective etch bias for UI CD, independence of corrective Cr etch process from UV irradiated resist, isolated-dense CD difference,.. etc. In this paper, strategy of design for the progressive CD correction method for defect-free photomask and process details will be discussed.

As the tolerances for photomask Critical Dimension (CD) become smaller, more focus has been placed on all processes and their contribution to final mask CD. One key contributor to final mask feature dimensions is the resist develop process and it is the focus of this work. We have studied different resist develop methods to determine optimum process conditions for 45 nm critical photomasks. In searching for the optimum conditions, special consideration was made to study the influence of pattern density effects. We focused on variations in the develop nozzle. Results of the nozzles' impact on pattern density and long range pattern density effects will be presented, for both positive and negative chemically-amplified resists. A characterization of the repeatability of the processes will be presented as well.

We have developed a new method of accurately profiling a mask shape by utilizing a Mask CD-SEM. The method is intended to realize high accuracy, stability and reproducibility of the Mask CD-SEM adopting an edge detection algorithm as the key technology used in CD-SEM for high accuracy CD measurement. In comparison with a conventional image processing method for contour profiling, it is possible to create the profiles with much higher accuracy which is comparable with CD-SEM for semiconductor device CD measurement. In this report, we will introduce the algorithm in general, the experimental results and the application in practice. As shrinkage of design rule for semiconductor device has further advanced, an aggressive OPC (Optical Proximity Correction) is indispensable in RET (Resolution Enhancement Technology). From the view point of DFM (Design for Manufacturability), a dramatic increase of data processing cost for advanced MDP (Mask Data Preparation) for instance and surge of mask making cost have become a big concern to the device manufacturers. In a sense, it is a trade-off between the high accuracy RET and the mask production cost, while it gives a significant impact on the semiconductor market centered around the mask business. To cope with the problem, we propose the best method for a DFM solution in which two dimensional data are extracted for an error free practical simulation by precise reproduction of a real mask shape in addition to the mask data simulation. The flow centering around the design data is fully automated and provides an environment where optimization and verification for fully automated model calibration with much less error is available. It also allows complete consolidation of input and output functions with an EDA system by constructing a design data oriented system structure. This method therefore is regarded as a strategic DFM approach in the semiconductor metrology.

Load of photomask manufacturing for the most advanced semiconductor devices is increasing due to the complexity of mask layouts caused by highly accurate RET or OPC, tight specification for 2D/3D mask structures, and requirements of quick deliveries. The mask cost becomes a concern of mask users especially in SoC businesses because the number of masks required throughout the wafer process is almost the same for each product regardless of the variety in production volume when a unified platform is applied to the designs. Shares of mask cost within total production cost cannot be ignored especially in small volume SoC products. DFM (design for manufacturing) is inevitable in a mask level as well as in a wafer level to solve the cost problem. "Mask-DFM" is a method to decrease the burden of mask manufacturing and to improve the yield and quality of masks, not only by modification of mask pattern layouts (design) but also all other things including utilization of designer's intents. We have developed our Mask-DFM system called "MiLE", that calculates mask-manufacturing workload through layout analyses combining information of mask configuration, and visualizes the consequence of Mask-DFM efforts. "MiLE (Mask manufacturIng Load Estimation)" calculates a relative index which represents the mask manufacturing workload determined by factors of 1) EB writing, 2) defect inspection/repair, 3) materials and processes and 4) specification. All the factors are computed before tape-outs for mask making in the system by the following methods. To estimate EB writing time, we applied high-throughput simulator and counted the number of "shot", minimum figure unit in EB writing, by using post-OPC layout data. Mask layout that caused troubles and extra load in mask inspection or repair was specified from MRC (mask rule checking) of the same post-OPC data. Additional layout analysis perceives designer's intents that are described in the layout data and these are reflected in the calculation of the "MiLE" index. Finally, chip arrangement on a mask is retrieved from so-called electronic mask spec sheets to construct mask layouts. "MiLE" notifies to designers the index of mask manufacturing workload that is caused by mask layout, while modification and adjustments of design or OPC are iterated to maximize device productivity in early design phases. Therefore, designers can judge and control the mask manufacturability, or mask cost by designs and additional intents useful for mask making. In the production phases, our system releases useful information for mask manufacturing to a mask shop and decreases the mask manufacturing workload. In this paper, we report the outline and functions of MiLE system and the results of mask manufacturing workload calculation using post-OPC layout data.

We present a novel software system that combines design intent as known by EDA designers with defect inspection results from the maskshop to analyze the severity of defects on photomasks. The software -named Takumi Design- Driven Defect Analyzer (TK-D3A)- analyzes defects by combining actions in the image domain with actions in the design domain and outputs amongst others flexible mask-repair decisions in production formats used by the maskshop. Furthermore, TK-D3A outputs clips of layout (GDS/OASIS) that can be viewed with its graphical user interface for easy review of the defects and associated repair decisions. As inputs the system uses reticle defect-inspection data (text and images) and the respective multi-layer design layouts with the definitions of criticalities. The system does not require confidential design data from IDM, Fabless Design House, or Foundry to be sent to the maskshop and it also has minimal impact on the maskshop's mode of operation. The output of TK-D3A is designed to realize value to the maskshop and its customers in the forms of: 1) improved yield, 2) reduction of delivery times of masks to customers, and 3) enhanced utilization of the maskshop's installed tool base. The system was qualified together with a major IDM on a large set of production reticles in the 90 and beyond-65 nm technology nodes of which results will be presented that show the benefits for maskmaking. The accuracy in detecting defects is extremely high. We show the system's capability to analyze defects well below the pixel resolution of all inspection tools used, as well as the capability to extract multiple types of transmission defects. All of these defects are analyzed design-criticality-aware by TK-D3A, resulting in a large fraction of defects that do not need to be repaired because they are located in non-critical or less-critical parts of the layout, or, more importantly, turn out to be repairable or negligible despite of originally being classified as unrepairable when no such criticality knowledge is used. Finally, we show that the runtimes of TK-D3A are relatively short, despite the fact that the system operates on full-chip designs.

This paper studies the impact of shape and local environment (pattern layout) on the ability to detect defects on the reticle and the extent to which they affect the dimension of the printed image on the wafer. The authors have made extensive use of design information to perform a thorough evaluation. OPC software was used to generate mask data that was comparable to product mask data. Defects were placed on the post-OPC layout and OPC software was also used to simulate the dimension of the defective features as printed on the wafer. "Design Based Metrology" was used to create accurate metrology recipes to support wafer and mask metrology. Ultimately the procedures described in this paper allow a direct correlation to be made between reticle inspectability and the impact of the same defects on wafer CD. Data is presented for the case of the Contact Hole layer of a "65nm" Logic technology, though the methods described in the paper are applicable to all layers.

Transistor dimensions are quickly approaching atomic levels. Metrology is already a challenge. Several technologies have evolved to keep pace such as scatterometry and bare wafer inspection. Lithography critical dimensions, registration and pitch are the forefront of dimensional scaling challenges. Variability at these dimensions can limit function, performance, yield and profitability with design for manufacturing (DFM) challenges. Intel's integrated device manufacturing (IDM) model has enabled many technologies and disciplines to come together to provide the most cost effective and optimal solutions to Moore's law scaling challenges. Intel's Automated Manufacturing Technology (AMT) capabilities play a significant role in enabling optimal Moore's law scaling solutions. The information turn cycle starts with the definition of the technology Test Chip and ends with the analysis of results from end of line (EOL) metrology. We will discuss the relevant DFM elements of AMT to enable: test-chip setup, computational lithography and validation, product & process modeling and setup, intelligence and control to minimize variability, rapid yield learning, and rapid product design learning.

Traditional design rules to ensure device functionality and yield are defined by multiple criteria. However, in a complex and mature design and manufacturing environment and a quickly changing marketplace, one should consider a more comprehensive and efficient way to gradually replace the rigid design rules with yield and product models based on the extracted layout features, process capabilities, and market conditions. This methodology may be of particular attractiveness for custom products such as Systems-on-Chip where the complexity of customized design rules can be a detriment for product optimization. In addition, the key criterion for product development: profitability in the marketplace, or Design-for-Profit (DfP), has usually not been taken into account in the verification of design kits. In this paper, we would discuss how yield models can help re-derive the existing design rule and "recommended rule" methodology and take it to the next level of a comprehensive product development using model based design.

New DFM tools appearing on the market hold a promise of assessing parametric and functional yield loss due to lithography effects. The accuracy of underlying models can limit the veracity of such assessment. For example, many lithography steps used in the fab are extremely nonlinear and might exhibit significant differences from models used by the DFM tools. Furthermore, inputs used in calibrating a model can limit its accuracy, and most organizations are challenged to characterize the exact needs of a lithography model at a statistically relevant sampling size. After discussing potential sources of inaccuracy in modeling, the paper will describe a methodology for modeling and yield prediction based on such accurate modeling.

At 65nm technology node and below, with the ever-smaller process window, it is no longer sufficient to apply traditional model-based verification at only the nominal condition. Full-chip, full process-window verification has started to integrate into the OPC flow at the 65nm production as a way of preventing potentially weak post-OPC designs from reaching the mask making step. Through process-window analysis can be done by way of simulating wafer images at each of the corresponding focus and exposure dose conditions throughout the process window using an accurate and predictive FEM model. Alternatively, due to the strong correlation between the post-OPC design sensitivity to dose variation and aerial image (AI) quality, the study of through-dose behavior of the post-OPC design can also be carried out by carefully analyzing the AI. These types of analysis can be performed at multiple defocus conditions to assess the robustness of the post-OPC designs with respect to focus and dose variations. In this paper, we study the AI based approach for post-OPC verification in detail. For metal layer, the primary metrics for verification are bridging, necking, and via coverage. In this paper we are mainly interested in studying bridging and necking. The minimum AI value in the open space gives an indication of its susceptibility to bridging in an over-dosed situation. Lower minimum intensity indicates less risk of bridging. Conversely, the maximum AI between the metal lines provides indication of potential necking issues in an under-dosed situation. At times, however, in a complex 2D pattern area, the location as to where the AI reaches either maximum or minimum is not obvious. This requires a full-chip, dense image-based approach to fully explore the AI profile of the entire space of the design. We have developed such an algorithm to find the AI maximums and minimums that will bear true relevance to the bridging and necking analysis. In this paper, we apply the full-chip image-based analysis to 65nm metal layers. We demonstrate the capturing of potential bridging or necking issues as identified by the AI analysis. Finally, we show the performance of the full-chip image-based verification.

A few years ago, model-based layout verification was used primarily with mask data preparation as a safety net to predict and avoid limited printability performance prior to mask fabrication. If certain layout locations would transfer poorly onto the wafer, the mask data was intercepted, preventing yield loss associated with "mask issues." Such mask-related issues come primarily from three sources: Mask manufacture bias, OPC limitations and intrinsic layout configurations. While mask manufacture bias and OPC limitations can be addressed during the final stages of mask synthesis and manufacture, layout configurations that exhibit poor lithographic performance for a given process cannot be modified without considering the electrical effect such new topologies will induce in the modified layout. In principle, marginally performing layouts can be removed from the design by adequately interpreting geometric design rules. Unfortunately, while such rules are strictly defined for 1D, they are not as well-defined for arbitrary 2D configurations. For that reason, several approaches to transferring sufficient process information to the layout synthesis tools to prevent the presence of layout configurations incompatible with the production process have been attempted. However, when the production process is not fully developed, using these approaches can potentially limit the portability of the layout. In this paper, we describe and evaluate different approaches to defining reasonable layout verification targets by exploring various methods to reduce verification time, maintain accuracy and improve layout portability. First, to reduce verification time, we implement a method to quickly scan the layout for large variations without the need to run the actual OPC recipe. This paper describes the characteristics of a model that defines a pseudo-OPC process. Next, because the pseudo-OPC process cannot be mapped exactly to the real OPC process, there are accuracy limitations when using only the pseudo-OPC process. To overcome these limitations, the verification system follows an incremental approach, in which those regions previously selected are evaluated with the full mask synthesis recipe to reduce the number of falsely detected errors. Finally, to investigate the issue of portability, we evaluate how different errors evolve with maturing process and OPC recipe conditions for different layout patterns.

An automated litho-aware design migration solution has been implemented to enable designers to port existing IP layouts (custom, library, and block) to nanometer technologies while optimizing layout printability and silicon yield. With rapidly shrinking technology nodes, the industry consolidation toward fabless or fab-lite manufacturing, demand for second-sourcing and dramatic increase in cost of IP development, the automation of "vertical" (between nodes) and 'horizontal" (between chip manufacturers) migration becomes a very important task. The challenge comes from the fact that even within the same technology node design and process-induced rules deviate substantially among different IDMs and foundries, which leads to costly, error-prone and time consuming design modifications. At the same time, fast and reliable adjustments to design and ability to switch between processes and chip manufacturers could represent significant improvement to TTM, and respectively improving ROI. Using conservative rules (or restricted design rules) is not always a viable option because of the area, performance and yield penalties. The difficulty of migration is augmented by the fact that design rules are not sufficient to guaranty good printability, maximum process window and high yield. Model-based detection of lithography-induced systematic yield-limiting defects (a.k.a. hotspots) is becoming a vital part of the design-for-manufacturing flow for advanced technology nodes at 65nm and below. Driven by customer demand, a collaborative effort between EDA vendors provides a complete design-for-manufacturing migration solution that allows sub-65 nanometer designers to comprehensively address the impact of manufacturing variations on design yield and performance during layout migration. First, the physical hard IP is migrated from its existing 90nm process to a more advanced 65 and 45 nm processes, resulting in an area-optimized DRC-clean 65nm design retaining the original hierarchy to facilitate further editing and design verification the original hierarchy is maintained. Then, the design manufacturability is checked using a model-based hotspot detection solution, applying foundry-certified models. Along with hotspots, it is also critical for the hotspot detection tool to generate directives on how to modify the layout to fix hotspots and prevent creation of new hotspots. Several alternative fixing guidelines, ranked by amount of design perturbation, are generated to provide focus and maximum flexibility to the correction tool. The correction tool reads hotspot locations, severities along with the fixing guidelines, identifies area to be fixed and converts the fixing guidelines into geometry constraints. Correction is then done on each area while respecting design rules, managing ripple effects through multiple layers and maintaining the hierarchy. When all the corrections are completed areas that have been affected are identified to allow these to be incrementally checked by the lithography verification tool (LPC) and re-assembled. In case new or residual hotspots are detected, this fix-verify flow iterates over to converge on a DRC and lithography-compliant design. Usually no more than three iterations are needed to output hotspot-free, DRC and Lithocompliant design. We present the results of this fully automated lithography-aware migration flow on layout IPs ranging from 65 nm to 45 nm design and migrated across foundries. Results show substantial layout quality improvements, reduced design sensitivity to process variability by eliminating hotspots. Run-time and hotspot fixing performance are shown.

A methodology to predict the impact of mask overlay and litho-induced process variations on Statistical Timing for Double Patterning is presented. As we migrate to the 32nm node and Double Patterning techniques, Mask Makers, Ebeam providers and Scanner providers are given very aggressive requirements for maintaining overlay accuracy. This method takes into account Mask CD Uniformity and Mask Image placement error budgets presented in the 2006 ITRS. It is assumed the ITRS requirements are met. This methodology combines the infrastructure used in Single Exposure Litho-Aware Layout Implementation tools with Double Patterning decomposition results to determine a meaningful layout-specific analysis for pre-tape-out timing sign-off. Traditional timing analysis uses a set of look-up tables for simulating device distortions. These tables have been proven to require excessive guardbanding in Single Exposure masks. Adding the additional dimension of overlay distortion to these tables will have the effects of hiding parametric failures, or requiring excessive guardbanding to ensure timing predictability. Results will be shown that describe the timing effects with and without taking into account these distortions, as well as design samples that contribute to these distortions.

DFM considerations have become an indispensable and integral part of advanced nanometer semiconductor product designs. Traditional first-generation DFM tools have focused on functional lithography hotspot detections. While useful, these tools offer designers few hints on the complex layout fixings and the intricate trade-off decisions required. With these limitations, DFM layout optimization has become a tedious and inconsistent design endeavor. In addition, the long and intense calibration cycle required for the traditional DFM models have hindered their effectiveness and timeliness. An automatic DFM layout optimization system that performs systematic multi-objective functional and parametric DFM optimizations at early design phase will be introduced. A calibration-lite methodology that has expedited the DFM model set-ups will be discussed along with the silicon validation test pattern designs. Finally, both simulation and silicon experiment results will be presented.

We demonstrate a consolidated metric that can quantitatively express design quality with respect to multiple yield loss mechanisms. Using this metric and the design analysis and optimization framework we have developed, we study the effectiveness of different layout enhancements and the effect of combining multiple enhancements in a single layout. Previous works attempted to select a single combination of design enhancements that presents the optimal trade-off between different yield loss mechanisms and optimizes the total yield. We show that the optimal solution depends on the layout features on a small scale, thus the best yield can be achieved by selecting different combinations of enhancements in different locations. We introduce a general form of the cost function and compare different layout configurations, taking into account lithography process variations, random defect distributions, and recommended design rules. Since all layout configurations represent the same electrical devices, it is possible to dynamically determine the most robust layout implementation according to the cost function that incorporates the relative importance of each yield loss contributor. We compare the globally optimized layout, where the sequence of yield enhancements is selected based on the overall design yield, with locally optimized layouts, where the enhancements are fine-tuned for each location. We show that when comparing different layout enhancements it is important to consider two types of yield tradeoffs, local tradeoffs where the same layout feature impacts several yield loss mechanisms, and global tradeoffs where the net effect of a particular type of layout enhancement depends on its location. By selectively applying yield enhancements to the areas of the layout where they are needed we can considerably improve the overall design quality.

This paper proposes a novel method of identifying interactions between neighboring standard cells via fast-CAD pattern matching. Studies of cell-to-cell interactions for both metal 1 and poly layouts are made for selected samples from libraries for 130 and 90 nm generations provided under an NDA agreement by ST Microelectronics. Both simulation and pattern matching are utilized to identify and quantify hot-spots. The physical basis for pattern matching is described. In validating pattern matching compared to full simulation, changes in linewidth for a fixed defocus setting varied quadratically with pattern match factor and can be modeled by a parabolic equation with an r-squared value of 0.77. Results demonstrate that there is a considerable best-to-worst variation of 4-7% in the linewidth among neighbors, which is produced through a focus swing of 0.58 Rayleigh Units (RU). The focus swing is oscillatory with cell separation distance, and a slight shift in spacing on the order of 0.5 λ /NA can mitigate lateral interaction effects.

DFM tools have been all the rage in recent years. By exposing potential manufacturability, timing and variation issues early, these tools can help the designers correct such issues before the tape out. Such an early intervention delivers a faster yield ramp for the product. For the lower volume devices, the faster yield ramp can help meet the market window while for higher volume devices it can also mean millions of dollars in cost savings. While there have been several DFM product announcements, case studies focusing on actual usage of such tools are not publicly available. In this article we share the data from a real customer evaluation and deployment. This North American customer has deployed the tool and completed several TSMC 65nm layouts. By focusing on the motivation to use such a tool, the article will first quantify the expected value from such a tool. Next the article will present the detailed evaluation criteria for choosing a tool. Finally, actual error data from production tape outs and performance metrics of the LCC tool will be presented showing runtime, scalability and memory numbers.

A detailed defect printability analysis is reported for conditions that are fully representative for the world's first full field EUV scanner, using 4X reticles, as obtained by simulation. For absorber type defects the historical rule of thumb underestimates the printability. An opaque defect located in a space within a 40nm lines and space pattern can already cause more than a 10% change in the space width from 80% of the space width onwards (>32nm at mask scale, >8 nm at wafer scale) depending on its location. Absorber type clear defects start affecting line width in 40nm lines and spaces from about twice the size of an opaque defect. Particles simulated as carbon cubes have a similar effect as absorber type opaque defects provided that they are about 50% larger. Other possible particle materials are investigated as well. Local carbon deposition, which may originate from SEM inspection, can cause a printing effect already at a thickness of only 2nm. Multilayer or substrate type defects require surface smoothing to less than about 2nm, as to keep the impact of so-called phase defects under control. Experimental plans for comparison of simulations to exposures on the ASML Alpha Demo Tool installed at IMEC are included.

The readiness of a defect-free extreme ultraviolet lithography (EUVL) mask blank infrastructure is one of the main enablers for the insertion of EUVL technology into production. It is essential to have sufficient defect detection capability and understanding of defect printability to develop a defect-free EUVL mask blank infrastructure. The SEMATECH Mask Blank Development Center (MBDC) has been developing EUVL mask blanks with low defect densities with the Lasertec M1350 and M7360, the 1st and 2nd generations, respectively, of visible light EUVL mask blank inspection tools. Although the M7360 represents a significant improvement in our defect detection capability, it is time to start developing a 3rd generation tool for EUVL mask blank inspection. The goal of this tool is to detect all printable defects; therefore, understanding defect printability criteria is critical to this tool development. In this paper, we will investigate the defect detectability of a 2nd generation blank inspection tool and a patterned EUVL mask inspection tool. We will also compare the ability of the inspection tools to detect programmed defects whose printability has been estimated from wafer printing results and actinic aerial images results.

According to the International Technology Roadmap for Semiconductors, meeting the strict requirements on image placement errors in the sub-45-nm regime may be one of the most difficult challenges for the industry. For Extreme Ultraviolet Lithography (EUVL), the nonflatness of both the mask and chuck is critical as well, due to the nontelecentric illumination during exposure. To address this issue, SEMI Standards P37 and P40 have established the specifications on flatness for the EUVL mask substrate and electrostatic chuck. This study investigates the procedures for implementing the Standards when measuring and characterizing the shapes of these surfaces. Finite element simulations are used to demonstrate the difficulties in supporting the mask substrate, while ensuring that the measured flatness is accurate. Additional modeling is performed to illustrate the most appropriate methods of characterizing the nonflatness of the electrostatic chuck. The results presented will aid in identifying modifications and clarifications that are needed in the Standards to facilitate the timely development of EUV lithography.

A high flatness of 50 nm, zero defects at more than a size of 30 nm and a high reflectivity of more than 66% for extreme ultraviolet (EUV) light are critical issues related to EUV mask blanks. In this paper, progress on these issues and the recent performance of EUV blanks is reported. Steady progress in defect reduction was achieved in the past six years by improving fabrication processes. When inspected by a Lasertec M1350, defect quality as low as 0.02 defects/cm² at 70-nm sensitivity was demonstrated on a multilayer (ML) blank with a quartz (QZ) substrate. A QZ substrate with a high flatness of around 90 nm peak-to-valley (P-V) on both sides and a high defect quality of 0.006 defects/cm² at 60-nm sensitivity was obtained using a newly developed polishing process consisting of local polishing, touch polishing and cleaning. The cleaning process was developed for low thermal expansion (LTE) glass to reduce the defects associated with it. Using the cleaning process, the ULE^TM substrates showed defectivity similar to the QZ substrates. An average flatness of 117 nm P-V, and best flatness of 84 nm P-V on the front side and 56 nm P-V on the back side were obtained on ULE substrates using the new polishing process. Multilayer (ML) blanks with a high defect quality of 0.08 defects/cm² at 80-nm sensitivity were produced on a ULE substrate. The ML blanks, consisting of 50 bilayers, have high peak reflectivity of more than 66% and excellent uniformity of less than 0.04 nm in centroid wavelength, which meets the desired specifications.

In this paper, we report our recent investigations into the effect of resist processing on defect printability. Simulations are conducted using both aerial image threshold and resist models in an attempt to determine the effect of the resist process. There is good agreement between the resist model simulation and the printing data obtained using the EUV micro exposure tool (MET) and a programmed defect mask. The CD error, or defect printability, introduced by edge defects on 70nm semi-iso lines predicted by the aerial image threshold model is larger than that by both the resist model and the actual printing results. However, this favorable difference vanishes for edge defects on 30nm lines. Mask error enhancement factor (MEEF) is used to understand the discrepancy between the aerial image threshold model and the resist model. Image quality measured by normalized image log slope (NILS) and resist process window characterized by exposure latitude are closely related to image MEEF and resist MEEF respectively, and ultimately determine defect printability for a given patterning and resist processing. Defect printability increases exponentially as the feature size shrinks. This nonlinear behavior presents a challenge for defining defect specifications for EUV lithography based on extrapolations from currently available printing data.

The impact of mask absorber properties on printability in EUV lithography was studied from the viewpoint of lithographic requirements which can give high imaging contrast and reduce the shadowing effect. By using the refractive indices of the elements and compounds employed as absorbers, their reflectivity on multilayer blanks, aerial image on wafer plane and printed CDs depending on absorber thicknesses were simulated. This predicted an optimum Ta-based absorber's thickness. Several patterned masks of LR-TaBN absorber with various thicknesses were prepared. Each patterned mask was exposed with the newly developed small-field-exposure-tool (SFET). It was demonstrated that optimized absorber thickness can, without loss of printability performance, reduce CD difference between horizontal and vertical pattern that has been known to be caused by shadowing effect.

In sub-60nm technology node, cleaning process becomes specialized to clear the defects without pattern damage as decreasing critical particle size to control. While cleaning process has to meet the primary requisite, removal of particle including organic residue and prevention of particle re-deposition, it should enable to suppress haze phenomena for a long life of photomask. However, to solve the problem of haze, the chemical materials caused haze seed should be hardly used and physical force becomes strengthen as the compensation for cleaning efficiency. Unfortunately it brings about another problem, pattern damage seriously. In this paper, adequate cleaning conditions which are applicable in sub-60nm technology node are evaluated to meet the dilemma among three requirements, high cleaning efficiency, and prevention of pattern collapse, and prevention of haze phenomenon. All cleaning steps in photomask process were set up using only 172nm UV irradiation for degradation of organic contaminants and deionized water (DI) with acoustic power for particle lift-off. The effect of UV and DI cleaning on cleaning efficiency and haze phenomena was derived from carrying out chemical and physical analysis simultaneously. Also, we could quantify the statistical probability of pattern collapse in each of technology node and layer shape as different condition of megasonic frequency and its power. As a result, it was known that this cleaning process have various merits to make out dilemma mentioned above, if it satisfies optimized conditions.

Progressive mask defects are a critical mask-reliability issue in DUV lithography. It is well known that the majority of the defects are ammonium sulfates. We have found using ToF-SIMS that metallic atoms are localized at ammonium-sulfate defects on the mask surface, can influence the growth of the defects. Carbon compounds containing nitrogen atoms are also localized at the some defects. These carbon compounds are the result of the adsorption of organic volatiles outgassing from a reticle SMIF pod. Metal residues and organic contamination on a photomask as well as airborne acidic and basic contamination must be controlled to avoid progressive defects on photomasks.

The authors have developed and successfully implemented a practical, yet effective solution to help eliminate haze formation in the production fab. Based on a novel mechanism of haze formation described earlier, along with a thorough understanding of the reticle surface chemistry changes during the manufacturing process, the authors found an unexpectedly simple and straightforward way to prevent haze formation. This is possible regardless of the origin of the reticle, by controlling the purity of the immediate reticle environment.

Reticle Haze results from the deposition of a chemical residue of a reaction that is initiated by Deep Ultra Violet (DUV) or higher frequency actinic radiation. Haze can form on the backside of the reticle, on the chrome side and on the pellicle itself. The most commonly reported effect of haze is a gradual loss in transmission of the reticle that results in a need to increase the exposure-dose in order to maintain properly sized features. Since haze formation is non-uniform across the reticle, transmission loss results in an increase in the Across Chip Linewidth Variation (ACLV) that is accompanied by a corresponding reduction in the manufacturing process window. Haze continues to grow as the reticle is exposed to additional low wavelength radiation through repeated use. Early haze formation is a small-area phenomenon in comparison to the total area of the reticle and may initiate simultaneously in separate areas. The early stages of reticle haze therefore results in a degradation of Best Focus, Depth of Focus and the Exposure latitude of individual features in the "hazed" area prior to any noticeable large area transmission loss. Production lots subject to reticle hazing on critical layers will experience a direct loss of lithographic yields, loss of capacity, an increase in rework rates and an ultimate loss in overall final-test yield long before the need for an overall image exposure-dose increase is detected. Feature profiles and process response are degraded at the earliest stages of haze formation. While early hazing may occur in a small area of the reticle, the area influenced by the initial deposition is relatively large in comparison to the size of an individual circuit feature. A sampled metrological inspection of a regular array of points across the exposure field is therefore able to detect any form of reticle haze if the analysis monitors the feature-profile response rather than simply feature widths. A model-driven method for the early detection of reticle-haze using basic feature metrology is developed in this study. Application results from a production reticle are used to demonstrate validation of the technique that employs a highly accurate method of calculation of the uniformity of the reticle exposure-response for individual features across the exposure.

The haze issue has gradually increased in the 65 nm node technology and beyond. This issue has been reporting that it is caused by chemical reaction among ions like SO₄^2-, NH₄⁺ and aromatic hydrocarbon compounds (AHCs) such as butylated hydroxy toluene (BHT), toluene and etc. on mask by 193 nm laser in general. This haze growth causes defects with accumulation of exposure energy. Finally, it decreases the lifetime of photomask with an increase in defects. The source of this haze is generated from storage materials as well as chemical residue in the photomask process. Therefore, we investigated the adsorption rate of airborne molecular contamination (AMC) on each layer with storage materials which were assumed to be the source of the haze. We analyzed adsorbed ions and volatile organic compounds (VOCs) on each layer to verify the effects of storage materials for some storage periods by automatic thermal desorption gas chromatography/mass spectrometer (ATD GC/MS) and ion chromatography (IC). Also, we investigated the contact angle of each layer as AMC concentration of storage materials. From the experimental results, we confirmed that the adsorption rate of AMC was different on each layer as storage materials.

While significant progress has been made in reducing the occurrence rate of progressive defect growth on photomasks used at 193nm, the issue continues to be a problem for many semiconductor fabs. Increasing evidence from multiple sources indicates that further reduction in haze risk involves closely controlling the storage and exposure environment of the photomask. Further controlled testing is necessary to characterize the impact of environment and individual components on growth. In this way, photomask users, equipment and material providers may be better prepared to ensure the proper storage and use of photomasks in order to reduce the risk of haze growth. In continuation of work previously reported by Toppan Photomasks, advanced test apparatus, recently designed and built, now enables researchers to generate and maintain stable and controlled levels of multiple impurities which potentially effect haze growth. Supported by on-line and off-line analytical methods and instrumentation, new experimental set-up enables accuracy in the testing and validation of the impacts of environmental variables. Different classes of pollutants in multiple combinations have been studied to more precisely characterize environmental sensitivity of varying types of 193 nm reticles. Authors report further on the study of the effect of environmental conditions on severity and rate of haze formation to provide insight into the requirements for reducing or even preventing such conditions.

Reducing the amount of ionic residues coming from cleaning chemistry became necessary for photomask manufacturing process in order to eliminate the major cause of haze. The achievement of this target involves using sulphate-free steps from resist removal to final cleaning, maintaining good performances on particles or residues removal as well as minimization of pattern damages and preservation of the substrate properties. In this paper the cleaning strategies for high-end masks are discussed and a tight dependency on substrate and contamination type is highlighted as the major aspect that influences the good performances for ozone-based technique. The data collected from both tests and real production for sulfate-free cleaning show that the key point to achieve the full effectiveness is the careful definition of the sequence of treatments and rinses, allowing also the minimization of pattern damages. The cleaning capability of the full sulphate-free process is tested on various types of contaminants and the achieving of excellent removal performance is demonstrated for contaminations of sizes down to 100nm. When the sulfate-free cleaning is not fully effective, a pre-treatment is applied before the cleaning in order to reduce the interaction between contamination and substrate, thus enlarging the removal capability of the ozone-based cleaning. The ion chromatography confirms that the sulphate residues can be reduced below the threshold value for haze formation.

We have tested the validity of the so-called 'vector-effect emulation mode' of the newest member of the AIMS^TM family, the AIMS^TM45-193i, that was recently developed for Hyper-NA applications. This vector-effect emulation mode (also called 'scanner mode') converts the measured signals into a prediction of what the image-in-resist of a Hyper-NA scanner would be (so including vector- and polarization effects). We've done a number of experiments that directly test the validity of this vector-effect emulation, by comparing them to rigorous lithographic simulations and to CD-measurements from printed NA=1.20 scanner wafers, and found that the AIMS^TM 45-193i results are in fact quite accurate. Afterwards we looked at a number of potential Hyper-NA imaging applications for the AIMS^TM 45-193i, again comparing it to rigorous simulations and wafer CD-measurements. These results indicate that, next to its traditional use as reticle-inspection tool, the AIMS^TM 45-193i has potential use also in the wafer fab as an 'imaging-inspection' or 'OPC-defect inspection' tool, especially when applied to 2D patterns.

Double patterning (DPT) lithography is seen industry-wide as an intermediate solution for the 32nm node if high index immersion as well as extreme ultraviolet lithography are not ready for a timely release for production. Apart from the obvious drawbacks of additional exposure, processing steps and the resulting reduced throughput, DPT possesses a number of additional technical challenges. This relates to, e.g., exposure tool capability, the actual applied process in the wafer fab but also to mask performance and metrology. In this paper we will address the mask performance. To characterize the mask performance in an actual DPT process, conventional parameters need to be re-evaluated. Furthermore new parameters might be more suitable to describe mask capability. This refers to, e.g., reticle to reticle overlay but also to CD differences between masks of a DPT reticle set. A DPT target of reticle to reticle induced overlay of 6nm, 3σ at mask level was proposed recently for the 32nm node. The results show that this target can be met. Besides that, local CD variations and local displacement become critical. Finally, the actual mask metrology for determination of these parameters might not be trivial and needs to be set up and characterized properly. In this paper we report on the performance of two-reticle sets based on a design developed to study the impact of mask global and local placement errors on a DPT dual line process. In a first step we focus on reticle to reticle overlay. The overlay between two masks evaluated for different wafer overlay targets is compared with measurements on actual resolution structures. In a second step, mask to mask CD variations are addressed. Off-target CD differences as well as variations of CD signatures on both reticles of a set are investigated. Finally, local CD variations and local displacements are examined. To this aim, local variations of adjacent structures on the reticle are characterized. The contribution of local effects to the overall CD and registration budget is estimated.

DPL (Double Patterning Lithography) has been in public as one of candidates for 45nm or 32nm HP since ITRS2006update disclosed. A lot of report of the performances and issues regarding to DPL were published. The current main concerns are evaluation of the infrastructures such as decomposition software, advanced photomasks, higher-NA exposure tool and leading-edge hard-mask process. If there is simpler procedure to evaluate DPL using a conventional environment without hard-mask process, the development of DPL will be accelerated. Here, the simple evaluation procedure for DPL using actual photomasks combining double exposure technique was proposed. The pseudo DPL result in terms of mask CD uniformity, image placement and overlay were demonstrated. In this evaluation procedure, decomposition restriction, mask latitude and fabrication load were also discussed

DPL (Double Patterning Lithography) has been identified as one of major candidates for 45nm and 32nm HP since ITRS2006update and several reports of the performance or challenges of DPL have been published. DPL requires at least two photomasks with tighter specification of image placement and the difference of mean to target according to ITRS2006update. On the other hand, approximately half of whole features of single layer are written on each photomask and the densest features are split into other photomask in consequence of pitch relaxation for DPL. Then the photomask writing data of two sets for DPL and single data for single exposure are evaluated for photomask fabrication load. The design will be automatically decomposed with EDA tool and OPC will be tuned as DPL or single exposure. Not only number of fractured features but also feasibility study of automatic decomposition will be presented and discussed. The consequences of relaxed pitch on process, inspection, repair, yield, MEEF and cycle time will be discussed with results as available.

To fulfill Moore's law the R&D stage of 3x nm HP nodes will have to be reached in 2008. Conventional DUV immersion technology is resolution limited to half pitch values exceeding 40 nm. Double Patterning Technology (DPT) is a major candidate to reach the 3x nm node in time. Geometrical pattern split, doubling the pitch, is one of the major steps of DPT. We present a feasibility study of the Rule Based (RB) DPT approach to pattern splitting based on a representative and reviewed selection of clips and full-mask designs.

For tight pitch patterning with sub-wavelength mask features, simulations and wafer data show that many mask stacks that provide superior image contrast, can provide inferior MEEF performance. For example, 6% MoSi EPSM is found to have higher MEEF than binary masks despite having better contrast and exposure latitude when equal lines and spaces on the mask are used to pattern equal lines and spaces on the wafer. Likewise, the deposition of SiO₂ on-top of the chrome surface of a binary mask improves contrast but degrades MEEF compared to a binary mask. When contrast is varied by mask stack or by print bias, MEEF is poorly correlated with contrast and often increases with increasing contrast. The optimal print bias for exposure latitude is significantly different than the optimum print bias for MEEF. MEEF, on the other hand, is highly correlated with the difference between maximum and minimum intensity when one varies mask stack, print bias and illumination. Analytical MEEF equations are derived that support this strong relationship between MEEF and the difference between maximum and minimum intensity.

The lithographic performance of current state-of-the-art resolution enhancement techniques (RET) will become critical at hyper numerical aperture (NA>1) due to mask 3D effects. We have studied the impact of the mask material on the lithographic performance at NA 1.2 and above. The assessment, both by rigorous simulations and experiments, involves the standard mask stacks, Cr binary mask (BIM) and MoSi 6% attenuated phase shift mask (attPSM), as well as alternatives such as thick Cr BIM, Ta/SiO₂ 1% and 6% attenuated PSM, and Ta/SiON 1% attenuated PSM. Using the rigorous electro-magnetic field (EMF) and lithographic process simulations (IISB DrLiTHO) the mask structure is optimized taking into account the trade_off with mask error enhancement factor (MEEF). Next, a throughpitch evaluation of the 45nm half-pitch (HP) node at NA1.2-1.35 is carried out examining maximum exposure latitude (EL), depth-of-focus (DOF), best focus shifts, and MEEF behavior for the various mask stacks. For the validation of the simulation methodology a correlation is made between scanner (ASML XT:1700Fi), AIMS (Zeiss AIMS^TM45-193i), and simulation results indicating the importance of the mask quality and mask properties. Based on the lithographic performance and the mask manufacturability we put together a ranking of the commercially available mask stacks for the 45nm HP node at NA 1.2 and 1.35.

As semiconductor features shrink in size and pitch, the pattern placement error at photomask, that is, the registration becomes more important factor to be reduced. Following ITRS roadmap, the registration for sub-45 nm node is required to be less than 5 nm but this specification still corresponds to the challengeable goal. Among several reasons to induce registration, here, we have focused on four major registration errors: e-beam positioning error, patterning effect, pellicle attachment effect, and sampling error of measurement. We quantify and analyze each error with the help of finite element modeling and by experiment. Based on these results, we present the current status and the goal of each error for the roadmap of sub-45 nm node.

A new and optimized waveguide based electromagnetic field solver with decomposition technique for rigorous optical and extreme ultraviolet (EUV) mask near field simulations is presented. The model allows to perform full three dimensional (full 3D) simulations as well as three dimensional simulations based on a decomposition technique (Q3D, "Q" means "quasi"). After a short introduction of the waveguide method the decomposition technique is presented. Subsequently the capabilities of the new electromagnetic field solver are demonstrated exemplarily based on state-of-the-art optical and EUV systems. The simulation of larger mask areas and the fast simulation of standard sized mask areas is shown. A comparison between the full 3D and the Q3D approach demonstrates the field of application of the decomposition technique.

The increasingly stringent demand for shrinkage of IC device dimensions has been pushing the development of new resolution enhancement technologies in micro-lithography. High NA and Ultra-High NA (NA>1.0) applications for low k₁ imaging strongly demand the adoption of polarized illumination as a resolution enhancement technology since proper illumination polarization configuration can greatly improve the image contrast hence pattern printing fidelity. For polarized illumination to be fully effective, ideally all the components in the optical system should not alter the polarization state during propagation from illuminator to wafer surface. In current OPC modeling tools, it is typically assumed that the amplitude and polarization state of the electric field do not change as it passes through the projection lens pupil. However, in reality, the projection lens pupil of the scanner does change the amplitude and the polarization state to some extent, and ignorance of projection pupil induced polarization state and amplitude changes may cause CD errors which are un-tolerable at the 45nm device generation and beyond. We developed an OPC-deployable modeling approach to model polarization aberration imposed by the projection lens pupil via Jones matrix format. This polarization aberration modeling capability has been integrated into the Synopsys OPC modeling tool, ProGen, and its accuracy and efficiency have been validated by comparing with an industry standard lithography simulator SolidE. Our OPC simulations show that the impact of projection lens pupil polarization aberrations on optical proximity effect (OPE) could be as large as several nanometers, which is not negligible given the extremely stringent CD error budget at 45nm node and beyond. This modeling approach is applicable to arbitrary polarization aberrations imposed by any components in the lithography system that can be characterized in Jones matrix format. Based on an experimentally measured Jones matrix pupil which intrinsically provides a much better approximation to the physical scanner pupil, we propose a more physics-centric methodology to evaluate the optical model accuracy of OPC simulator.

The accuracy of a fast 3D thick mask model is evaluated for 6% AttPSM having sub-resolution assist features (SRAF). The main features and SRAFs are designed to print 40nm lines or spaces on wafer (k1~0.28) through pitch from 100nm to 500nm. The resulting optimum SRAF sizes vary from 10nm to 48nm depending on the main feature pitch, mask tone and illuminator shape. The model accuracy is evaluated on both main feature CDs and SRAF side lobe intensities by comparing with a rigorous model. The fast 3D model shows improvements in both areas over thin mask model, particularly in SRAF printability prediction.

To simulate the interaction of buried defects and absorber features in EUV masks, a full three-dimensional, fast, integrated, simulator based on ray tracing and a thin mask model is presented. This simulator allows rapid assessment of the effects of buried defects on EUV printing. This new simulator, RADICAL (Rapid Absorber Defect Interaction Computation for Advanced Lithography), gives a 450X speed increase compared to FDTD, and matches FDTD within 1.5nm for predicting CD change due to a buried defect. RADICAL consists of three sequential steps: the propagation of the mask illumination down through the absorber pattern, the reflection off the defective multilayer, and the propagation back up through the absorber. A propagated thin mask model is used to model the down/up propagation through the absorber pattern and a ray tracing simulator is used for the multilayer reflection. These simulators are linked together using a Fourier transform to convert the near field output of one simulator step into a set of plane wave inputs for the next.

With the continuous shrink of feature sizes the pitch of the mask comes closer to the wave length of light. It has been recognized that in this case polarization effects of the mask become much more pronounced and deviations in the diffraction efficiencies from the well-known Kirchhoff approach can no longer be neglected. It is not only the diffraction efficiencies that become polarization-dependent, also the phases of the diffracted orders tend to deviate from Kirchhoff theory when calculated rigorously. This also happens for large structures, where these phase deviations can mimic polarization dependent wave front aberrations, which in the case of polarized illumination can lead to non-negligible focus shifts that depend on the orientation and the features size themselves. This orientation dependence results in a polarization induced astigmatism offset, which can be of the same order of magnitude or even larger as polarization effects stemming from the lens itself. Hence, for correctly predicting polarization induced astigmatism offsets, one has to both consider lens and mask effects at the same time. In this paper we present a comprehensive study of polarized induced phase effects of topographic masks and develop a simple theoretical model that accurately describes the observed effects.

An experimental technique for quantitatively characterizing edge effect contributions in transmission through thick photomasks is described and evaluated through electromagnetic simulation. The technique consists of comparing the 0^th order transmission for various duty cycles to the expected experimental behavior from a thin mask model. The real electric field component from the edges is proportional to the shift in the position of the minimum energy in the 0^th order field away from the expected thin mask location. The square root of the minimum 0^th order diffraction energy normalized to a clear mask gives the imaginary edge contribution. The results indicate that Alternating Phase Shifting Masks (ALT-PSM) and Attenuating Phase Shifting Masks (ATT-PSM) technologies have significant edge effects on the order of 0.1λ to 0.2λ per edge respectively, as well as polarization dependence. For periods of 2 wavelengths and larger these edge contribution values are nearly independent of pitch. The existence of an imaginary (or quadrature) phase component is shown to result in an additive linear variation of line edge shortening through focus. This tilt can be interpreted as a focus shift of the normal parabolic behavior and is about 0.5 Rayleigh units (RU). This focus shift depends to some extent on the surrounding layout as well as the feature itself.

We present rigorous 3D EMF simulations of isolated features on photomasks using a newly developed finite-element method. We report on the current status of the finite-element solver JCMsuite, incorporating higher-order edge elements, adaptive refinement methods, and fast solution algorithms. We demonstrate that rigorous and accurate results on light scattering off isolated features can be achived at relatively low computational cost, compared to the standard approach of simulations on large-pitch, periodic computational domains.

In this work, we model the effects of excimer laser bandwidth on optical proximity effects in high-NA ArF dry and immersion lithography. We quantify the errors introduced by using common approximation methods for the laser spectrum, such as the modified Lorentzian and Gaussian forms. Although these approximations are simple to use, and their symmetry properties can lead to reduced simulation run-times, they typically induce significant CD error when compared to the use of measured spectral profiles, which are obtained from high-resolution spectrophotometry. In this paper we establish some accuracy benchmarks and demonstrate the need for inclusion of information about the spectral profile - for the laser type of interest - in order to achieve sub-nanometer image calculation accuracy required for optical proximity correction. We further assess the speed-accuracy tradeoffs in terms of data truncation and sampling, and propose some practical limits for sampling the illumination spectrum. Additionally, in this work, we propose a new physically-based spectrum approximation method, which significantly reduces computation time at a cost of less than 0.25nm residual image-CD error from the fully-sampled image calculation. In addition to aerial image, we compare 45nm-node calibrated resist models and latent image results for 0.92NA dry and 1.2NA immersion processes using measured illumination profiles and lens aberrations. Finally, we consider the laser bandwidth sensitivity of 2D line-end patterns and typical post-OPC designs for a logic gate-process.

The majority of trends in lithography technology necessitate the use of smaller, higher aspect, patterns on photomasks which are increasingly sensitive to traditional cleaning processes. Particle defects are of increasing concern since, in deep and even overhanging structures, they can become fixed to the surface with such strength that any traditional cleaning technique would destroy any small, high-aspect, mask structures. A series of advanced new solutions are presented here which have been shown to remove these types of problem particles as applied to 45 nm node nanomachining mask repair with a RAVE nm450 system. In the first method, a cryogenic cleaning system is modified to greatly enhance selective removal of nanoparticles from high aspect structures. In the second method, the nm450 repair tool itself is applied to selectively remove targeted particles from a nanoscale area of the mask surface thus only affecting the region of interest and not touching any sensitive surrounding surfaces or structures.

The decreasing feature sizes as induced by the ITRS have a growing impact on the cost of current and future photolithographic masks. The assessment, repair and repair validation of these expensive masks has become a very substantial factor of the total mask production cost. The introduction of immersion lithography and the proposed introduction of double exposure strategies will further amplify this trend. In order to make the whole procedure more manageable in a production environment, with its constraints on timing and resource allocation, a seamless workflow of the repair and validation procedure is sought. A proposed way to achieve this is the set up of a dedicated tool set with a backbone infrastructure designed for this workflow as well as for the specific high resolution task. In this paper we concentrate on masks with feature sizes relevant for the 45nm node and defects with typical size and shape as they appear in production. Phase shifting masks with synthetic defects have been manufactured and the printability of the defects is analyzed with an AIMS^TM45-193i. In part the defect outline and three-dimensional shape as well as further characteristics have been visualized with an electron microscope, prior to repairing them with an electron beam based repair system. In addition we will show the behaviour of the phase of the mask in a region of interest, that is in this case the repair area and its immediate vicinity. This will be done by a special new tool, named Phame^®, developed for measuring the actual phase of smallest mask features with a high spatial resolution. In the conclusion we will give an outlook how the proposed workflow and the how the employed technologies will influence the masks that are expected to emerge for the 32nm node.

For almost a decade Nanomachining application has been studied and developed to repair next generation of photomasks. This technique, based on Atomic Force Microscopy (AFM), applies a mechanical removing of the defects with almost negligible quartz-damage, high accuracy of the edge-placement and without spurious depositions (stain, implanted elements, etc.) that may affect the optical transmission. SII NanoTechnology Inc. (SIINT) is carrying out a joint-development project with DNP Photomask Europe S.p.A. (DPE) that has allowed the installation in DPE of the next generation state-of-the-art AFM based system SPR6300 to meet the repair specifications for the 65 nm Node. Drift phenomena of the AFM probe represent one of the major obstacles for whichever kind of nano-manipulation (imaging and material or pattern modification). AFM drift undermines the repeatability and accuracy performances of the process. The repair methodology, called NewDLock, implemented on SPR6300, is a semi-automated procedure by which the drift amount, regardless of its origin, is estimated in advance and compensated during the process. Now AFM Nanomachining approach is going to reveal properties of repeatability and user-friendly utilization that make it suitable for the production environment.

Recently questions have been raised about whether high aspect ratio (HAR) NanoBits^TM can be effectively utilized to repair extension defects in 45 nm node and beyond. The primary concern has been how the effect of NanoBit^TM deflection impacts edge placement, sidewall angle and z-depth control repeatability. Higher aspect ratio bits are required for defects that arise as mask feature sizes become smaller. As the aspect ratio of the NanoBit^TM continues to increase to meet these demands, the cross sectional area of the bit used for nanomachining becomes thinner and more susceptible to bending under the forces applied during the nanomachining process. This is especially true when deeper features that require HAR NanoBits^TM are being repaired. To overcome this trend RAVE LLC has developed a new repair process that utilizes the strength of the bit shape. Repair of 45 nm node defects that require HAR NanoBits^TM will be demonstrated using a new repair process and cantilever design.

The Aerial Image Measurement Tool (AIMS) can estimate the wafer printability without exposure to wafer by using scanner. Since measured aerial images are similar with wafer prints, using AIMS becomes normal for verifying issue points of a mask. Also because mask design rule continues to shrink, defects and CD uniformity are at issues as factors decreasing mask yield. Occurred defects on a mask are removed by existing mask repair techniques such as nanomachining, electron beam and focused ion beam. But damages and contaminants by chemical and physical action are found on the mask surface and contaminants above special size lead to defects on a wafer. So cleaning has been necessary after repair process and detergency has been important. Before AIMS measurement, cleaning is done to make same condition with shipped mask, which method brings repeated process - repair and cleaning - if aerial image was not usual. So cleaning effect after the FIB repair is tested by using the AIMS to find the optimized process minimizing the repeated process and to get similar scanner results. First, programmed defect mask that includes various defect size and type is manufactured on some kinds of patterns in DRAM device and sub-80nm tech. Next the defects on the programmed mask are repaired by FIB repair machine. And aerial images are compared after the chemical cleaning, non-chemical cleaning and without cleaning. Finally, approximate aerial images to scanner results are taken regardless of cleaning process. It means that residue originated from repair process doesn't affect aerial images and flexible process is possible between AIMS, repair and cleaning process. But as the effect of minute particles and contaminations will be increased if pattern size is much smaller, it needs to reconfirm the effect below the sub-60nm in DRAM device.

Defect inspection is one of the major challenges in the manufacturing process of photomasks. The absence of any printing defect on patterned mask is an ultimate requirement for the mask shop, and an increasing effort is spent in order to detect and subsequently eliminate these defects. Current DUV inspection tools use wavelengths five times or more larger than the critical defect size on advanced photomasks. This makes the inspectability of high-end mask patterns (including strong OPC and small SRAF's) and sufficient defect sensitivity a real challenge. The paper evaluates the feasibility of inspecting the printed wafer as an alternative way for the high-sensitivity defect inspection of photomasks. Defects originating in the mask can efficiently be filtered as repeated defects in the various dies on wafer. Using a programmed-defect mask of 65-nm technology, a reliable detection of the printing defects was achieved with an optimized inspection process. These defects could successfully be traced back to the photomask in a semi-automated process in order to enable a following repair step. This study shows that wafer inspection is able to provide a full defect qualification of advanced photomasks with the specific advantage of assessing the actual printability of arbitrary defects.

As design rules continue to shrink towards 4x nm, there are increase usage of aggressive Optical Proximity Correction (OPC) in reticle manufacturing. One of the most challenging aggressive OPCs is Sub Resolution Assist Feature (SRAF) such as scattering and anti-scattering bars typically used to overlap isolated and dense feature process windows. These SRAF features are sub-resolution in that these features intentionally do not resolve on the printed wafer. Many reticle manufacturers struggle to write these SRAFs with consistent edge quality even the most advanced E-Beam writers and processes due to resolution limitations. Consequently, this inconsistent writing gives reticle inspection challenges. Large numbers of such nuisance defects can dominate the inspection and impose an extraordinarily high burden on the operator reviewing these defects. One method to work around inconsistent assist feature edge quality or line-end shortening is to adjust the mask inspection system so that there is a substantial sensitivity decrease in order to achieve good inspectability, which then compromises the sensitivity for the defects on main geometries. Modern defect inspection tools offer multiple modes of operation that can be effectively applied to optimize defect sensitivity in the presence of SRAF feature variability. This paper presents the results of an evaluation of advance inspection methods and modes such as die to database selective thinline desense, transmitted & reflected light inspections, review system and die to die selective desense to increase inspectability and usable sensitivity using challenging production and R&D masks. Key learnings are discussed.

'Fast Integrated Die-to-Die T+R' pattern inspection (DDTR), reflected tritone database inspection (DBRt) and STARlight2^TM (SL2) contamination inspection are employed by mask makers in order to detect pattern defects and contamination defects on photomasks for in process inspection steps. In this paper we compare the detection capabilities of these modes on real production masks with a representative set of contamination and pattern defects. Currently, SL2 inspection is used to find contamination defects and die-to-die and die-to-database are used for pattern defects. In this paper we will show that the new introduced 'Fast Integrated Die-to-Die T+R' pattern inspection (DDTR)¹ in combination with the DBRt can be used in production environment, instead of SL2 without any loss in the sensitivity. During the study, we collected and analyzed inspection data on critical layers such as lines & spaces and contact holes. Besides, performance of the modes on product plates characterization was done using a test mask with programmed defects.

Inspection strategies of transmitted die-to-database pattern inspection (DBT), reflected die-to-database inspection (DBR) and STARlight2^TM (SL2) contamination inspection are employed by mask makers in order to detect pattern defects and contamination defects on photo-masks in process inspection steps and outgoing quality control (OQC). Currently, SL2 inspection is used to detect contamination defects while die-to-database inspections are used to detect pattern defects. However, such inspection strategies need two passes to detect both pattern defects and contamination defects. In this paper we introduce 'Fast Integrated Die-to-Database T+R' (Fast dbTR) and compare its detection capabilities and the productivity to conventional standard detection modes, such as, DBT, DBR and SL2. Programmed reticles and production reticles with pattern defects and contamination defects were used for comparative data collection. During the study, we collected and analyzed inspection data on critical layers such as lines & spaces and contact holes. Empirical data show that 'Fast dbTR' is able to cover the sensitivity required by DBT, DBR and SL2 to detect both pattern defects and contamination defects in one single scan without any loss of productivity in production runs.

In this paper, a defect disposition integrated system for progressive growth and hard defects has been proposed and discussed for 65 nm and 45 nm immersion lithography. Pre-programmed hard defects on mask with minimum defect size of 60 nm are studied. These mask defects are scanned by STARlight inspection with pixel size P90 for mask defect capturing. Aerial Image Measurement System (AIMS) and printed photoresist features are used for modeling. Line, space and hole in both bright and dark field are used for model setup. Printability for these programmed mask defects is determined from process critical dimension (CD) variability. Experimental wafer results on the programmed defect mask are obtained using 193 nm immersion tool with effective NA of 1.2 imaging lens. The resist CDs response to the mask defect area are measured under the different exposure dose or focus. The correlation of AIMS CD, simulated CD and wafer CD for different defect types and sizes to printability is performed. Scan result of progressive growth defects are captured and verification of its printability using AIMS and Automated Mask Defect Disposition (AMDD) from KLATencor is obtained.

The ORION^TM series of test reticles have been used for many years as the photomask industry standard for evaluating contamination inspection algorithms. The deposition of Polystyrene Latex (PSL) spheres on various reticle pattern designs allow STARlight^TM tool owners to measure the relative contamination inspection performance in a consistent and quantifiable manner. However, with recent inspection technology advances such as shorter laser (light source) wavelengths and smaller inspection pixels, PSL spheres were observed to physically degrade over relatively short time periods: especially for the smallest sized spheres used to characterize contamination inspection performance at the most advanced technology nodes. Investigations into using alternative materials or methods that address the issue of PSL shrinkage have not yet proven completely successful. Problems such as failure to properly adhere to reticle surfaces or identification of materials that can produce consistent and predictable sphere sizes for the reliable manufacture of these critical test masks are only some of the challenges that must be solved. Even if these and other criteria are met, the final substance must appear to inspection optics as pseudo soft defects which resemble actual contamination that inevitably appears on production reticle surfaces. In the interim, programmed pindot defects present in the quartz region of the SPICA^TM test reticle are being used to characterize contamination performance while a suitable long-term solution to address the issue of shrinking PSL spheres on ORION masks can be found. This paper examines the results of a programmed pindot test reticle specifically designed to evaluate contamination algorithms without the deposition of PSL spheres or similar structures. This alternative programmed pindot test reticle uses various background patterns similar to the ORION, however, it also includes multiple defects sizes and locations making it more desirable than the limited range of defects found on the SPICA.

Sensitivity of newly developed photo mask inspection tool with reflective optic was evaluated for 45nm DRAM device. To get the required defect sensitivity of mask, printability of mask defect on wafer were simulated using in house simulation tool. Simulation results were compared with inspection results. Characteristic and sensitivity comparison between conventional transmissive and reflective optic tools were evaluated for several types of mask layer of 45nm and 55nm DRAM according to pixel size of detector of inspection tools. This reflective optic with short working distance was equivalent in sensitivity to transmissive optic tool. Mask for 45nm DRAM can be qualified by current status of the art inspection tools.

Results from the recently available TeraScanHR reticle inspection system were published in early 2007. These results showed excellent inspection capability for 45nm logic and 5xnm half-pitch memory advanced production reticles, thus meeting the industry need for the mid-2007 start of production. The system has been in production use since that time. In early 2007, some evidence was shown of capability to inspect reticles for the next nodes, 32nm logic and sub-50nm half-pitch memory, but the results were incomplete due to the limited availability of such reticles. However, more of these advanced reticles have become available since that time. Inspection results of these advanced reticles from various leading edge reticle manufacturers using the TeraScanHR are shown. These results indicate that the system has the capability to provide the needed inspection sensitivity for continued development work to support the industry roadmap.

Ever-tightened design rules and ensuing aggressive OPC features pose significant challenges for wafer fabs in the pursuit of compelling yield and productivity. The introduction of advanced reticles considerably augments the mask error enhancement factor (MEEF) where progressive defects or haze, induced by repeated laser exposure, continue to be a source of reticle degradation threatening device yield. High resolution reticle inspection now emerges as a rescue venue for wafer fabs to assure their photomask integrity during intensive deep UV exposure. Integrated in the high resolution reticle inspection, a MEEF-driven lithographic detector "Litho3" can be used run-time to group critical defects into a single bin. Previous investigations evinced that critical defects identified by such detector were directly correlated with defects printed on wafer, upon which fab users can make cogent decisions towards reticle disposition and cleaning therefore reduce cycle time. One of the challenges of implementing such detector resides in the lengthy set up of user-defined parameters, from practitioner standpoint, can considerably extend reticle inspection time and inevitably delay production. To overcome this, an automatic simulation program has been written to optimize Litho3 settings based off a pre-inspection in which only default Litho3 values are needed. Upon completion of the pre-inspection, the images are then scanned and processed to extract the optimal Litho3 parameters that are largely dependent upon the feature size characteristics and local MEEF. Thus optimized Litho3 parameters can then be input into the recipe set up to enable a real-time inspection, as such fab user can timely access the defect criticality information for subsequent defect disposition. In the interest of printability validation, such defect information and associated coordinates can be passed onto defect review via XLINK for further analysis. Corresponding MEEF values are also available for all identified critical defects. Through this automatic program the set up time for Litho3 can be reduced by up to 90%. For high capacity production fabs running a pre-inspection is deemed infeasible; this automatic optimization program can also serve as a direct interpretation of any regular reticle inspection even without invoking Litho3 set up, yet in the end provide output in the context of defect criticality. Results acquired from this program were found in good accordance with those from the real-time Litho3 inspection, for both critical and non-critical layers of 90 nm design node. Such capability allows detailed study of defect criticality in relation to its size, defect optical transmittance, residing surface, its proximity to a printing pattern as well as lithography parameters such as NA and sigma. Furthermore, coupling this automatic program with high resolution inspection also assists in determining lithography process window and an indepth comprehension of defect progression mechanism.

Double patterning lithography processes can offer significant yield enhancement for challenging circuit designs. Many decomposition (i.e. the process of dividing the layout design into first and second exposures) techniques are possible, but the focus of this paper is on the use of a secondary "cut" mask to trim away extraneous features left from the first exposure. This approach has the advantage that each exposure only needs to support a subset of critical features (e.g. dense lines with the first exposure, isolated spaces with the second one). The extraneous features ("printing assist features" or PrAFs) are designed to support the process window of critical features much like the role of the subresolution assist features (SRAFs) in conventional processes. However, the printing nature of PrAFs leads to many more design options, and hence a greater process and decomposition parameter exploration space, than are available for SRAFs. A decomposition scheme using PRAFs was developed for a gate level process. A critical driver of the work was to deliver improved across-chip linewidth variation (ACLV) performance versus an optimized single exposure process while providing support for a larger range of critical features. A variety of PRAF techniques were investigated by simulation, with a PrAF scheme similar to standard SRAF rules being chosen as the optimal solution [1]. This paper discusses aspects of the code development for an automated PrAF generation and placement scheme and the subsequent decomposition of a layout into two mask levels. While PrAF placement and decomposition is straightforward for layouts with pitch and orientation restrictions, it becomes rather complex for unrestricted layout styles. Because this higher complexity yields more irregularly shaped PrAFs, mask making becomes another critical driver of the optimum placement and clean-up strategies. Examples are given of how those challenges are met or can be successfully circumvented. During subsequent decomposition of the PrAF-enhanced layout into two independent mask levels, various geometric decomposition parameters have to be considered. As an example, the removal of PrAFs has to be guaranteed by a minimum required overlap of the cut mask opening past any PrAF edge. It is discussed that process assumptions such as CD tolerances and overlay as well as inter-level relationship ground rules need to be considered to successfully optimize the final decomposition scheme. Furthermore, simulation and experimental results regarding not only ACLV but also across-device linewidth variation (ADLV) are analyzed.

To maximize the process window and CD control of main features, sizing and placement rules for sub-resolution assist features (SRAF) need to be optimized, subject to the constraint that the SRAFs not print through the process window. With continuously shrinking target dimensions, generation of traditional rule-based SRAFs is becoming an expensive process in terms of time, cost and complexity. This has created an interest in other rule optimization methodologies, such as image contrast and other edge- and image-based objective functions. In this paper, we propose using an automated model-based flow to obtain the optimal SRAF insertion rules for a design and reduce the time and effort required to define the best rules. In this automated flow, SRAF placement is optimized by iteratively generating the space-width rules and assessing their performance against process variability metrics. Multiple metrics are used in the flow. Process variability (PV) band thickness is a good indicator of the process window enhancement. Depth of focus (DOF), the total range of focus that can be tolerated, is also a highly descriptive metric for the effectiveness of the sizing and placement rules generated. Finally, scatter bar (SB) printing margin calculations assess the allowed exposure range that prevents scatter bars from printing on the wafer.

Sub Resolution Assist Features (SRAFs) are now the main option for enabling low-k₁ photolithograpy. These technical challenges for the 45nm node, along with the insurmountable difficulties in EUV lithography, have driven the semiconductor mask-maker into the low-k₁ lithography era under the pressure of ever shrinking feature sizes. Extending lithography towards lower k₁ puts a strong demand on the resolution enhancement technique (RET), and better exposure tool. However, current mask making equipments and technologies are facing their limits. Particularly, due to smaller feature size, the critical dimension (CD) linearity of both main cell patterns and SRAFs on a mask is deviated from perfect condition differently. There are certain discrepancies of CD linearity from ideal case. For example, as the CD size gets smaller, the bigger CD discrepancy is to be. There are many technologies, such as hard-mask process and negative-resist process and so on. One of them is an assist feature correction, which can be applied to achieve better CD control. In other words, in order to compensate this CD linearity deviation, the new correction algorithm with SRAFs is applied in data process flow. In this paper, we will describe in detail the implement of our study and present results on a full 65nm node with experimental data.

Model-based Optical Proximity Correction (OPC) usually takes into consideration optical and resist process proximity effects. However, the etch bias proximity effect usually can not be completely eliminated by etch process optimization only and needs to be compensated for in OPC flow for several critical layers. Since the understanding of the etch process effect is getting better and accurate etch bias modeling is available now, lithographers start to migrate from rule-based correction to model-based correction. Conventionally when etch bias is considered in model-based correction, optical/resist/etch effect is corrected in one step by using the input layout as the final etch target. In this paper, we proposed a new flow in which etch and optical/resist process effect are separated in both model calibration and layout correction. This double separation allows easier control over etch and resist target, resulting in drastic reduction of OPC runtime. In addition it enables post-OPC verification at both resist and etch level. Advantages of the new integrated model-based retarget/OPC flow in RET implementation are also discussed.

A newly developed sub-resolution assist feature (SRAF) placement technique with two-dimensional transmission cross coefficient (2D-TCC) is described in this paper. In SRAF placement with 2D-TCC, Hopkins' aerial image equation with four-dimensional TCC is decomposed into the sum of Fourier transforms of diffracted light weighted by 2D-TCC, introducing an approximated aerial image so as to place SRAFs into a given reticle layout. SRAFs are placed at peak positions of the approximated aerial image for enhanced resolution. Since the approximated aerial image can handle the full optical model, SRAFs can be automatically optimized to the given optical condition to generate the optimized reticle. The validity of this technique was confirmed by experiment using a Canon FPA6000-ES6a, 248 nm with a numerical aperture (NA) of 0.86. A binary reticle optimized by this technique with mild off-axis illumination was used in the experiment. Both isolated and dense 100 nm contacts (k₁ = 0.35) were simultaneously resolved with the aid of this technique.

Optical Proximity Correction (OPC) relies on predictive modeling to achieve consistent wafer results. To that end, understanding all sources of variation is essential to the successful implementation of OPC. This paper focuses on challenging SRAM layouts of contacts to study the sources of wafer variation. A range of shape geometries and contact configurations are studied. Contact shapes are no longer restricted to simple rectangles on the mask, some more complex OPC outputs may include shapes like H's or T's or even more fragmented figures. The result is a large group of parameters that can be measured at both mask and wafer level. The dependence of mask variation on geometry is studied through the statistical distributions of parameter variations. The mask metrology output is expanded from traditional linear dimensional measurements to include area, line edge roughness, corner rounding, and shape-to-shape metrics. Wafer mask error enhancement factor (MEEF) is then calculated for the various contact geometries. This collection of data makes it possible to study variation on many levels and determine the underlying source of wafer variations so that, ultimately, they can be minimized.

The OPC model is very critical in the sub 45nm device because the Critical Dimension Uniformity (CDU) is so tight to meet the device performance and the process window latitude for the production level. The OPC model is generally composed of an optical model and a resist model. Each of them has physical terms to be calculated without any wafer data and empirical terms to be fitted with real wafer data to make the optical modeling and the resist modeling. Empirical terms are usually related to the OPC accuracy, but are likely to be overestimated with the wafer data and so those terms can deteriorate OPC stability in case of being overestimated by a small cost function. Several physical terms have been used with ideal value in the optical property and even weren't be considered because those parameters didn't give a critical impact on the OPC accuracy, but these parameters become necessary to be applied to the OPC modeling at the low k1 process. Currently, real optic parameter instead of ideal optical parameter like the laser bandwidth, source map, pupil polarization including the phase and intensity difference start to be measured and those real measured value are used for the OPC modeling. These measured values can improve the model accuracy and stability. In the other hand these parameters can make the OPC model to overcorrect the process proximity errors without careful handling. The laser bandwidth, source map, pupil polarization, and focus centering for the optical modeling are analyzed and the sample data weight scheme and resist model terms are investigated, too. The image blurring by actual laser bandwidth in the exposure system is modeled and the modeling result shows that the extraction of the 2D patterns is necessary to get a reasonable result due to the 2D patterns' measurement noise in the SEM. The source map data from the exposure machine shows lots of horizontal and vertical intensity difference and this phenomenon must come from the measurement noise because this huge intensity difference can't be caused by the scanner system with respect to the X-Y intensity difference specification in the scanner. Therefore this source map should be well organized for the OPC modeling and a manipulated source map improves the horizontal and vertical mask bias and even OPC convergence. The focus parameter which is critical for the process window OPC and ORC should be matched to the tilted Bossung plot which is caused by uncorrectable aberration to predict the CD change in the through focus with a new devised method. Pupil polarization data can be applied into the OPC modeling and this parameter is also used for the unpolarized source and the polarized source and specially this parameter helps Apodization loss to be 0 and is evaluated for the effect into the modeling. With the analysis and optimization about the model parameters the robust model is achieved in the sub 45nm device node.

Sub-resolution Assist Feature (SRAF) insertion is one of the most important Resolution Enhancement Techniques (RET) for the 65 nm, 45 nm nodes and beyond. In this paper, we are proposing a novel approach for the optimum placement of 2D SRAF structures using state of the art Calibre RET flow. In this approach, the optimal SRAF shapes are achieved simultaneously during the OPC step. The SRAF and main features are optimized to account for their edge placement and process window metrics (aerial image slope/contrast, out of focus/dose EPE, etc...). The resulting mask shapes deliver some of the properties that can be obtained using the Inverse Lithography Techniques (ILT), such as excellent Process Window Performance, while there is almost no impact on the runtime. The implemented model-based optimization flow remains compatible with the current OPC production flows.

The drive toward advanced technology nodes has drastically increased the computational complexity of optical proximity correction (OPC). Applying full-chip OPC to all critical layers has become the most computational demanding step in the tape-out process. Tuning for fast and accurate OPC recipes is a critical step in the development of a total manufacturing solution. OPC is by design an iterative cycle, where one iteration is a single simulation and polygon fragmentation shift sequence. Typically an accurate OPC recipe requires eight or more iterations to converge to a final best solution. The number of iterations in a recipe directly impacts the full-chip OPC runtime. Engineers often find themselves spending hours tuning an OPC recipe to reduce just one iteration. This paper presents a generic technique called Fast Forward OPC (FFOPC). FFOPC will help to reduce any golden OPC recipe that meets certain requirements to a fixed 4 iterations with minimum accuracy lost. Most importantly this technique can be easily implemented as a plugin with any existing OPC tools.

Topographic mask effects can no longer be ignored at technology nodes of 45 nm, 32 nm and beyond. As feature sizes become comparable to the mask topographic dimensions and the exposure wavelength, the popular thin mask model breaks down, because the mask transmission no longer follows the layout. A reliable mask transmission function has to be derived from Maxwell equations. Unfortunately, rigorous solutions of Maxwell equations are only manageable for limited field sizes, but impractical for full-chip optical proximity corrections (OPC) due to the prohibitive runtime. Approximation algorithms are in demand to achieve a balance between acceptable computation time and tolerable errors. In this paper, a fast algorithm is proposed and demonstrated to model topographic mask effects for OPC applications. The ProGen Topographic Mask (POTOMAC) model synthesizes the mask transmission functions out of small-sized Maxwell solutions from a finite-difference-in-time-domain (FDTD) engine, an industry leading rigorous simulator of topographic mask effect from SOLID-E. The integral framework presents a seamless solution to the end user. Preliminary results indicate the overhead introduced by POTOMAC is contained within the same order of magnitude in comparison to the thin mask approach.

An alternative method of OPC model fitting based on model parameter sensitivity is presented. Theoretical advantages are discussed, including improved model quality and time to results. The parameter sensitivity method is applied using a basic optical model to 32nm logic node experimental data. Results include standard and parameter sensitivity model fits using both constant and variable threshold models. The results show that the parameter sensitivity methodology enables an overall model fit that is more physically-predictive than a standard OPC model fit.

Many issues need to be overcome in creating a production-worthy sub-k1 (<0.25) process. The repeating photo-etch sequential method for clear and dark mask type is susceptible to overlay issues while accuracy of first pattern is critical for the space technology. Both technologies require improved model accuracy and process margin. Because of this, even traditionally noncritical regions of a layout may contain process margin-limiting defects for double patterning technology. An integrated OPC-Verification-Selective OPC procedure is developed to improve quality of results for non-critical regions while retaining fast TAT. The first step utilizes a fast OPC method with reduced TAT. Next, a lithographic verification tool is used to perform a thorough check of the OPC results, including process window analysis. This determines which points limit process margin. Finally, advanced OPC methods are applied to reprocess the areas limiting process margin. These advanced OPC techniques may include broader lithographic analysis, field-based correction and process window consideration. Since advanced OPC methods are only applied to part of the design, TAT is fast. TAT can be further improved by treating critical regions differently. Critical regions will not be processed in the initial OPC or intermediate verification steps, but will be corrected by the advanced OPC methods. This methodology is called Incremental OPC as it applies the most appropriate OPC techniques to each area of the design. As a result, process margin limiting defects, side-lobe printing and subresolution assist feature printing can be eliminated prior to mask tape-out with minimal impact to TAT. In this paper, Incremental OPC is compared to "all-or-nothing" OPC techniques which must be applied across an entire pattern.

Complex Optical Proximity Correction (OPC) must be deployed to meet advanced lithography requirements. The OPC models are used to convert input design shapes into mask data that often deviate significantly from both the initial design and the final wafer image in resist. The process includes selective shape biasing, applying pattern-specific corrections, and, possibly, modeling the effect at multiple exposure conditions. It is important to verify the results of the OPC model and this is done by invoking OPC verification programs. The verification models identify points of failure to specific criteria. Failure can be defined as the simulated resist dimension below which a feature will not survive additional processing. Since these models are built for use in OPC verification, they may only be well-calibrated at feature sizes near target. This can introduce uncertainties in the failure predictions. This paper will explore options for validating the OPC verification models and methods. While wafer prints are an obvious source of feedback on the simulated results, there are also options at mask level. In this paper, we study the effect of programmed defects at wafer level, mask level and through OPC verification method. For each test case, five points in the process window space are chosen to provide comparison data between OPC verification measurements, mask-level intensity contour measurements - e.g. Aerial Image Microscope System (AIMS), and wafer measurement of patterned photoresist. The results permit correlation to measurable metrics and provide an improved understanding of OPC verification validity.

6% attenuated embedded PSM (att-EAPSM) has been widely used in semiconductor wafer manufacturing industry at 130nm, 90nm, 65nm and 45nm nodes. To effectively use the 6% att-EAPSM photomask technology and reduce its manufacturing costs, it is important for the industry to develop a comprehensive mask specification that can fully meet the wafer level lithography requirements without over-constraining the control parameters in 6% att-EAPSM manufacturing process. In this paper, we used computer simulation software, Prolith by KLA-Tencor to study the impact of local phase-angle and transmission errors to wafer lithography process. The simulation results indicated that phase-angle and transmission errors result in a best focus plane shift, and hence reduce the common focus exposure window across the mask. The data also indicated that as the NA (numerical aperture) of the lithography system increases, the same amount of phase-angle error results less amount of focus shift. Based on this study and the practical common focus windows in semiconductor industry, we proposed a new phase-angle and transmission specification of 6% att-EAPSM for 90nm, 65nm and 45nm node wafer process.

In the course of using Optical Proximity Correction (OPC) to optimize contact printing, the obvious solution is not always the correct solution. This paper will explore two different types of contact layers, with two different sets of objectives. In the first type of contact layer, the primary objective is to achieve consistent area uniformity. For these designs, use of contacts without serifs over contacts with traditional corner serifs will result in a mask that has a lower data volume input to the mask writer and an easier time in inspection and repair. We also show that on the wafer, this simpler style of OPC will result in lower variation of area and CD. In second type of contact layer, there are additional complicating factors over the first type of contact layer in that these mask designs include layouts with different sizes of contacts that must be printed simultaneously. As contacts get pushed close together on corner to corner type spacing, traditional serifs will be more likely to drive mask inspection issues and high mask error enhancement factor (meef). One way to address this is with OPC that employs inverse serifs, with the center fragment of the rectangle pushed out and the corners pushed in. This approach reduces meef and provides better image parameters for lower variability through process window. However, this solution does not lend itself to very aggressive correction to achieve aggressive contact aspect ratios. We compare these different OPC strategies (squares, traditional corner serifs and inverse corner serifs) and describe the strengths and weaknesses of each approach.

Model-Based Optical Proximity Correction (MBOPC) is now found in nearly all resolution enhancement recipes used in leading technology integrated circuit fabrication facilities. Many masks now have critical dimensions less than the exposure wavelength, which results in light diffraction that distorts the image projected onto the wafer. The industry is relying more and more on MBOPC to compensate for optical effects that are induced during the exposure of these masks. The MBOPC operation is usually the highest computational time contributor in the RET flow. MBOPC procedures include the fragmentation of layout edges longer than a specific value into a number of sub-edges (fragments). The software engine can move and manipulate each fragment to improve the image transferred to the wafer. In the sparse MBOPC approach, each fragment receives one or more optical simulation sites, which is a one-dimensional array of points where light intensity is sampled and calculated. To correctly capture the resist behavior at each simulation site, there must be enough points to ensure extension of the site to a certain distance from the fragment. Adding more points beyond this distance does not add any benefit, but can significantly increase the runtime. This paper presents an automated method that analyzes layouts for different technology nodes that depend on sparse simulations as their MBOPC engine, and reports the optimized number of simulation points that need to be in the simulation site to get the desired accuracy and optimum runtime performance.

In the past technology generations, Optical Proximity Correction (OPC) has been applied using a model capturing the Optical proximity effects in a single focal plane. In the newer generations, this method is more and more difficult to maintain because of very small process windows in specific situations. These specific situations include 1D configurations (e.g. isolated small lines) but increasingly complex 2D configurations. In the more advanced technology nodes 2D configuration are starting to play a much bigger role. Process windows need to be preserved in all cases, and so this brings about another challenge for the OPC flow. The more traditional OPC approaches may result in un-acceptable small process window in such cases, whereas well characterized Process Window aware OPC (PW-OPC) can provide better results, with much less engineering interventions. In this paper the method of Process Window aware OPC is applied on special designed test structures and on a larger scale (full chip). Verifications and assessments are demonstrated and compared with alternatives. In the past OPC engineers have been pushing for more and more design constraints in order to allow the OPC flow to be successful. The PW-OPC approach is more adaptive compared with traditional single focal plane OPC, and can still converge to an acceptable solution in complicated (unforeseen) layout configurations, without the need to introduce complicated design constraints.

In this paper we discuss four business concepts that will impact the adoption of e-beam direct write (EbDW). They are: (1) The economically advantageous region for EbDW. At what costs and volumes EbDW is economically advantageous is controlled by a two-sided constraint involving the cost of reticles on one hand and the cost of design on the other. (2) The important role of product derivatives and other markets that can be satisfied by designs with heavy IP reuse. The natural long tail in demand for differentiated products is today chopped off by the high costs of reticles. We show data on the elasticity of the product derivative market with respect to certain costs. (3) That because reticle prices typically decline at a 30% per year for the first few years after a new node is introduced, delaying the fabrication of that first reticle set for a new product can save millions, more than paying for EbDW. The applicability of this technique is, however, limited by the need for product requalifaction. (4) Finally, we introduce the business concept of the virtual reticle as a possible component in EbDW pricing.

In 2005, Freescale Semiconductor's newly centralized mask data prep organization (MSO) initiated a project to develop an automated global quality validation system for photomasks delivered to Freescale Semiconductor fabs. The system handles Certificate of Conformance (CofC) quality metric collection, validation, reporting and an alert system for all photomasks shipped to Freescale fabs from all qualified global suppliers. The completed system automatically collects 30+ quality metrics for each photomask shipped. Other quality metrics are generated from the collected data and quality metric conformance is automatically validated to specifications or control limits with failure alerts emailed to fab photomask and mask data prep engineering. A quality data warehouse stores the data for future analysis, which is performed quarterly. The improved access to data provided by the system has improved Freescale engineers' ability to spot trends and opportunities for improvement with our suppliers' processes. This paper will review each phase of the project, current system capabilities and quality system benefits for both our photomask suppliers and Freescale.

Double-patterning lithography / double-exposure lithography is believed to be a solution in order to enable the 32nm-Half-Pitch (HP) and below process node until EUV lithography infrastructure is ready. However, one of the biggest challenges is the overlay budget along with critical dimension (CD) control. In this paper, we propose that instead of using multiple masks for the DPL (STD DPL), multiple split patterns are printed on a single mask so that each pattern is separately or simultaneously exposed onto a wafer in order to reduce the mask-to-mask overlay error. This can also reduce the mask cost and mask manufacturing time compared with STD DPL, at the expense of reducing manufacturing throughput. We propose two ideas about how to place the split patterns in a single mask and simulate corresponding shot throughput comparisons. The results show that by using multi-layer reticle (MLR) strategy for splitting the original layout into 2 split patterns onto a single mask (Method I), we achieve: 1) reduction of the mask-to-mask overlay error factor 2) use of a single mask (reducing mask costs) and 3) reduction of wafer shot throughput to roughly 50% of that achieved by STD DPL. Also by using our new approach of placing multiple-split patterns to form the arrays within the mask scribe (Method II), we achieve: 1) reduction of the mask-to-mask overlay error factor 2) use of a single mask (reducing mask costs) and 3) drastically improved wafer shot throughput (at least 90% of the STD DPL, 180% of Method I).

In recent years, mask critical dimension (CD) linearity and uniformity has become increasingly important. The ITRS roadmap shows the mask CD control requirements exceeding those of the wafer side beyond the 45nm node. Measurements show that there are systematic, uncorrected proximity effects even when a state-of-the-art proximity effect correction (PEC) algorithm is used. The uncorrected proximity effect is predictable with a computational model. The model for e-beam lithography and etch process contains terms to model short-range pattern density effects and plasma shadowing effect in Cr-etch. The model is calibrated using CD measurements on a test mask. The model is valid for arbitrary 2-D patterns. We present a model-based mask process compensation (MPC) method which applies geometric changes to polygons as in OPC. We discuss the goodness of model fit to the calibration data; verification of the calibrated model by SEM images; and the improvement obtained by MPC. The mask writing error, i.e. final inspection CD minus incoming database CD, was reduced by a factor of 2 through the use of MPC.

According to device shrinkage, pattern load, layout geometry and process induced critical dimension (CD) trend are the most important factors deciding mask CD uniformity in a mask manufacturing process. The CD distribution is generally divided by two categories - contribution of pattern load and process induced CD distribution. Etch bias uniformity on a mask is one of the decisive contributors at a standpoint of pattern load. The signature of etch bias uniformity totally depends on the pattern load in a mask. In a low pattern load, etch bias uniformity shows a radial signature which is geometrically distributed regardless of pattern position. In a high pattern load, etch loading effect becomes dominant. The pattern load, however, can have various definitions, which means that a criterion of low and high pattern load can be obscure. Specific layouts which have same pattern load over mask but separated region of low and high load pattern in one mask was designed to specify the effect of pattern load. The radial CD signature is mitigated as pattern load increases locally. At the same time, etch loading trend grows and dominates total CD uniformity. The radial signature and etch loading trend have inverse signs on central region which enables to compensate each signature. Therefore a specific pattern load which can make etch bias uniformity minimized can exist. "Transition pattern load" is detected here. One can use this specific pattern load as an indicator to specify design categories for mass production. In addition, geometry of layout should be considered to achieve uniformity number required in 45nm node technology. In high pattern load over transition pattern load, etch bias shows saddle shape uniformity. Since the saddle shape uniformity is uncorrectable with conventional etch loading kernel, new correction model should be considered to meet the confined CD specification in future device nodes.

Image placement (IP) errors caused by electro-static chuck (ESC) and non-flatness of mask are additional factors in writing extreme ultra-violet (EUV) mask, and minimizing their influences is being fervently addressed. New correction technique of EBM-6000 has been developed for EUV mask writing based on the conventional grid matching correction (GMC) without ESC to obtain good reproducibility to satisfy user's requirement to develop EUV mask at an early stage.

Double exposure / Double pattering methodologies are being adopted to extend 193nm optical lithography until the next generation lithography, most likely the EUV, is solidified. The Double exposure / Double patterning methodologies require tighter image-placement accuracy and Critical Dimension (CD) controls on a mask than the conventional single exposure technique. NuFlare Technology's mask writer, EBM-6000 (1), is capable of achieving the required CD control and high patterning resolution as fine as 35 nm, that are required for the hp 45nm lithography with Double exposure / Double patterning methodologies, when newly developed resist (i.e. "low-sensitivity" resist) is used, as shown at several occasions to date. Further, image-placement control with EBM-6000 has been improved based on extensive error budget analysis to comply with the tight image-placement specifications required by the Double exposure / Double Patterning lithography. This paper will show the results of the analysis and improvement of the image-placement accuracy of EBM-6000 series mask writers.