This PDF file contains the front matter associated with SPIE Proceedings Volume 6922, including the Title Page, Copyright information, Table of Contents, and the Conference Committee listing.

Resolution enhancement in advanced optical lithography will reach a new plateau of complexity at the 32 nm design rule manufacturing node. In order to circumvent the fundamental optical resolution limitations, ultra low k₁ printing processes are being adopted, which typically involve multiple exposure steps. Since alignment performance is not fundamentally limited by resolution, it is expected to yield a greater contribution to the effort to tighten lithographic error budgets. In the worst case, the positioning budget usually allocated to a single patterning step is divided between two. A concurrent emerging reality is that of high order overlay modeling and control. In tandem with multiple exposures, this trend creates great pressure to reduce scribeline target real estate per exposure. As the industry migrates away from metrology targets formed from large isolated features, the adoption of dense periodic array proxies brings improved process compatibility and information density as epitomized by the AIM target¹. These periodic structures enable a whole range of new metrology sensor architectures, both imaging and scatterometry based, that rely on the principle of diffraction order control and which are no longer aberration limited. Advanced imaging techniques remain compatible with side-by-side targets while scatterometry methods require grating-over-grating targets. In this paper, a number of different imaging and scatterometry architectures are presented and compared in terms of random errors, systematic errors and scribespace requirements. It is asserted that an optimal solution must combine the TMU peak performance capabilities of scatterometry with the cost of ownership advantages of target size and multi-layer capabilities of imaging.

The introduction of new techniques such as double patterning will reduce overlay process tolerance much faster than the rate at which critical feature dimensions are shrinking. In order to control such processes measurements with uncertainties under 0.4nm are desirable today and will become essential within the next few years. This very small error budget leads to questions about the capability of the imaging technology used in overlay tools today and to evaluation of potential replacement techniques. In this paper we will show that while imaging technology is in principle capable of meeting this requirement, the real uncertainty in overlay within devices falls well short of the levels needed. A proper comparison between techniques needs to focus on all of the possible sources of error, and especially those that cannot be simply reduced by calibration or by repeating measurements. On that basis there are more significant problems than the relative capability of different measurement techniques. We will discuss a method by which overlay within the device area can be controlled to the required tolerance.

Immersion lithography addresses the limits of optical lithography by providing higher NA's (NA > 1), which enable imaging of smaller features and hence it enables production of 45nm logic devices. One of the key challenges of this advanced technology, however, is controlling the defectivity level produced specifically by the Lithography immersion stepper and track systems. To control and monitor the immersion processes in production, consideration has been given to identifying an alternative to the traditional sensitivity approaches, using Darkfield (DF) and Brightfield (BF) wafer inspection methodologies. This unique method should provide for stable, reliable and sensitive inspection results which are capable of supporting a technology node introduction (product ramp) as well as monitoring the base line performance (in other words, capture excursions). The following study was done to explore laser DUV Brightfield inspection, utilizing the Applied Materials UVision^TM, which has the ability to detect defects as small as 20-40nm size. Additionally a joint project between AMD, ASML and AMAT developed an appropriate inspection strategy that combines, lithographic defect printing simulations and sensitive inspection routines to identify defect problems effectively, drive defect reduction efforts and result in stable production monitoring. We investigated the use of traditional Photo Test Monitor (PTM) as a valid technique to monitor the introduction of the immersion lithography at 45nm. In addition, we explored the correlation between these PTM wafers and the actual production wafers for new types of defects. It was found that the amount of small protrusion defects (~20-40nm size) increased on immersion PTM wafers compared to dry processed PTM wafers. Based on process experiments at AMD and immersion defect simulations provided by ASML we were able to isolate immersion specific defect problems from general lithography related defects also seen in Dry lithography. The results show that unique combination of high sensitivity defect inspection methods and simulation efforts can very effectively drive defect reduction efforts and accelerate yield on advanced technology like immersion lithography. Additionally, it is also possible to provide a production monitoring of 45nm immersion processes with such extreme sensitive inspection of PTM wafers of defects down to 20nm.

The introduction of Immersion lithography, combined with the desire to maximize the number of potential yielding devices per wafer, has brought wafer edge engineering to the forefront for advanced semiconductor manufactures. Bevel cleanliness, the position accuracy of the lithography films, and quality of the EBR cut has become more critical. In this paper, the effectiveness of wafer track based solutions to enable state-of-art bevel schemes is explored. This includes an integrated bevel cleaner and new bevel rinse nozzles. The bevel rinse nozzles are used in the coating process to ensure a precise, clean film edge on or near the bevel. The bevel cleaner is used immediately before the wafer is loaded into the scanner after the coating process. The bevel cleaner shows promise in driving down defectivity levels, specifically printing particles, while not damaging films on the bevel.

At PTB a new type of DUV scatterometer has been developed. The concept of the system is very variable, so that many different types of measurements like e. g. goniometric scatterometry, ellipsometric scatterometry, polarisation dependent reflectometry and ellipsometry can be performed. The main applications are CD, pitch and edge profile characterisation of nano-structured surfaces mainly, but not only, on photomasks. Different operation wavelength down to 193nm can be used. The system is not only a versatile tool for a variety of different at-wavelength metrology connected with state-of-the-art photolithography. It allows also to adapt and to vary the measurand and measurement geometry to optimise the sensitivity and the unambiguity for the measurement problem. For the evaluation of the measurements the inverse diffraction problem has to be solved. For this purpose we developed a special FEM-based software, which is capable to solve both the direct diffraction problem and the inverse diffraction problem. The latter can be accomplished using different optimisation schemes. Additionally this software allows also to estimate the quality of the measured data and the model based measurement uncertainty. This paper gives an overview about the PTB DUV scatterometer, it's metrological potential and the evaluation methods applied using the software DIPOG2.1.

Over the last few years, the need for shape metrology for process control has increased. A key component of shape metrology is sidewall angle (SWA). However, few instruments measure SWA directly. The critical dimension atomic force microscope (CD-AFM) is one such instrument. The lateral scanning capability and the shape of the CD-AFM probe enable direct access to the feature sidewall. This produces profile information that could be used as a process monitor. Due to their relative insensitivity to material properties, CD-AFMs have been used as reference measurement systems (RMS) for measurands such as width. We present a technique for calculating the uncertainty of sidewall angle measurements using a CD-AFM. We outline an overall calibration strategy; address the uncertainty sources for such measurements, including instrument-related and parameter extraction; related; and discuss the way the calibration is transferred to workhorse instruments.

We present a summary of various methods for inverting top and bottom critical dimension (CD) data to extract dose and focus information. We explain analytical, numerical, and library inversion techniques in detail, and explore their relative merits for the purposes of online and offline focus monitoring use models. We also detail the modeling requirements associated with each inversion technique, and -- for cases where the model form is flexible -- present a cross-validation methodology for optimizing the response model to fit experimental data. We present modeling and inversion results from seven exemplary photolithography processes, and study the results from each methodology in detail. While each method has its own set of advantages and disadvantages, we show that the library method represents the optimum choice to satisfy a variety of use models while minimizing cost.

Optical Proximity Correction (OPC) Model Calibration has required an increasing number of measurements as the critical dimension tolerances have gotten smaller. Measurement of two dimensional features have been increasing at a faster rate than features with one dimensional character as the technologies require better accuracy in the OPC models for line-end pull-back and corner rounding. New techniques are becoming available from metrology tool manufacturers to produce GDSII contours of shapes from wafers and modeling software has been improved to use these contours. The challenges of implementing contour generation from the SEM tools will be discussed including calibration methods, physical dimensions, algorithm derivations, and contour registration, resolution, scan direction, and parameter space coverage.

Semiconductor manufacturing is always looking for more effective ways to monitor and control the manufacturing process. Helium Ion Microscopy (HIM) presents a new approach to process monitoring which has several potential advantages over the traditional scanning electron microscope (SEM) currently in use in semiconductor research and manufacturing facilities across the world. Due to the very high source brightness, and the shorter wavelength of the helium ions, it is theoretically possible to focus the ion beam into a smaller probe size relative to that of an electron beam of an SEM. Hence, resolution 2 to 4 times that of comparable SEMs is theoretically possible. In an SEM, an electron beam interacts with the sample and an array of signals are generated, collected and imaged. This interaction zone may be quite large depending upon the accelerating voltage and materials involved. Conversely, the helium ion beam interacts with the sample, but it does not have as large an excitation volume and thus, the image collected is more surface sensitive and can potentially provide sharp images on a wide range of materials. Compared to an SEM, the secondary electron yield is quite high - allowing for imaging at extremely low beam currents and the relatively low mass of the helium ion, in contrast to other ion sources such as gallium potentially results in minimal damage to the sample. This presentation will report on some of the preliminary work being done on the HIM as a research and measurement tool for semiconductor process metrology being done at NIST.

Demanding sub-45 nm node lithographic methodologies such as double patterning (DPT) pose significant challenges for overlay metrology. In this paper, we investigate scatterometry methods as an alternative approach to meet these stringent new metrology requirements. We used a spectroscopic diffraction-based overlay (DBO) measurement technique in which registration errors are extracted from specially designed diffraction targets for double patterning. The results of overlay measurements are compared to traditional bar-in-bar targets. A comparison between DBO measurements and CD-SEM measurements is done to show the correlation between the two approaches. We discuss the total measurement uncertainty (TMU) requirements for sub-45 nm nodes and compare TMU from the different overlay approaches.

Particle contamination on surfaces used in extreme ultraviolet (EUV) mask blank deposition, mask fabrication, and patterned mask handling must be avoided since the contamination can create significant distortions and loss of reflectivity. Particles on the order of 10nm are problematic during MLM mirror fabrication, since the introduced defects disrupt the local Bragg planes. The most serious problem is the accumulation of particles on surfaces of patterned blanks during EUV light exposure, since > 25nm particles will be printed without an out-of-focus pellicle. Particle contaminants are also a problem with direct imprint processes since defects are printed every time. Plasma Assisted Cleaning by Electrostatics (PACE) works by utilizing a helicon plasma as well as a pulsed DC substrate bias to charge particle and repel them electrostatically from the surface. Removal of this nature is a dry cleaning method and removes contamination perpendicular from the surface instead of rolling or sweeping the particles off the surface, a benefit when cleaning patterned surfaces where contamination can be rolled or trapped between features. Also, an entire mask can be cleaned at once since the plasma can cover the entire surface, thus there is no need to focus in on an area to clean. Sophisticated particle contamination detection system utilizing high power laser called DEFCON is developed to analyze the particle removal after PACE cleaning process. PACE has shown greater than 90 % particle removal efficiencies for 30 to 220 nm PSL particles on ruthenium capped quartz. Removal results for silicon surfaces and quartz surfaces show similar removal efficiencies. Results of cleaning 80 nm PSL spheres from silicon substrates will be shown.

We present a new optical technique for dimensional analysis of sub 100 nm sized targets by analyzing through-focus images obtained using a conventional bright-field optical microscope. We present a method to create through-focus image maps (TFIM) using optical images, which we believe unique for a given target. Based on this we present a library matching method that enables us to determine all the dimensions of an unknown target. Differential TFIMs of two targets are distinctive for different dimensional differences and enable us to uniquely identify the dimension that is different between them. We present several supporting examples using optical simulations and experimental results. This method is expected to be applicable to a wide variety of targets and geometries.

The 3D-AFM technique is a very well known technique as a non destructive reference to calibrate CD-SEM and Scatterometry metrology. However, recent hardware, tip design and tip treatment improvements have offered to the technique new capabilities that pave the way for multiple applications in the semiconductor industry. The 3D-AFM technique is today not only a calibrating technique but also a process control technique that can be use either at the R&D level or in fab environment. In this paper, we will address the limits of the 3D-AFM technique for the semiconductor industry depending on the applications by focusing our study on tip to sample interactions. We will identify, test and validate potential industrial solutions that could extend the 3D-AFM potentialities. Subsequently, we will show some interesting applications of the technique related to LER/LWR transfer during silicon gate patterning and related to advance multiwires devices fabrication.

Particle standard is important and widely used for calibration of inspection tools and process characterization and benchmarking. We have developed a method for generating and classifying monodisperse particles of different materials with a high degree of control. The airborne particles are first generated by an electrospray. Then a tandem Differential Mobility Analyzer (TDMA) system is used to obtain monodisperse particles with NIST-traceable sizes. We have also developed a clean and well-controlled method to deposit airborne particles on mask blanks or wafers. This method utilizes electrostatic approach to deposit particles evenly in a desired spot. Both the number of particles and the spot size are well controlled. We have used our system to deposit PSL, silica and gold particles ranging from 30 nm to 125 nm on 193nm and EUV mask blanks. We report the experimental results of using these particles as calibration standards and discuss the dependency of sensitivity on the types of particles and substrate surfaces.

NIST is currently developing two Reference scanning electron microscopes (SEMs), which are based on FEI Nova 600* variable vacuum, and on FEI Helios* dual-beam instruments. These were installed in the new Advanced Metrology Laboratory at NIST where the temperature variation is under 0.1 C° and the humidity variation is under 1%. Both SEMs are equipped with field emission electron guns and are capable of better than 1 nm spatial resolution. The ESEM has large sample capability, allowing for measurements on 200 mm wafers, 300 mm wafers and 150 mm photolithography masks, with a 100 mm by 100 mm measurement area in the center. The dual-beam instrument's laser stage will work on smaller samples and has a 50 mm by 50 mm measurement area. The variable vacuum instrument is especially suitable for measurements on a large and diverse set of samples without the use of conductive coating. These will be among the most scrutinized of SEMs. A detailed, thorough work of combined measurements and optimization of the SEMs themselves is underway, which includes the assessment of resolution, signal transfer characteristics, distortion and noise characteristics in various working modes. Accurate three-dimensional modeling, including all aspects of beam formation, signal generation, detection and processing is under development. Establishment of modeling and measurement methods to ascertain the threedimensional shape and size of the electron beam is also underway. All these are needed to properly interpret the obtained data in accurate, physics-based measurements and will permit three-dimensional size and shape determination on a scale ranging from a few nanometers up to a few centimeters. Accuracy and traceability will be ensured through calibrated laser interferometry.

Average CD of CD SEM and scatterometry CD (OCD) have been adopted for advanced CD control. The advantages and disadvantages of these two CD metrologies have been well discussed. The target of CD uniformity (CDU) for advanced technology has been driven to 1 nm, i.e. about three and half the size of a silicon atom, which is 0.29 nm. In the real production environment, engineers need to face sub-nanometer (< 1 nm) CD variations and do the necessary process corrections to meet the 1-nm CDU requirement. In other words, advanced CD process control has already been in the world of atomic scale. It turns out that methodology to ensure the accuracy of sub-nanometer CD has become essential for advanced CD control. In this paper, we introduced a methodology to produce 0.25, 0.5, and 1 nm programmed pitch offsets through mask design. These offsets are attainable with current process capability. Pitch offsets instead of line/space width offsets were used because the pitch is relatively process insensitive. The pitch has already been widely used as a CD SEM magnification calibration standard, e.g. Hitachi m-scale 240-nm pitch and VLSI 100-nm pitch standards. We produced large and small pitch splits to meet different magnification linearity requirements. We also used optical CD to verify the programmed pitch offset. Using the raw spectrum of OCD, systematic pitch signal changes in 0.25-nm steps can be detected, ensuring that 0.25-nm pitch offset standards are meaningful. Interestingly, 0.25 nm is smaller than the 0.29-nm Si atom. We also used this standard wafer to do the sampling size or data quality evaluation for different CD SEM measurement methodologies, e.g. 150K by 150K or 80K by 35K magnifications that in turn dictates the sample size. Pitch sensitivity is strongly related to the sampling size and line-edge roughness (LER). For example, 0.25-nm pitch sensitivity needs a larger sampling size than those of 0.5-nm and 1- nm pitch sensitivities. By means of this standard wafer, we can easily quantify metrology quality as well as choose the right metrology and sampling size for advanced process control.

To use atomic force microscope (AFM) to measure dense patterns of 32-nm node structures, there is a difficulty in providing flared probes that go into narrow vertical features. Using carbon nanotube (CNT) probes is a possible alternative. However, even with its extremely high stiffness, van der Waals attractive force from steep sidewalls bends CNT probes. This probe deflection effect causes deformation (or "swelling") of the measured profile. When measuring 100-nm-high vertical sidewalls with a 24-nm-diameter and 220-nm-long CNT probe, the probe deflection can cause a bottom CD bias of 13.5 nm. This phenomenon is inevitable when using long, thin probes whichever scanning method is used. We have developed a method of deconvolving this probe deflection effect that is well suited to our AFM scanning mode, Advanced Step-in^TM mode. In this scanning mode, the probe is not dragged on the sample surface but approaches the sample surface vertically at each measurement point. The CNT probe deformation is stable because we do not use cantilever oscillation that can cause instability, but we detect static flexure of the cantilever. Consequently, it is possible to estimate the amount of CNT probe deflection by detecting the degree of cantilever torsion. Using this information, we have developed a technique for deconvolving the probe deformation effect from measured profiles. This technique in combination with deconvolution of the probe shape effect makes vertical sidewall profile measurement possible.

The present paper is a continuation of an investigation to validate CD AFM image reconstruction using Transmission Electron Microscopy (TEM) as the Reference Metrology System (RMS). In the present work, the validation of CD AFM with TEM is extended to include a 26 nm diameter carbon nanotube (CNT) tip for non-reentrant feature scans. The use of DT (deep trench) mode and a CNT tip provides detailed bottom feature resolution and close mid-CD agreement with both TEM and prior CD mode AFM scans (using a high resolution Trident tip). Averaging AFM scan lines within the ~80 nm thickness region of the TEM sample is found to reduce systematic error with the RMS. Similarly, errors in alignment between AFM scan lines and TEM sample are corrected by a moving average method. Next, the NanoCD standard is used for complete 2D tip shape reconstruction (non-reentrant) utilizing its traceable feature width and well-defined upper-corner radius. The shape of the NanoCD is morphologically removed from the tip/standard image, thus providing the tip's shape with bounded dimensional uncertainty. Finally, an update of the measurement uncertainty budget for the current generation CD AFM is also presented, thus extending the prior work by NIST.

Atomic Force Microscope (AFM) is a powerful metrology tool for process monitoring of semiconductor manufacturing because of its non-destructive, high resolution, three-dimensional measurement ability. In order to utilize AFM for process monitoring, long-term measurement accuracy and repeatability are required even under the condition that probe is replaced. For the measurement of the semiconductor's minute structure at the 45-nm node and beyond, AFM must be equipped with a special probe tip with smaller diameter, higher aspect ratio, sufficient stiffness and durability. Carbon nanotube (CNT) has come to be used as AFM probe tip because of its cylindrical shape with small diameter, extremely high stiffness and flexibility. It is said that measured profiles by an AFM is the convolutions of sample geometry and probe tip dimension. However, in the measurement of fine high-aspect-ratio LSI samples using CNT probe tip, horizontal measurement error caused by attractive force from the steep sidewall is quite serious. Fine and long CNT tip can be easily bent by these forces even with its high stiffness. The horizontal measurement error is caused by observable cantilever torsion and unobservable tip bending. It is extremely difficult to estimate the error caused by tip bending because the stiffness of CNT tips greatly varies only by the difference of a few nanometers in diameter. Consequently, in order to obtain actual sample geometry by deconvolution, it is essential to control the dimension of CNT tips. Tip-end shape also has to be controlled for precise profile measurement. We examined the method for the measurement of CNT probe tip-diameter with high accuracy and developed the screening technique to obtain probes with symmetric tip-ends. By using well-controlled CNT probe and our original AFM scanning method called as Advanced StepIn^TM mode, reproducible AFM profiles and deconvolution results were obtained. Advanced StepIn^TM mode with the dimension- and shape-controlled CNT probe can be the solution for process monitoring of semiconductor manufacturing at the 45-nm node and beyond.

As overlay budgets continue to shrink, there is an increasing need to more fully characterize the tools used to measure overlay. In a previous paper, it was shown how a single-layer Blossom overlay target could be utilized to measure aberrations across the field of view of an overlay tool in an efficient and low-cost manner. In this paper, we build upon this method, and discuss the results obtained, and experiences gained in applying this method to a fleet of currently operational overlay tools. In particular, the post-processing of the raw calibration data is discussed in detail, and a number of different approaches are considered. The quadrant-based and full-field based methods described previously are compared, along with a half-field method. In each case we examine a number of features, including the trade off between ease of use (including the total number of measurements required) versus sensitivity / potential signal to noise ratio. We also examine how some techniques are desensitized to specific types of tool or mark aberration, and suggest how to combine these with non-desensitized methods to quickly identify these anomalies. There are two distinct applications of these tool calibration methods. Firstly, they can be used as part of the tool build and qualification process, to provide absolute metrics of imaging quality. Secondly, they can be of significant assistance in diagnosing tool or metrology issues or providing preventative maintenance diagnostics, as (as shown previously) under normal operation the results show very high consistency, even compared to aggressive overlay requirements. Previous work assumed that the errors in calibration, from reticle creation through to the metrology itself, would be Gaussian in nature; in this paper we challenge that assumption, and examine a specific scenario that would lead to very non-Gaussian behavior. In the tool build / qualification application, most scenarios lead to a systematic trend being superimposed over Gaussian-distributed measurements; these cases are relatively simple to treat. However, in the tool diagnosis application, typical behavior will be very non- Gaussian in nature, for example individual outlier measurements, or exhibiting bimodal or other probability distributions. In such cases, we examine the effect that this has on the analysis, and show that such anomalous behaviors can occur "under the radar" of analyses that assume Gaussian behavior. Perhaps more interestingly, the detection / identification of non-Gaussian behavior (as opposed to the parameters of a best fit Gaussian probability density function) can be a useful tool in quickly isolating specific metrology problems. We also show that deviation of a single tool, relative to the tool fleet, is a more sensitive indicator of potential issues.

Overlay process control up to and including the 45nm node has been implemented using a small number of large measurement targets placed in the scribe lines surrounding each field. There is increasing concern that this scheme does not provide sufficiently accurate information about the variation of overlay within the product area of the device. These concerns have led to the development of new, smaller targets designed for inclusion within the device area of real products [1,2]. The targets can be as small as 1-3μm on a side, which is small enough to permit their inclusion inside the device pattern of many products. They are measured using a standard optical overlay tool, and then calibrated. However, there is a tradeoff between total measurement uncertainty (TMU) and target size reduction [1]. Also the calibration scheme applied impacts TMU. We report results from measurements of 3μm targets on 45nm production wafers at both develop and etch stages. An advantage of these small targets is that at the etch stage they can readily be measured using a SEM, which provides a method for verifying the accuracy of the measurements. We show how the 3μm in-chip targets can be used to obtain detailed information for in-device overlay variability and to maintain overlay control in successive process generations.

The overlay metrology budget is typically 1/10 of the overlay control budget resulting in overlay metrology total measurement uncertainty requirements of 0.57 nm for the most challenging use cases of the 32nm technology generation. Theoretical considerations show that overlay technology based on differential signal scatterometry (SCOL^TM) has inherent advantages, which will allow it to achieve the 32nm technology generation requirements and go beyond it. In this work we present results of an experimental and theoretical study of SCOL. We present experimental results, comparing this technology with the standard imaging overlay metrology. In particular, we present performance results, such as precision and tool induced shift, for different target designs. The response to a large range of induced misalignment is also shown. SCOL performance on these targets for a real stack is reported. We also show results of simulations of the expected accuracy and performance associated with a variety of scatterometry overlay target designs. The simulations were carried out on several stacks including FEOL and BEOL materials. The inherent limitations and possible improvements of the SCOL technology are discussed. We show that with the appropriate target design and algorithms, scatterometry overlay achieves the accuracy required for future technology generations.

Overlay requirements for semiconductor devices are increasing faster than anticipated. Overlay becomes much harder to control with current methods and therefore novel techniques are needed. In this paper, we present our investigation methods for High Order Control, and the candidates for improvement. This paper will present the study for each components of high order control. High order correction is one component for high order control and several correction methods were compared for this study. High order alignment is another important component for higher order control instead of using conventional linear model for the alignment. Alignment and overlay measurement sampling decision becomes a more critical issue for sampling efficiency and accuracy. Optimal sampling for high order was studied for high order control. Using all these studies, various applications for optimal high order control have also been studied. This study will show the general approach for high order control with theory and actual experimental data.

We develop a novel target, dual-overlay grating, used in the overlay measurement with an optical bright-field imaging tool. The dual-overlay grating is the combination of two overlay gratings with different pitch. The two overlay grating are approached each other and the separation gap between them is sub-micrometer. The image in the proximity of the boundary of two overlay gratings is measured at in-focus position, and a method is built to analyze the image. The gradient value of image and a merit value are calculated. A series of dual-overlay grating is measured and analyzed with different overlay offset. We found the relation between the merit value and overlay offset is linear in certain region, and the dual-overlay grating has the nano-scale resolution to the overlay offset. Thus, the dual-overlay grating has potential application in overlay metrology for the process control in the future semi-conductor manufacturing.

This paper discusses the scatterometry-based measurement of a complex thin-spacer PFET structure containing an embedded SiGe (eSiGe) trench. The thickness of the spacer and the overfill of the eSiGe trench are critical measurement parameters for such a structure. Although the corresponding NFET structure does not contain the eSiGe-filled trench, it is also found to be a good barometer of thin-spacer measurement capability and so is also used in the study. First, the paper discusses the dispersion analysis challenges and approaches for these 45 nm node structures. Next, two sets of scatterometry hardware, one in production and one under development, are used to measure the critical parameters in order to understand the differences in measurement performance between the systems. Transmission Electron Microscopy (TEM) analysis is used as a reference metrology to assess the accuracy performance of the hardware. Results show that the advanced optics of the newer system significantly improves the dynamic repeatability of the parameters compared to the older system, while the newer system's extended wavelength range down into the deep UV (DUV) can provide a noticeable improvement in measurement accuracy due to the significantly greater parameter sensitivity in this wavelength range.

Implementations of scatterometry in the back end of the line (BEOL) of the devices requires design of advanced measurement targets with attention to CMP ground rule constraints as well as model simplicity details. In this paper we outline basic design rules for scatterometry back end targets by stacking and staggering measurement pads to reduce metal pattern density in the horizontal plane of the device and to avoid progressive dishing problems along the vertical direction. Furthermore, important characteristics of the copper shapes in terms of their opaqueness and uniformity are discussed. It is shown that the M1 copper thicknesses larger than 100 nm are more than sufficient for accurate back end scatterometry implementations eliminating the need for modeling of contributions from the buried layers. AFM and ellipsometry line scans also show that the copper pads are sufficiently uniform with a sweet spot area of around 20 μm. Hence, accurate scatterometry can be done with negligible edge and/or dishing contributions if the measurement spot is placed any where within the sweet spot area. Reference metrology utilizing CD-SEM and CD-AFM techniques prove accuracy of the optical solutions for the develop inspect and final inspect grating structures. The total measurement uncertainty (TMU) values for the process of record line width are of the order of 0.77 nm and 0.35 nm at the develop inspect and final inspect levels, respectively.

Gate patterning is critical to the final yield and performance of logic devices. Because of this, gate linewidth control is viewed by many as the most critical application for integrated metrology on etch systems. For several years, integrated metrology and wafer-level process control have been used in high volume manufacturing of 90 and 65nm polysilicon gate etch [1], [3], [17], [22]. These wafer-level CD control systems have shown the ability to significantly reduce CD variation. With gate linewidth under control (< 2nm 3σ wafer-to-wafer), the next parameter to impact gate electrical performance is side wall angle (SWA). SWA had not been considered a critical control parameter due to the difficulty of measurement with conventional scanning electron microscope (SEM). With scatterometry, SWA measurement of litho and etch profiles are included with the critical dimension (CD) measurements. Recently, it has become visible that the polysilicon SWA correlates to electrical device parameters, and is thus, an important parameter to control. This paper will examine the current relationship between litho and etch profile control, determine potential limitations for future technology nodes, and introduce novel etch process control techniques based on multiple input multiple output (MIMO) modeling.

New material innovations such as Embedded Silicon Germanium (eSiGe) provide a substantial metrology challenge for the 45 nm node technology and beyond. We discuss the details of how scatterometry provides in-line metrology solution to measure key features of the eSiGe structure. Critical features to measure are eSiGe to gate proximity and the un-etched silicon on insulator (SOI) thickness. The proximity measurement is particularly vital because it has a major influence on device performance, yet there was no high throughput in-line metrology solution until scatterometry. Results from multiple scatterometry platforms (three) are presented along with a summary of various metrology performance metrics like precision and accuracy. We also show how scatterometry measurements have been instrumental in supporting process development efforts. The comparison of scatterometry measurements to reference data from multiple metrology techniques is presented in order to evaluate the accuracy performance of various supplier platforms. Reference metrology techniques used are thin-film measurements from un-patterned targets, transmission electron microscopy (TEM) and cross-section scanning electron microscopy (XSEM). Tool matching uncertainty (TMU) analysis and weighted reference measurement system (wRMS) technique have been utilized to assist in the interpretation of correlation data. Scatterometry results from various wafers that were generated to modulate spacer width and etch cavity are also presented. The results demonstrate good sensitivity for key measurement features, especially eSiGe proximity and un-etched SOI thickness, which have very tight process control requirements.

Aggressive CMOS transistor scaling requirements have motivated the IC industry to look beyond simply reducing the film thickness or implementing different gate stack materials towards fundamentally redesigning the transistor architecture by forcing the silicon channel to protrude upwards from the planar (2D) substrate. These 3D transistors, namely FinFETs, ideally offer at least a 2X improvement in the drive current since more than one surface is available, for which the minority carrier population can be adjusted by an applied voltage. However, the ability to modulate this voltage is known to suffer due to the non-uniform film deposition on the three sides of the Si Fin. This concern is of immediate interest because it impedes device performance and future integration since subtle differences among the thicknesses on each side of the Fin will negatively impact threshold voltage and the capability to tune the effective work function. It is therefore necessary to have an in-line metrology capability that can properly characterize and understand the deposition of both the high-k and metal gate film on the sidewalls of the Fin in order for FinFETs to ultimately replace planar CMOS devices. We will report on the ability of scatterometry to accurately measure the high-k and metal film thickness on the sidewall of the FinFET. The results will be discussed in detail with emphasis on sensitivity towards fin critical dimension (CD) and sidewall thickness, and comparison of the conclusions reached from the analysis with cross-sectional transmission electron microscopy (TEM) data.

CMOS 65nm technology node requires the introduction of advanced materials for critical patterning operations. The study is focused on the multilayer Anti Reflective Coating (ARC) stack, used in photolithography, for the gate patterning such as Advanced Patterning Film (APF). The interest on this new and complex ARC stack lies in the benefit to guarantee low CD dispersion thanks to a better reflectivity control and resist budget which leads to a larger lithographic process window. However, it implies numerous metrology challenges. The paper deals with the challenges of monitoring the gate Critical Dimension (CD) on this stack. The validation of the scatterometry model versus stack thicknesses and indexes variations, through experiments, is also described. The final result is the complete characterization of the materials for thickness and scatterometry CD control, for photo feedback and for etch feed-forward deployment in an industrial mode. The analysis shows that scatterometry measurements on a standard 65 nm gate process ensure a better effectiveness than the CD Scanning Electron Microscopy (SEM) ones when injected in the Advanced Process Control (APC) system from photo to etch.

The International Technology Roadmap for Semiconductors (ITRS) provides a set of Metrology specifications as targets for each technology node. In the current edition (2007) of the ITRS the conventional precision (reproducibility) is replaced with a new metric - measurement uncertainty for dimensional metrology. This measurement uncertainty contains single tool precision, tool-to-tool matching, sampling uncertainty, and inaccuracy (sample-to-sample bias variation and other effects). Clearly, sampling uncertainty is a major component of measurement uncertainty. This paper elaborates on sampling uncertainty and provides statistical estimates for sampling uncertainty. The authors in this paper address the importance and the methods of proper sampling. The correct sampling captures and allows for the expression of the information needed for adequate patterning process control. Along with typical manufacturing process control cases (excursion control, advanced and statistical process control), several other applications are explored such as optical and electron beam line width measurement calibration, measurement tool evaluations, lithographic scanner assessment and optical proximity correction implementation. The authors show how appropriate choices among measurement techniques, sampling methods, and interpretation of measurement results give meaningful information for process control and demonstrate how an incorrect choice can lead to wrong conclusions.

Critical dimension (CD) or linewidth is one the most critical variable in the lithography process with the most direct impact on the device speed and performance of integrated circuits. Photoresist thickness is one of the photoresist properties that can have an impact on the CD uniformity. Due to thin film interference, CD varies with photoresist thickness. In this paper, we present an innovative approach to control photoresist thickness in real-time during thermal processing steps in the lithography sequence to control CD. As opposed to run-to-run control where information from the previous wafer or batch is used for control of the current wafer or batch, the approach here is real-time and make use of the current wafer information for control of the current wafer CD. The experiments demonstrated that such an approach can reduce CD non-uniformity from wafer-to-wafer and within-wafer.

This paper present an evaluation of our CMOS 45nm gate patterning process performance based on immersion lithography in a production environment. A CD budget breakdown is shown detailing lot to lot, wafer to wafer, intrawafer, intrafield and proximity CD uniformity characterization. Emphasis is given on scatterometry library development and deployment. We also look more into detail to focus effect on CD control. Finally status of overlay performance with immersion lithography is also presented.

This paper examines improvement in post-etching gate critical dimension (CD) uniformity by post exposure bake (PEB) temperature control. Although intra-wafer and inter-wafer resist CD uniformity is improved by PEB temperature optimization, intra-wafer gate CD uniformity after etching could not be improved due to etcher-attributed factors. To improve these factors, we carried out two-step optimization that combines lithography CD optimization with etching CD optimization. By using this method, the optimization strategy can clarify the targets of optimization in each step. PEB temperature optimization was performed by two step optimization in which etcher-attributed CD variations were canceled out, leading to 66% improvement of gate etching CD uniformity successfully. Without any changes in modification parameter, this PEB temperature optimization proved to be applicable to several reticle patterns with different pattern density. Moreover, this optimization method proved the applicability to the gate process for a 55nm node logic device for the duration of five months without modification. The result proved its long-term stability and practicality.

Self-Aligned Double Patterning (SADP) scheme is considered as one of the most promising lithographic techniques to meet the challenges for aggressive flash 32 nm semiconductor technology node and beyond. Monitoring the SADP stages implies the necessity to use metrology methods that meet advanced technology nodes requirements. One important growing metrology factor is the Line Edge Roughness (LER). This factor is most relevant due to the unique processing of the outer vs. inner edges in the SADP process. The aim of the present study is to evaluate the right metrics to tightly monitor SADP process, including the roughness behavior of the features on SADP layers, and seek correspondence of LER characteristics between SADP sequential process stages. Additional element of this study will be to examine the performance of CD-SEM roughness analysis on small features, with the usage of improved LER measurement method that takes into account the contribution of SEM imaging noise to the obtained LER values.

We have proposed a new inspection method of in-line focus and dose controls for semiconductor volume production. We referred to this method as the focus and dose line navigator (FDLN). Using FDLN, the deviations from the optimum focus and exposure dose can be obtained by measuring the topography of the resist pattern on a process wafer that was made under a single-exposure condition. Generally speaking, FDLN belongs to the technology of solving the inverse problem as scatterometry. The FDLN sequence involves following the two steps. Step 1:creating a focus exposure matrix (FEM) using a test wafer for building the model as supervised data. The model means the relational equation between the multi measurement results of resist patterns ( e.g. Critical dimension (CD), height, sidewall angle) and FEM's exposure conditions. Step 2: measuring the resist patterns on a production wafers and feeding the measurement data into the library to extrapolate focus and dose. In this time, we have evaluated the estimated accuracy of Focus and dose for actual process wafer using the advanced CD-SEM and we also have developed new algorithm for considering against thermal dose error.

Increasing inspection sensitivity may be necessary for capturing the smaller defects of interest (DOI) dictated by reduced minimum design features. Unfortunately, higher inspection sensitivity can result in a greater percentage of non-DOI or nuisance defect types during inline monitoring in a mass production environment. Due to the time and effort required, review sampling is usually limited to 50 to 100 defects per wafer. Determining how to select and identify critical defect types under very low sampling rate conditions, so that more yield-relevant defect Paretos can be created after SEM review, has become very important. By associating GDS clip (design layout) information with every defect, and including defect attributes such as size and brightness, a new methodology called Defect Criticality Index (DCI) has demonstrated improved DOI sampling rates.

The optimizing of sampling plans for process control and lot acceptance inspections is emerging as an important subject concerning the recent lithography process. With proper acceptance variables, one can reduce sample size using inspection by variables rather than inspection by attributes. The inspection by variables is cost-effective and desirable. However, it is difficult to apply to a non-normal population. Many cases exist where CD distribution cannot be regarded as normal. If one applies the acceptance sampling inspection with conventional acceptance variables@in those cases, the inspections become tighter or are reduced, which is contrary to expectations. The problem of non-normality, which is an essential property of CD distributions, should be treated extensively. We found that the above problem can be overcome by modifying the conventional acceptance variables through the inclusion of the 3rd moment. As a result, 50% reduction of sample size can be realized by introducing the lot acceptance sampling with new variables.

The optical defect identification on wafer still remains a useful tool, even if the structure sizes have the order of magnitude of the used wavelengths of the light and far beyond it. Structures are not resolved in this way, but one receives a contrast in the microscopic image of a defect with a certain illumination configuration. We show simulations of such images at structures relevant for practice and present methods to accelerate the computations. These accelerations can cause a loss of accuracy, but they can give hints to useful illumination configurations.

In this paper, we propose a novel defect inspection method by considering the advantage that the same pattern is repeatedly transferred onto a large number of areas in resist pattern fabrication. This approach consists of following two steps. The first step is to obtain a high-resolution pattern image from multiple low-resolution images of the same pattern on an observed noisy SEM image using a reconstruction-based super-resolution technique where the B-spline interpolation is utilized. It can reconstruct a high-resolution image from the low resolution and noisy images with a high degree of accuracy. The next step is to inspect defects by comparing the high-resolution pattern image with lowresolution images to be verified. We applied our method to model and SEM images to show its validity.

Electron beam-induced contamination is one of the most bothersome problems encountered in the use of the scanning electron microscope (SEM). Even in "clean-vacuum" instruments it is possible that the image gradually darkens because a polymerized hydrocarbon layer with low secondary electron yield is deposited. This contamination layer can get so thick that it noticeably changes the size and shape of the small structures of current and future state-of-the art integrated circuits (ICs). Contamination greatly disturbs or hinders the measurement process and the erroneous results can lead to wrong process control decisions. NIST has developed cleaning procedures and a contamination specification that offer an effective and viable solution for this problem. By the acceptance, implementation and regular use of these methods it is possible to get rid of electron beam induced contamination.

We developed an in-line inspection method for partial-electrical measurement of contact resistance, which is quantitatively estimated from the voltage contrast formed in an SEM image of an incomplete-contact defect. At first, standard calibration wafers were manufactured for the voltage-contrast calibration. The contact resistance of systematically formed defects was varied from 10⁸ to 10¹⁷ ohms. We quantitatively analyzed the grayscale of these defect images captured by a review SEM. Then, the relationship between the grayscales of the defect images captured from these standard calibration wafers and the contact resistances of the defects was studied. We obtained a uniform, stable grayscale of the SEM images of each standard calibration wafer. As a result, calibration curves for estimating the contact resistance of the incomplete-contact defect were obtained at a probe current condition of 80 pA and charging voltages of 1 and 2 V. The estimated contact resistance under these inspection conditions was between 10¹⁰ and 10¹⁶ ohms. Using this in-line inspection method, we demonstrated wafer mapping of contact resistances calibrated from grayscales of defect patterns. We could not determine whether contact resistances on a wafer widely varied unless we used this method.

In semiconductor manufacturing, control of hotspots by optical proximity correction (OPC) requires accurate measurements of shapes and sizes of fabricated features. These measurements are carried out using CD-SEM. In order to measure 2D shapes, edges of features should be clearly defined in all directions. Positions of edges are often unclear because of charging. Depending on the SEM setup and the pattern under measurement, the effect of charging varies. The influence of measurement conditions can be simulated and optimized. A Monte Carlo electron-beam simulation tool was developed, which takes into account electron scattering and charging. CD-SEM imaging of SiO₂ lines on Si were studied. In experiment, an effect of contrast tone reversal was found, when beam voltage was varied. The same effect was also found in simulations, where contrast reversal was similar to the experimental results. The time dependence of contrast variation was also studied. A good agreement between simulation and measurement was found. The simulation software proved reliable in predicting SEM images, which makes it an important tool to optimize settings of electron-beam tools. Based on such simulations, optimum conditions of SEM setup can be found.

For many years, lithographic resolution has been the main obstacle for keeping the pace of transistor densification to meet Moore's Law. For the 45 nm node and beyond, new lithography techniques are being considered, including immersion ArF lithography (iArF) and extreme ultraviolet (EUV) lithography. As in the past, these techniques will use new types of photoresists with the capability to print 45 nm node (and beyond) feature widths and pitches. In a previous paper ("SEM Metrology for Advanced Lithographies," Proc SPIE, v6518, 65182B, 2007), we compared the effects of several types of resists, ranging from deep ultraviolet (DUV) (248 nm) through ArF (193 nm) and iArF to extreme UV (EUV, 13.5 nm). iArF resists were examined, and the results from the available resist sample showed a tendency to shrink in the same manner as the ArF resist but at a lower magnitude. This paper focuses on variations of iArF resists (different chemical formulations and different lithographic sensitivities) and examine new developments in iArF resists during the last year. We characterize the resist electron beam induced shrinkage behavior under scanning electron microscopy (SEM) and evaluate the shrinkage magnitude on mature resists as well as R&D resists. We conclude with findings on the readiness of SEM metrology for these challenges.

In this research, we improved litho process monitor performance with CD-SEM for hyper-NA lithography. First, by comparing litho and etch process windows, it was confirmed that litho process monitor performance is insufficient just by CD measurement because of litho-etch CD bias variation. Then we investigated the impact of the changing resist profile on litho-etch CD bias variation by cross-sectional observation. As a result, it was determined that resist loss and footing variation cause litho-etch CD bias variation. Then, we proposed a measurement method to detect the resist loss variation from top-down SEM image. Proposed resist loss measurement method had good linearity to detect resist loss variation. At the end, threshold of resist loss index for litho process monitor was determined as to detect litho-etch CD bias variation. Then we confirmed that with the proposed resist loss measurement method, the litho process monitor performance was improved by detection of litho-etch CD bias variation in the same throughput as CD measurement.

As design rules shrink, there is an increase in the complexity. OPC/RET have been facilitating unprecedented yield at k₁ factors, they increase the mask complexity and production cost, and can introduce yield-detracting errors. Currently OPC modeling techniques are based on extensive CD-SEM measurements which are limited to one dimensional structures or specific shape structures e.g. contact holes. As a result the measured information is not representing the whole spatial 2D change in the process. Therefore the most common errors are found in the OPC design itself and in the resulting patterning robustness across the process window. A new methodology for OPC model creation and verification is to extract contours from complex test structures which beside the CD values contain further information about e.g. various proximities. In this work we use 2D contour profiles extracted automatically by the CD-SEM over varying focus and exposure conditions. We will show that the measurement sensitivity and uncertainty of that algorithm through the whole process window fulfills the requirements of the ITRS with respect to CD-SEM metrology tools. This will be done on various test structures normally being used for OPC model generation and OPC stability monitoring. Furthermore a study on systematic influences on the quality of the extracted contours has been started. This study includes the evaluation of various parameters which are considered as possible contributors to the uncertainty of the edge contour extraction. As one of the parameters we identified the pixel size of the SEM images. Furthermore, a new metric for calculating repeatability and reproducibility determination for 2D contour extraction algorithms will be presented. By applying this contour extraction based methodology to different CD-SEM tool generations the influence of SEM beam resolution to the quality of the contours will be evaluated.

Multi patterning lithography (MPL) breaks the k₁=0.25 barrier to become the main candidate for 32nm device fabrication before 2010. When using MPL, overlay (OVL) becomes an essential part of the overall critical dimension (CD) budget and therefore can no longer be treated as a separate process control measure. Furthermore, the CD measured at each of the two consecutive lithography steps must be combined into one single 32nm process control measure and will require further improvements of CD-SEM precision, resolution and accuracy. The metrology challenges involved in measuring double patterning CD and OVL arise from the fact that across chip pitch variations (ACPV) are determined by the two separate lithographic processes [1]. This aspect makes the control of the process significantly more complex and requires careful measurement of the processes, both individually as well as combined. Meeting the ITRS specifications for CD and localized OVL measurements beyond 32nm half pitch is challenging and will require innovative CDSEM algorithmic solutions. This paper is a follow-up from last year's paper that introduced SEM metrology for MPL technology. In this paper, we report on the actual implementation of combined CD and OVL metrology solutions for the latest immersion scanner generation. We will describe the latest OVL measurements performed at ASML and demonstrate the robustness of the novel algorithm for accurate separation and recombination of two individual CD populations related to the consecutive MPL steps.

With the planned introduction of double patterning techniques, the focus of attention has been on tool overlay performance and whether or not this meets the required overlay for double patterning. However, as we require tighter and tighter overlay performance, the impact of the selected integration strategy plays a key part in determining the achievable overlay performance. Very little attention has been given at this time to the impact of for example deposition steps, oxidation steps, CMP steps and the impact that they have on wafer deformation and therefore degraded overlay performance, which directly reduces the available overlay budget. Also, selecting the optimum alignment strategy to follow, either direct or indirect alignment, plays an important part in achieving optimum overlay performance. In this paper we investigate the process impact of various double patterning integration strategies and attempt to show the importance of selecting the right strategy with respect to achieving a manufacturable double patterning process. Furthermore, we report a methodology to minimize process overlay by modelling the non-linear grids for process induced wafer deformation and demonstrate best achievable overlay by feeding this information back to the relevant process steps.

Current ITRS projections indicate that overlay metrology measurement uncertainty requirements will be less than 1 nm by the year 2009. The challenge in attaining this level of precision for semiconductor and thin-film head (TFH) applications is complicated by the use of increasingly complex multilayer dielectric stacks in the fabricated devices. This paper details results from a fundamental study designed to quantify and understand the effects of dielectric film optical properties on overlay metrology uncertainty. Overlay precision was measured for a series of advanced imaging metrology (AIM) targets having a region of interest (ROI) ranging from 2.8 - 19.5 μm and mark pitch ranging from 1.9 - 4.5 μm. The interlayer dielectric (ILD) film separating the layers of relevance was systematically varied in both thickness (0 - 5 μm) and refractive index (1.60 - 2.54). A reasonable correlation is observed between the measured precision values and the Rayleigh optical thickness, indicating that the optical clarity of ILD films contributes significantly to the minimum achievable overlay metrology precision.

It is evident that DRAM ground rule continues to shrink down to 90nm and beyond, overlay performance has become more and more critical and important. Wafer edge shows different behavior from center by processes, e.g. a tremendous misalignment at wafer edge makes yield loss . When a conventional linear model is used for alignment correction, higher uncorrectable overlay residuals mostly happen at wafer edge. Therefore, it's obviously necessary to introduce an innovational alignment correction methdology to reduce unwanted wafer edge effect. In this study, we demonstrate the achievement of moderating poor overlay in wafer edge area by a novel zone-dependent alignment strategy, the so-called "Zone Alignment (ZA)". The main difference between the conventional linear model and zone alignment strategy is that the latter compensates an improper averaging effect from first modeling through weighting all surrounding marks with a nonlinear model. In addition, the effects of mark quantity and sampling distribution from "Zone Alignment" are also introduced in this paper. The results of this study indicate that ZA can reduce uncorrectable overlay residual and improve wafer-to-wafer variation significantly. Furthermore, obvious yield improvement is verified by ZA strategy. In conclusion, Zone alignment is the noteworthy strategy for overlay improvement. Moreover, suitable alignment map and mark numbers should be taken into consideration carefully when ZA is applied for further technology node.

Traditionally OPC models are calibrated to match CD measurements from selected test pattern locations. This demand for massive CD data drives advances in metrology. Considerable progress has recently been achieved in complimenting this CD data with SEM contours. Here we propose solutions to some challenges that emerge in calibrating OPC models from the experimental contours. We discuss and state the minimization objective as a measure of the distance between simulation and experimental contours. The main challenge is to correctly process inevitable gaps, discontinuities and roughness of the SEM contours. We discuss standardizing the data interchange formats and procedures between OPC and metrology vendors.

Optical Proximity Correction (OPC) has become an integral and critical part of process development for advanced technologies with challenging k₁ requirements. OPC solutions in turn require stable, predictive models to be built that can project the behavior of all structures. These structures must comprehend all geometries that can occur in the layout in order to define the optimal corrections by feature, and thus enable a manufacturing process with acceptable margin. The model is built upon two main component blocks. First, is knowledge of the process conditions which includes the optical parameters (e.g. illumination source, wavelength, lens characteristics, etc) as well as mask definition, resist parameters and process film stack information. Second, is the empirical critical dimension (CD) data collected using this process on specific test features the results of which are used to fit and validate the model and to project resist contours for all allowable feature layouts. The quality of the model therefore is highly dependent on the integrity of the process data collected for this purpose. Since the test pattern suite generally extends to below the resolution limit that the process can support with adequate latitude, the CD measurements collected can often be quite noisy with marginal signal-to-noise ratios. In order for the model to be reliable and a best representation of the process behavior, it is necessary to scrutinize empirical data to ensure that it is not dominated by measurement noise or flyer/outlier points. The primary approach for generating a clean, smooth and dependable empirical data set should be a replicated measurement sampling that can help to statistically reduce measurement noise by averaging. However, it can often be impractical to collect the amount of data needed to ensure a clean data set by this method. An alternate approach is studied in this paper to further smooth the measured data by means of curve fitting to identify remaining questionable measurement points for engineering scrutiny since they may run the risk of incorrectly skewing the model. In addition to purely statistical data curve fitting, another concept also merits investigation, that of using first principle, simulation-based characteristic coherence curves to fit the measured data.

The volume of measurements and the complexity of metrology recipes in state-of-the-art semiconductor manufacturing have made the conventional manual process of creating the recipes increasingly problematic. To address these challenges, we implemented a system for automatically creating production metrology recipes. We present results from the use of this system for CD-SEM and overlay tools in a high-volume manufacturing environment and show that, in addition to the benefits of reduced engineering time and improved tool utilization, recipes produced by the automated system are in many respects more robust than the equivalent manually created recipes.

Sub-resolution assistance feature (SRAF) has become one of popular resolution enhancement technique because it is the most easily applicable technique that can be adopted for sub-65 nm node technology. The SRAF can be realized, for example, by locating lines having width below resolution limit around isolated feature. With the SRAF, intensity profile of the isolated feature will be modified to dense-like one and, as a result, focus response of the isolated feature can be improved up to dense feature level. Previous works on SRAF have focused mainly on the critical dimension (CD) margin window. However, CD margin window is not sufficient to evaluate optimum SRAF configuration because process margin degradation due to irregular pattern profile such as line edge roughness (LER) would become more prominent as technology node goes beyond sub-65nm node. Therefore, appropriate methodology to optimize SRAF configuration both for CD margin window and pattern profile is indispensable for those applications. In this paper, we focus on the impact of SRAF configuration to pattern profile as well as CD margin window. The SRAF configuration was adjusted by varying assistance feature to main feature distance and pitch of the assistance features at mask level. Pattern profile was investigated by measuring LER with varying assistance feature parameters quantitatively. From the results, we prove the impact of SRAF configuration both on pattern profile and CD margin window. We also show that the experimental data can easily be predicted by calibrating aerial image simulation results to measured LER. As a conclusion, we suggest methodology to set up optimum SRAF configuration with regard to both CD margin window and pattern profile.

A new methodology to predict changes in device performances due to systematic lithography and etch effects is described in this paper. Our methodology consists on Automatic Edge-Contour-Extraction (ECE) on Poly Over Active Layer, taking along the manufacturing variability. In general, the AMAT SEM (Scanning Electron Microscopy) ECE algorithm is based on CAD (GDS) to SEM pattern recognition, followed by CD based 2D edge extraction. Device modeling (using SPICE simulation) is used, to predict the nominal values as well as the device performances variability of the transistors drive current (Ion) and leakage current (Ioff). We used our method to compare a classical (simple rectangular) transistors and "U-Shape AA" transistors, both manufactured using Tower TS013LL (0.13um Low-Leakage) Platform. It was found, as predicted, that U-shape transistors have larger W distribution. However, "U-shape" also showed much tighter L distribution and the overall Ion spread is lower comparing to classical transistors. Also, U-Shape transistors found to have lower Lstdev (gate length distribution of each individual transistor). We also used the ECE methodology, to compare transistors of single side dog-bone to double-side dog-bone. Based on our work, we can predict that single-side dog-bone transistors, will have higher and larger Ioff distributions, and the overall Ioff speared along the wafer, will go up to a factor of x2.5.

There has been a substantial increase in the research and development of optical metrology techniques as applied to linewidth and overlay metrology for semiconductor manufacturing. Much of this activity has been in advancing scatterometry applications for metrology. In recent years we have been developing a related technique known as scatterfield optical microscopy, which combines elements of scatterometry and bright field imaging. In this paper we present the application of this technique to optical system alignment, calibration, and characterization for the purpose of accurate normalization of optical data, which can be compared with optical simulations involving only absolute measurement parameters. We show a series of experimental data from lines prepared using a focus exposure matrix on silicon and make comparisons between the experimental and theoretical results. The data show agreement on the nanometer scale using parametric simulation libraries and no "tunable" parameters.

We review early challenges and opportunities for optical CD metrology (OCD) arising from the potential insertion of double patterning technology (DPT) processes for critical layer semiconductor production. Due to the immaturity of these new processes, simulations are crucial for mapping performance trends and identifying potential metrology gaps. With an analysis methodology similar in spirit to the recent NIST OCD extendability study1, but with aperture and noise models pertinent to current or projected production metrology systems, we use advanced simulation tools to forecast OCD precision performance of key structural parameters (eg., CD, sidewall angle) at litho (ADI) and etch (ACI) steps for a variety of mainstream optical measurement schemes, such as spectroscopic or angle-resolved, to identify strengths and weaknesses of OCD metrology for patterning process control at 32 and 22nm technology nodes. Test case geometries and materials for the simulated periodic metrology targets are derived from published DPT process flows, with ITRS-style scaling rules, as well as rather standard scanner qualification use cases. Consistent with the NIST study, we find encouraging evidence of OCD extendability through 22nm node dense geometries, a surprising and perhaps unexpected result, given the near-absence of published results for the inverse optical scattering problem for periodic structures in the deep sub-wavelength regime.

A review of selected current and new Maxwell equation solve algorithms used in critical dimension metrology is presented. We show that the standard RCWA can have serious issues under certain conditions, even in some typical scatterometry applications. We present some results showing that some of the newer algorithms we developed can significantly outperform the RCWA. The strengths and weakness of algorithms are illustrated.

Spectroscopic Mueller polarimetry may provide a useful alternative to standard spectroscopic ellipsometry (SE) for the dimensional characterization of periodic structures, as it provides 16 quantities instead of 2 for SE. We present a detailed experimental comparison of the results provided by conventional scatterometry (0.7 - 5 eV) spectral range), Mueller polarimetry in the visible (450 - 825 nm), electron microscopy (top CD-SEM and cross section) and state-of-the-art CDAFM (Veeco X3D). This last instrument was considered as the best reference currently available. The samples were 1D gratings etched in bulk Si, with 150 and 250 nm nominal CDs and several pitches for each CD. SE spectra were taken at zero azimuthal angles (i.e. with the grooves perpendicular to the incidence plane), as it is usually done with standard scatterometers, while Mueller spectra were measured at all azimuths in steps of 5°, allowing significant consistency tests by comparing the results of the corresponding fits. Both techniques provided CD values in agreement with AFM and CD-SEM data to within 5 nm, comparable to the AFM precision. Grating thickness and sidewall angle (SWA) were best determined by Mueller polarimetry at 90° azimuth, while in the usual zero azimuth configuration, SWA was typically underestimated by several degrees.

CD-SEMs fleet matching is a widely discussed subject and various approaches and procedures to determine it were described in the literature [1,2,4-6]. The different approaches for matching are all based on statistical treatment of CD measurements that are performed on dedicated test structures. The test structures are a limited finite set of features, thus the matching results should be treated as valid only for the specific defined set of test features. The credibility of the matching should be in question for different layers and specifically production layers. Since matching is crucial for reliable process monitoring by a fleet of CD-SEMs, the current matching approaches must be extended so that the matching will be only tool dependent and reproducible on all layers regardless their specific material or topographic characteristics. In our previous work [1] the new approach named "Physical Matching" was introduced and a new matching procedure based on the direct estimation of tool physical parameters was described. This approach extends the conventional matching methods to enable significant improvement of the matching between CD-SEM tools in production environment. In this work we present results of applying the physical matching method in FAB environment by using the physical parameters of the brightness and SNR, extend it to noise frequency domain characteristics monitoring, and enhanced collection uniformity. Improving the collection uniformity is also demonstrated and proved to be a significant factor. The advantage of the physical matching with noise spectra analysis approach for a case study is demonstrated. This method will enable detection of specific reasons for mismatching between the tools, based on analysis of specific frequencies that are resulted from known mechanical/electrical noise. The proposed procedure allows tool problems fixing before CD measurements are affected. In order to get a reliable visualization of the difference between two systems, new automatic and manual tool finger print methods were developed. The application of the proposed approach to vendor to vendor matching problem is considered.

Minute variations in advanced VLSI manufacturing processes are well known to significantly impact device performance and die yield. These variations drive the need for increased measurement sampling with a minimal impact on Fab productivity. Traditional discrete measurements such as CDSEM or OCD, provide, statistical information for process control and monitoring. Typically these measurements require a relatively long time and cover only a fraction of the wafer area. Across array across wafer variation mapping ( AWV) suggests a new approach for high throughput, full wafer process variation monitoring, using a DUV bright-field inspection tool. With this technique we present a full wafer scanning, visualizing the variation trends within a single die and across the wafer. The underlying principle of the AWV inspection method is to measure variations in the reflected light from periodic structures, under optimized illumination and collection conditions. Structural changes in the periodic array induce variations in the reflected light. This information is collected and analyzed in real time. In this paper we present AWV concept, measurements and simulation results. Experiments were performed using a DUV bright-field inspection tool (UVision^(TM), Applied Materials) on a memory short loop experiment (SLE), Focus Exposure Matrix (FEM) and normal wafers. AWV and CDSEM results are presented to reflect CD variations within a memory array and across wafers.

The linewidth measurement capability of the model-based library (MBL) matching technique was evaluated experimentally. This technique estimates the dimensions and shape of a target pattern by comparing a measured SEM image profile to a library of simulated line scans. The simulation model uses a non-linear least squares method to estimate pattern geometry parameters. To examine the application of MBL matching in an advanced lithography process, a focus-exposure matrix wafer was prepared with a leading-edge immersion lithography tool. The evaluation used 36 sites with target structures having various linewidths from 45 to 200 nm. The measurement accuracy was evaluated by using an atomic force microscope (AFM) as a reference measurement system. The results of a first trial indicated that two or more solutions could exist in the parameter space in MBL matching. To solve this problem, we obtained a rough estimation of the scale parameter in SEM imaging, based on experimental results, in order to add a constraint in the matching process. As a result, the sensitivity to sidewall variation in MBL matching was improved, and the measurement bias was reduced from 22.1 to 16 nm. These results indicate the possibility of improving the CD measurement capability by applying this tool parameter appropriately.

CAD based recipe creation paves the way for complete recipe automation and minimizes the need for human intervention. A high volume production environment presents its own unique challenges for automatic CAD based metrology. In our work we describe the approach of automatic offline CD-SEM recipe creation for production using the Applied Materials OPC Check application. In addition, the study includes a comprehensive analysis of success rates for recipe creation, pattern recognition and measurement. The stability of automatically created recipes was evaluated against process variations for a number of test structures which are typically used for production control. Data was collected for various layers on multiple lots and the performance was compared to that of recipes created directly on the tool. All offline recipes for production were generated waferless from design data with success rates of 100%. They showed pattern recognition success rates and measurement success rates at the same level or better than the rates typically reached by recipes created directly on the tool by an experienced CD-SEM engineer.

CD-SEM is the metrology tool of choice for patterning process development and production process control. We can make these applications more efficient by extracting more information from each CD-SEM image. This enables direct monitors of key process parameters, such as lithography dose and focus, or predicting the outcome of processing, such as etched dimensions or electrical parameters. Automating CD-SEM recipes at the early stages of process development can accelerate technology characterization, segmentation of variance and process improvements. This leverages the engineering effort, reduces development costs and helps to manage the risks inherent in new technology. Automating CD-SEM for manufacturing enables efficient operations. Novel SEM Alarm Time Indicator (SATI) makes this task manageable. SATI pulls together data mining, trend charting of the key recipe and Operations (OPS) indicators, Pareto of OPS losses and inputs for root cause analysis. This approach proved natural to our FAB personnel. After minimal initial training, we applied new methods in 65nm FLASH manufacture. This resulted in significant lasting improvements of CD-SEM recipe robustness, portability and automation, increased CD-SEM capacity and MT productivity.

IONiSE is a Monte Carlo simulation which describes the interactions of 5-50 keV energy He+ ions with solids, and predicts the production of ion induced secondary electron (iSE) emission. Its use to determine the most probable implant depth, the maximum ion range, and the effect of straggle are presented. IONiSE has been used to numerically fit literature tabulations of iSE generation from five elements so as to derive excitation energy and mean free path parameters. By employing those parameters in IONiSE the topographic yield variation for iSE as a function of energy and the atomic number of the target has been predicted, and estimates of the individual secondary electron contributions from the incident and backscattered ions have been made. These simulations help to create a foundation for the application and the interpretation of iSE images for metrology.

A new technology was developed to detect Critical Dimension (CD) variations in a Fourier space. The detection principle is a form birefringence of the wafer. Utilizing this principle, CD and Pattern Edge Roughness (PER) variations are detected as a polarization fluctuation and converted into light intensity. We have achieved high resolution and high sensitivity by combining a form birefringence with a novel optical system. This system detects the light intensity in a Fourier space with a high NA objective, enabling the detection of various lights with different incident angles and polarization states at a time. We have confirmed through simulations that this system has high sensitivity toward CD variations. Furthermore, in partnership with Toshiba Corporation, and through the evaluation of wafers fabricated at Toshiba, we conclude that the light intensity detected by the new system strongly correlates with CD values, and that the new system is capable of detecting CD variations in sufficient sensitivity.

The damage mechanisms that take place when a reticle is subjected to electrical stress by exposure to an electric field have been investigated by applying voltage directly to the structures in a special test reticle. Surface current was recorded at all levels of stress from 1V to 100V. The current/voltage characteristic was polarity dependent and exhibited increasing non-linearity as the feature spacing was reduced. Atomic Force Microscopy showed that the electrical stress caused EFM (Electric Field induced Migration of chrome), matching the damage seen in reticles stressed through induction by an external electric field. No ESD events were recorded, confirming that EFM is independent of ESD and that it occurs with lower electrical stress. The threshold for EFM was found to be five times lower than the previous estimate, starting at 1V with 1µm spacing. Damage caused by EFM was shown to be continuous, cumulative and the rate of CD degradation was measured to be from 3 to 6 nm per second.

Critical dimension small angle X-ray scattering (CD-SAXS) is a measurement platform that is capable of measuring the average cross section and sidewall roughness in patterns ranging from (10 to 500) nm in pitch with sub-nm precision. These capabilities are obtained by measuring and modeling the scattering intensities of a collimated X-ray beam with sub-nanometer wavelength from a periodic pattern, such as those found in optical scatterometry targets. In this work, we evaluated the capability a synchrotron-based CD-SAXS measurements to characterize linewidth roughness (LWR) by measuring periodic line/space patterns fabricated with extreme ultraviolet (EUV) lithography with sub-50 nm linewidths and designed with programmed roughness amplitude and frequency. For these patterns, CD-SAXS can provide high precision data on cross-section dimensions, including sidewall angle, line height, line width, and pitch, as well as the LWR amplitude. We also discuss the status of ongoing efforts to compare quantitatively the CD-SAXS data with topdown critical dimension scanning electron microscopy (CD-SEM) measurements.

Fluctuations in the line edge of lithographic features, termed line edge roughness (LER) always exist. At 32 nm line width (and below), LER can be a significant fraction of the feature dimensions. LER can be simply detected by AFM or SEM techniques, however, fast and nondestructive optical techniques should be developed in order to enable effective process control. Optical scatterometry is preferable over other existing measurement techniques, due to the relatively simple implementation in production and lower photoresist damage. In this article we show simulations of LER by 3-dimensional Rigorous Coupled Wave Theory (RCWT) calculations. The prediction of tool capabilities was done using simulations. The outcome of these simulations results where analyzed and used for the basic design of photoresist structures. The conclusions from sensitivity and correlation analysis of the simulation data were verified against measured scatterometry data. Well-defined features with controlled LER, in the range of 2.5 to 15nm, were fabricated by e-beam direct write technique (IMEC, Belgium). The photoresist features we created were a large matrix of different scatterometry targets with varying parameters of CD, Period, LER level, and LER frequency. These features were characterized by electron microscopy and AFM in order to verify the LER values and a NovaScan 3090 system and NovaMARS modeling software were used for the Scatterometry characterization. To achieve better sensitivity to the lower roughness dimensions, we used an option of Effective Medium Approximation (EMA) modeling for spectra analysis. Based on this reference data and the scatterometry measurements we have developed a novel scatterometry method that is sensitive to very low level of LER. This method is based on design of a special test structure which can show better sensitivities than the basic noise levels of the tool. The basic idea in this design is the calibration of the scatterometry measurement on a series of sites with LER steps. It will be shown that LER changes of about 1 nm can be detected based on these designed test structures. This is well below the normal capabilities of current optical tools.

The necessity for and validity of the bias-free line-edge roughness (LER) evaluation are examined. In a typical case, the LER obtained by the conventional method is found to contain 10% or more bias caused by noise. That is, the biasfree LER evaluation is needed to achieve absolute measurements. The bias-free method is also shown to be necessary in relative LER measurements. Moreover, the impact of the smoothing (i.e., averaging the signal intensity in x-direction) process on the LER obtained from scanning electron microscope (SEM) image was evaluated quantitatively by using the bias-free LER evaluation algorithm. We found that the smoothing broadens the SEM signal profile and causes a change in the LER value. Under practical conditions, his smoothing-induced LER change was 0.4 nm in the sample used for this study. This can be a large error when measuring a small LER. Finally, a procedure for optimizing the smoothing number used for applying the bias-free LER application was proposed by considering the validity limit of the application and smoothing-induced LER change.

The importance of LWR/LER has been wildly treated as an important process parameter to obtain good device performance especially entering 45nm era. The accurate estimation of the metrics is even more important as semiconductor fabrication keeps downsizing. In regular LWR/LER measurement by CDSEM, measurement noise is inevitable and causes bias from true roughness. One early bias-reduction roughness measurement method is by J. Villarrubia and B. Bunday [Proc. SPIE 5752, 480 (2005)] in which multiple images with different frame number are collected and averaged to reduce the noise level after edge position aligned (that is only possible in low noise level). Another proposal by A. Yamaguchi, etc. [Proc. SPIE 6152, 61522D (2006)] is curve fitting with a fixed semi-experimental formula to a measurement curve as a function of the number of scan line of summing. Both methods require complicated image/data collection and calculation method to obtain true roughness. We propose a practical and bias-free roughness measurement method here that is improved version of the two methods, and evaluate noise with multiple measurements at the same line which has adequate scan line summing number so that line edge alignment is doable no matter the noise level. We have verified that the noise is close to Gaussian distribution and the true roughness is estimable for different scan line summing number. The obtained true roughness is also verified by TEM picture. The advantage of this method is practical to commercial CDSEM application in combine with simple offline calculation.

The effects of Line Width Roughness (LWR) on transistor performance are one of the hottest issues in semiconductor industry. However, in most related studies, LWR is considered as the fluctuations of gate lengths and not of resist lines. In this paper, we examine the direct effects of one of the spatial resist LWR parameters, the fractal dimension, on transistor off current deviations for various correlation lengths and gate widths. The aim is to exploit the fractality of LWR in order to link the gap between the LWR of long resist lines and the gate length roughness that affects transistor performance. The used methodology is based on the simulation of both resist lines and transistor operation. The results of the two step methodology are presented for both narrow and wide gates. For the first, it is found that for all correlation lengths, higher fractal dimension (smaller roughness exponent) of the resist line leads to off state currents closer to the nominal value. For wide gates, an interesting differentiation is found at the dependence of the standard deviation from the fractal dimension as correlation length decreases. For sufficiently low correlation length, the behavior is reversed and the low fractal dimension are more beneficial that the higher ones. An explanation of that reverse is provided by means of the dependence of the CD variation on gate width for various fractal dimensions. Finally, the implications of these findings on the dependencies of the yield of transistors on fractal dimension and correlation length are also discussed.

Specular X-ray reflectivity (SXR) can be used, in the limit of the effective medium approximation (EMA), as a highresolution shape metrology for periodic and irregular patterns on a smooth substrate. The EMA defines as that the density of the solid pattern and the space separating the patterns are averaged together. In this limit the density profile as a function of pattern height obtained by SXR can be used to extract quantitative information on the cross-sectional pattern profile. Here we explore the limitations of SXR as a pattern shape metrology by studying diblock copolymer films with irregularly shaped bicontinuous terraces on quantized flat layers alternating with two polymer blocks. We conclude that SXR can be extended to irregular shaped patterns encountered in current electronic devices as long as average lateral length scale is smaller than coherence length of X-ray source. The detailed cross-sectional profiles of irregular patterns are discussed along with atomic force microscope results.

This paper presents a new highly sensitive scatterometry based Probe-Pattern Grating (PPG) focus monitor and its printing assessment on an advanced exposure tool. The high sensitivity is achieved by placing transparent lines spaced at the strong focus spillover distance from the centerline of a 90 degree phase-shifted probe line that functions as an interferometer detector. The monitor translates the focus error into the probe line trench depth, which can be measured by scatterometry techniques. The sensitivity of the defocus measurement through scatterometry calibration is around 1.1nm defocus / nm trench depth. This result indicates that the PPG focus monitor from a single wafer focus setting can detect the defocus distance to well under 0.05 Rayleigh Units.

In lithography and etch processing, the control inputs (dose or gas flow, etc) use the critical dimension measurements from CDSEM as feedback and/or feed forward parameters. Thus the image quality of the metrology tools is critical for controlling litho and etches processes. With wafer size increasing while CD and features shrinking, even tighter controls on CD are required. It has been shown in literature that during 24 hour period, the beam alignment can drift severely enough to cause a shift of over 10 nm in the measured CD. Though auto focus tuning is provided on some CDSEMs, our tests show that, depending on the focus algorithm used, the insitu autofocus may shift from the best focus. In practice, the tuning of CDSEM settings largely depends on the operator's "eyeball" judgments, thus the quality of the SEM images is dependent on the judgment of the operators. In this paper, we propose an objective and quantitative image quality monitor for focus monitor based on image processing and optimization. For focus monitor and optimization, a series of through-focus images are taken for a CDSEM tool. By processing the images using image processing toolbox in Matlab, an IFQ (image focus quality) score, used to quantify the image focus quality, is assigned to each image. The fitting of this data to a predefined polynomial can be used to determine best focus. The algorithm is robust and fast, and has been integrated into the existing manufacturing infrastructure for tool performance tracking and monitoring. The paper is organized as following: In the introduction, some background information on CDSEM, as well as existing and alternative image quality monitoring methods are reviewed. In the second part, we introduce the methodology and steps for the new focus monitor. The third part covers the experiments for CDSEM parameter optimization, robustness tests and validation. The next part explains the implementation of the focus monitor in manufacturing environment. In summary, the proposed method for focus monitor is fast, robust and manufacturability.

Crystal growth and haze formation on photomasks become serious problems in UV lithography. As the wavelength becomes shorter, photons carry more energy, so the chances of having a photochemical reaction become much higher. Pellicle, adhesive, residue from cleaning or resist strip process, and any contaminant in air can react with UV to form unwanted crystals and a haze layer on reticles. These will reduce the light transmission during exposure process. Thus, frequent mask inspection and periodic mask cleaning are needed to overcome these problems. However, these will in turn increase manufacturing cost and reduce mask life. Thus, a proper mask inspection tool is required to provide early warning of haze formation. In this work, we devised a new ellipsometric technique to investigate the inner surface of mask without removing pellicle. Ellipsometry is known to have mono-layer sensitivity and it can be used to measure any film or partial film formed on non-patterned spot in early stage of growth. However, when a pellicle covers the surface of mask, the ellipsometric data reflected from surface are extremely distorted due to the non-normal transmission through the pellicle. Thus, data analysis becomes extremely difficult without knowing the optical properties of pellicles. In order to solve this problem we developed compensation technique in which two blank pellicles are situated in the optical path in a way to compensate the polarization changes caused by the pellicle on mask. With this method, the conventional ellipsometry spectra of {Δ, Ψ} are deduced.

The development of a novel compact EUV spectrophotometer will be presented. The device is capable of measuring reflectance and transmittance spectra of medium scale EUV-optics primary in the spectral range from 12nm to 21nm. Based on a new polychromatic measurement principle, the system uses the direct irradiation of a table-top EUV-source for illuminating the sample and a broad-band spectrograph for detecting the probe and reference beam. Samples can be investigated under different angles of incidence and in respect of lateral dependencies. Typical results of reflectivity investigations of Mo/Si-mirrors and transmitting foils will be shown and compared with reference measurements of certified institutes and calculations.

Due to the feature size shrinking, the application of 193nm-ArF scanner systems with high numerical aperture (NA) and the use of resolution enhancement technologies (RET) have been essential for obtaining the desired pattern accuracy on a wafer. Thus the complexity and volume of data required for masks have been rapidly increasing. Moreover, the complexity of mask pattern makes mask inspection increasingly more difficult. The most annoying problem relating to the sensitivity of inspection system is the encountering of false signals arising from nuisance defects. Setting up thresholds in the defect detection algorithm is a difficult task between high sensitivity and less false defect detection. In addition, the effect of variations in defect printability which is strongly dependent on defect types and position must be considered in order to correctly evaluate mask defect inspection procedures. In order to overcome the problems we have previously proposed new algorithm for die-to-wafer-like image (D-to-WI) in real time. This inspection method compares the die, i.e. the wafer image calculated from CAD data, with the wafer-like image calculated from the mask images detected by the mask inspection system. This paper described optimum mask inspection optics for the D-to-WI mask inspection. We verify the optimum mask inspection optics with numerical simulation for various NA and partial coherence of illumination (σ) in the mask inspection optics. The simulated result shows that the optimum mask inspection optics has NA 0.9 and σ=1 for ArF-6%-PSM (Phase Shift Mask) 65/65 nm Line/Space pattern of 193nm-ArF scanner with NA 0.92. In this case the difference of the critical dimensions (CDs) found by D-to-WI and rigorous simulation results from CAD data was less than 1.5nm.

As PSM (Phase Shift Mask) process moves toward 45nm and 32nm node, phase control is becoming more important than ever. Both attenuated and alternating PSM need precise control of phase as a function of both pitch and target sizes. However conventional interferometer-based phase shift measurements are limited to large CD targets and requires custom designed target in order to function properly, which limits clear understanding and control of small target PSM features. New type of Phase metrology tool created by Zeiss, in collaboration with Intel has been introduced and Intel's 45nm node PSM targets have been measured. In this paper we present test results from AAPSM/EAPSM targets with space CDs down to 45nm a wafer-level. Smallest pitch was 300nm print pitch, 150nm CD at mask (75nm pitch at wafer). In addition to this, phase and transmission matching between conventional phase metrology tool and new tool has been investigated and shown.

STARlight2+^TM (SL2+) is a new high-resolution contamination inspection system based upon the KLA-Tencor TerascanHR platform. Building upon the proven technology of STARlight^TM (SL2), SL2+ uses transmitted and reflected images to detect potentially yield-limiting contamination defects on photomasks for wafer fabs and mask shops. It extends the contamination inspection capability to the 32nm logic/45nm Half Pitch (HP) technology nodes using the newly developed 72nm pixel image resolution as well as a significantly improved rendering model in the algorithm. In this paper, we present inspection results on a wide variety of photomasks, spanning the 32nm to 110nm technology nodes, in the recently concluded period of Alpha tests on the SL2+ system. The test results show that the sensitivity and the inspection capability of the new SL2+ system have been greatly improved. Such improvement enables wafer fabs and mask shops to inspect and qualify photomasks for 32nm node development and 45nm node production.

As the design technology node becomes smaller, k1 factor is decreasing below 0.3 and optical proximity correction (OPC) divergence is increasing. The gate critical dimension (CD) control and systematic defect inspection is becoming critical to improving circuit yield. For more accurate OPC verification and systematic defect inspection, design based metrology become increasingly important, because accuracy of simulation based OPC model verification has its limitation. In this paper, we used NGR-2100 as a design based metrology tool to confirm the accuracy of OPC modeling and process window qualification. NGR-2100 uses high energy wide-beam for high speed secondary electron sampling and large field of view. It can measure full chip CD distribution and more accurate process window compared to optical inspection tool. Because of using high energy beam, conducting layer like carbon film should be coated on photo resist patterned sample wafer to prevent local electron charging. However, coated carbon may increase CD variation. By using atomic layer deposition-type TiN layer instead of carbon, CD variation could be reduced.

We proposed a novel method (DBB: Designed Based Binning) by using design and defect inspection information to detect marginal design features. This method was used to identify a pattern failure problem (hammer head) which occurred during production early ramp (65 nm device). The traditional approach could not detect this hammerhead problem due to the intermittent nature and low defect count. This problem was identified by DBB methodology which showed problem root cause as a combination of lithography process conditions drift and marginal OPC issues. This use case proved that by using DBB to identify weak pattern features, it provides a common platform for designer, OPC and process engineer to communicate and identify design related problems faster. This method has helped integration engineer shorten process development time, supported product engineer to ramp new product faster and enabled defect engineer to detect excursion earlier. Overall, advanced manufacturing fab will achieve higher yield by adopting this.

Critical dimension small angle X-ray scattering (CD-SAXS) is a metrology platform capable of measuring the average cross section and line width roughness (LWR) with a sub-nm precision in test patterns with line widths ranging from 10 to 500 nm. The X-ray diffraction intensities from a collimated X-ray beam of sub-Angstrom wavelength were collected and analyzed to determine line width, pitch, sidewall angle, LWR, and others structural parameters. The capabilities of lab-scale and synchrotron-based CD-SAXS tools for LWR characterization were tested by measuring a set of identical patterns with designed roughness amplitude and frequency. These test patterns were fabricated using EUV lithography with sub-50 nm linewidths. To compensate for the limited photon flux from the lab-based X-ray source, the incident beam of the lab system was collimated to a less extent than the synchrotron beam-based tool. Consequently, additional desmearing is needed to extract information from data obtained from lab-based equipment. We report the weighted nonlinear least-squares algorithm developed for this purpose, in addiiton to a comparison between the results obtained from our lab system and the synchrotron beam-based tool.

Model-based optical proximity correction (OPC) is an indispensable production tool enabling successful extension of photolithography down to sub-80nm regime. Commercial OPC software has established clear procedures to produce accurate OPC models at best focus condition. However, OPC models calibrated at best focus condition sometimes fail to prevent catastrophic circuit failure due to patterning short & open caused by accidental shifts of dose/ focus within the corners of allowed processes window. A novel model-based OPC verification methodology is presented in this work, which precisely pinpoints post OPC photolithography failures in VLSI circuits through the entire lithographic process window. By application of a critical photolithography process window model in OPC verification software, we successfully uncovered all weak points of a design prior tape out, eliminating high risk of circuits open & shorts at the extreme corner of the lithographic process window in any complex circuit layout environment. The process window-related information is usually not taken into consideration when running OPC verification procedures with models calibrated at nominal process condition. Intensive review of the critical dimension (CD) and top-view SEM micrographs from the weak points indicate matching between post OPC simulation and measurements. Using a single highly accurate process window resist model provides a reliable OPC verification methodology when used in a field- or grid-based simulation engine ensuring manufacturability within the largest possible process window for any modern critical design.

The amplitude setpoint affects the critical dimension measurement with CD-AFM. The setpoint amplitude is the amplitude of the resonant oscillation of the AFM tip maintained by the feedback loop as it scans the surface. The Setpoint therefore decides the tip-surface distance, and the tip-surface interaction force as well. Normally, the tip moves an unknown distance away from the sample surface. Such a tip-sample distance on the top and bottom surface is cancelled out in height measurement. In width measurement, however, the tip-sample distance on the left and right sidewall will add up to produce a bias in the measured CD values. The bias will appear in the opposite way and by the same amount in line and trench measurement. We conducted the experiments to see the effect, and found out there exists the dependence of the measured linewidths on the setpoint in the consistent behavior as our hand-waving predicts. The effect may be a significant uncertainty source in the CD-AFM metrology.

This paper reports on new developments of advanced CD AFM probes after the prior introduction of "trident probes" in SPIE Advanced Lithography 2007 [1]. Trident probes, having sharpened extensions in the tip apex region, make possible bottom CD measurements within a few nanometers of the feature bottom corner; an area where other CD probes have difficulties due to tip shape limitations. Moreover, new metrology applications of trident probes have been developed for novel devices such as FinFET and vertical read/write hard disk heads. For ever smaller technology nodes, new probes evolved from the design of the trident probe. For example, the number of sharpened tip flares was reduced from three (trident) to two (bi-pod) to prevent possible interference of the third leg in the slow scan direction, as shown in Figure 3. Maintaining tip lateral stiffness as the tip size shrinks to less than 30 nm is vital for successful scanning. Consequently, a significant recent improvement is the change of probe shank cross-sectional geometry in order to maintain tip vertical aspect ratio of 1:5 (and lateral stiffness > 1 N/m). Finally, modifications of probe substrate are proposed and evaluated for current and new CD AFM systems. Hydrophobic, self-assembled monolayer (SAM) coatings were applied on CD probes to reduced tip "pull-away" distance1 during CD AFM scanning. Test results show that the pull away distance can be reduced more than 5 times on average (in some cases, by a factor of 15). Consequently, use of hydrophobic SAM coatings on CD probes mitigates pull-away distance thus allowing narrow trench CD measurements. We discuss limitations of prior CD AFM probes and design considerations of new CD probes. The characterization of first prototypes and evaluation of scan performance are presented in this work.

Strong candidate lithography for the mass production of devices at the 32nm technology node and beyond is extreme ultra violet lithography (EUVL). The mask used in EUVL is a complex set of layers. The material composition and thickness of each layer should be considered explicitly in an attempt to model the deposited energy in the resist film during fabrication of mask features using electron-beam lithography. Targeting to sub-32nm technology even with the reduction by 4 of the mask features on the wafer level, lithography should consider accurate fabrication features on the mask level of the order of 50nm. Therefore, detailed simulation of the electron-beam fabrication process, as well as the resist dissolution mechanism and etching is demanding. In this work an attempt is initiated targeting in combining two simulation techniques i.e., the electron-beam simulation, with the stochastic lithography simulation, in a common simulation platform. This way it will be possible to get detailed information of the fine details of the fabricated features, taking into account the multilayer substrate of the mask, and the resist material properties. The e-beam simulation algorithm is presented and used to expose a layout. The calculated energy deposition in the resist level, initially determined considering resist material to be continuous, is used in the discrete representation of the resist. With appropriate threshold in the exposure energy, also acid diffusion could be taken into consideration. Stochastic development of the resist material, delivers line-edge roughness (LER) and critical dimension (CD) on the resist level, in terms of polymer chain architecture.

The model-based library (MBL) matching technique was applied in hardmask linewidth metrology with a criticaldimension scanning electron microscope (CD-SEM). The MBL matching measures the edge positions and shapes of samples by comparing simulated images to measured images. To achieve reliable, stable measurements, two important simulation parameters were determined empirically. One was the beam width, and the other was a material parameter, the residual energy loss rate. This parameter is especially important for measurement of hardmask patterns, which have relatively high SEM image contrast. These simulation parameters were estimated so as to fit to actual SEM images, and then pinned to the estimated values during MBL matching. Hardmask patterns made of Si₃N₄ were measured by MBL matching with the estimated parameters. The accuracy of the measurements was evaluated by one-to-one comparison with atomic force microscope (AFM) results. The pattern profile deduced from only the top-down CD-SEM image with MBL matching agreed well with the AFM profile and a scanning transmission electron microscope (STEM) crosssectional image. The average measurement bias between the MBL matching and AFM results was 1.58 nm for the bottom CD and -0.64 nm for the top CD, with a standard deviation of about 1.3 nm.

CD-SEM measurement of linewidth, while providing good relative results, is not completely accurate. The measurements involve significant bias of the SEM signal at line edges. The bias varies depending on the SEM setup, the materials and profiles of patterns on the wafer, as well as charging. Existing methods of CD-SEM calibration are extremely limited, only being available for specific samples and materials. In this paper, simulations of SEM signal were carried out using advanced Monte Carlo models of electron interactions with samples. The linewidth was simulated for a variety of pattern materials and SEM setups. The corresponding linewidths were extracted. A CD bias was determined for each type of measurement. When a 3D pattern is exactly known in simulation, the SEM signal can be related to the pattern; then the bias can be found for any combination of SEM patterns. This has the potential to greatly improve CDSEM accuracy, toward the goal of absolute linewidth measurements.

SEM microscopy is a primary method for CD measurements of features on sub-micron scale. The process of feature characterization using SEM involves several steps that include image acquisition, image processing, image analysis and data analysis. Each one of these steps carries an error margin that contributes to the overall accuracy of measurements. While performing measurements at the nanoscale resolution the accuracy of the process becomes even more critical for obtaining accurate measurements, and needs to be determined and understood. Using object with known dimensions such as linewidth of an isolated polycrystalline ("poly") Si lines be useful for evaluating accuracy of the characterization process and calibrating SEM instrument. Reference materials for such evaluation are being developed by NIST. To use this approach successfully it is important to understand metrology issues involved in the image characterization process. This work will review the scope of metrology issues involved in the process of linewidth measurement using SEM imaging including image acquisition, image processing and segmentation, as well as data extraction and analysis using image analysis methods. We will review and discuss methods for evaluating accuracy throughout characterization process and obtaining reliable and repeatable measurements. The scope of study includes the use of two dimensional simulation and modeling of SEM line images, methods for grayscale image processing and segmentation, algorithms for obtaining statistically accurate linewidth measurements from the image that can be used for instrument calibration and inter-laboratory studies and are generally applicable for obtaining CD measurements of line features.

In our previous paper*[1], next generation lithography offering improved resolution by use of Hyper-NA and Low-k1, changes in exposure tool focus were seen to influence pattern shape and it was verified that pattern profile variation occurs even when measured CD values are similar. This shows the necessity for process control to include pattern shape information, conventional methods using the CD value alone will be insufficient as process latitudes continue to shrink. In such a situation, to be able to precisely measure the physical dimensions of design features becomes more and more important. In this study, we have investigated improved precision of Process Window (PW) determination by using the MPPC function that allows the pattern profile shape to be quantified. We have also evaluated pattern shape variation by means of Litho-simulation. As a result, it was confirmed that resist loss is the main change in shape that occurs. Therefore, we have focused our attention on resist loss and optimized the MPPC parameters by SEM simulation*[2]. As a consequence, it was possible to precisely detect the resist loss. Using this technique, it was possible to show the possibility for highly precise 3D measurement determination, for use in exposure tool monitoring, by using the MPPC measurement technique.

Multiple Gate Field Effect Transistors (MuGFETs) have been proposed to enable downsizing, when scaling the transistors to the 32nm technology node. The dimension of the gate on the surface of fin determines the effective channel length of the device. So, the characterization of the gate profiles at fin sidewalls becomes extremely critical. It is especially important to quantify the rounded intersection (etch residual) at the intersection of the fin and gate. In this report, we show top down images of a MuGFET taken with critical-dimension scanning electron microscopy (CD-SEM) and the results that were measured and characterized by measuring various portions of the pattern which will impact the MuGFET performance i.e. gate length, fin width. We will introduce a quantified relation between fin length and "its effect on the etch residue at the intersection of fin and gate". Next we discuss our approaches to analyze the variation of the shape of the gate at the fin sidewall.

As advanced semiconductor companies move forward to the 45nm technology node, traditional overlay sampling and linear correction used in dry lithography become less feasible to bring overlay control into the desired budget. New overlay control methodologies need to be established to meet the needs of much tighter overlay budgets in the immersion lithography process. Overlay source of variance (SOV) was first investigated to understand the major contributor of overlay error sources. The SOVis broken down into wafer, field, and random components in order to utilize the SOV information to prioritize overlay improvement decisions. High order wafer level or field level error components are commonly observed as a significant contributor and requires attention to bring the overlay residual into the desired limit. Optimal sample is determined in considering sample plan robustness and throughput impact while increasing sampling becomes a necessity in 45nm technology node.

As the semiconductor industry continues to drive towards high volume production at the 50nm technology node and beyond, there are formidable barriers imposed not only from technical challenges but also from economic challenges related to controlling overlay tightly enough to meet the strict requirements of a increasingly smaller overlay control window. In this paper, the authors will show potential sources overlay error for a 50nm node process and detail a methodology to pinpoint the root cause and an application to help reduce these errors to facilitate the ramp of a new process technology for high volume DRAM/FLASH manufacturing. In short, based on a series of experiments and analysis, the authors have identified high-order wafer-level residual component to be the main contribution of the high residuals with the source attributed to the scanner mix-and-match set. In turn, an overlay control approach using high order correctables generated from the overlay metrology system and fed through the APC system will be able to effectively reduce the mix-and-match high residual errors.

The newly emerging lithographic technologies related to the 32nm node and below will require a step function in the overlay metrology performance, due to the dramatic shrinking of the error budgets. In this work, we present results of an emerging alternative technology for overlay metrology - Differential signal scatterometry overlay (SCO^TM). The technique is based on spectroscopic analysis of polarized light, reflected from a "grating-on-grating" target. Based on theoretical analysis and initial data, this technology, as well as broad band bright field overlay, is a candidate technology that will allow achieving the requirements of the 32nm node and beyond it. We investigate the capability of SCOL^TM to control overlay in a production environment, on complex stacks and process, in the context of advanced DRAM and Flash technologies. We evaluate several metrology mark designs and the effect on the metrology performance, in view of the tight TMU requirements of the 32nm node. The results - achieved on the KLA-Tencor's Archer tool, equipped with both broad band bright field AIM^TM and scatterometry SCOL^TM sensors - indicate the capability of the SCOL^TM technology to satisfy the advanced nodes requirements.

As a design rule shrink down aggressively, various RETs (Resolution Enhancement Technology) have been developed to extend the resolution limits of lithography. Until now, next generation lithography has been focused on EUV technology. But no one can assure when EUV will be implemented. So, we must develop new technology with current immersion tool to catch up with aggressive design rule. One of those is DPT (Double Patterning Technology), however there are also many challenges to overcome such as patterning, overlay, hard mask etch and so on. The most critical issue would be overlay, because it affects CD (Critical dimension) uniformity directly. Therefore, overlay control is very important between 1^st DP layer and 2^nd DP layer. We utilized ArF immersion scanners for this experiment. In this paper, DP process flow, hard mask film dependency, align method dependency, efforts of new align key design and direct align analysis in DP overlay will be reported to understand and get better overlay accuracy than tool specification. It is needed to be verified that how much they take an effect on improving the DP overlay. Continuously we can conclude that most efforts in DPT should be focused on overlay control issue.

Overlay metrology and control have been critical for successful advanced microlithography for many years, and are taking on an even more important role as time goes on. Due to throughput constraints it is necessary to sample only a small subset of overlay metrology marks, and typical sample plans are static over time. Standard production monitoring and control involves measuring sufficient samples to calculate up to 6 linear correctables. As design rules shrink and processing becomes more complex, however, it is necessary to consider higher order modeled terms for control, fault detection, and disposition. This in turn, requires a higher level of sampling. Due to throughput concerns, however, careful consideration is needed to establish a base-line sampling, and higher levels of sampling can be considered on an exception-basis based on automated trigger mechanisms. The goal is improved scanner control and lithographic cost of ownership. This study addresses tools for establishing baseline sampling as well as motivation and initial results for dynamic sampling for application to higher order modeling.

Critical processing factors in the lithography process include overlaying the pattern properly to previous layers and properly exposing the pattern to achieve the desired line width. Proper overlay can only be attained in the lithography process while the desired line width accuracy is achieved by both lithography and etch processes. Since CD is substantially influenced by etch processing, therefore, it is possible to say that overlay is one of the most important processing elements in the lithography process. To achieve the desired overlay accuracy, it is desirable to expose critical layers with the same exposure tool that exposed the previous or target layer. This need to dedicate a particular exposure tool, however, complicates the lot dispatching schedule and, even worse, decreases exposure tool utilization. In order to allow any exposure tool available to print the arriving lot, M&M (Mix and Match) overlay control becomes necessary. By reducing overlay errors in M&M control, lot dispatching scheduling will become more flexible and exposure tool utilization will improve. Since each exposure tool has a unique registration signature, high order errors appear when overlaying multiple layers exposed with different tools. Even with the same exposure tool, if a different illumination is used, a similar error will be seen. A correction scheme to make the signature differences has to be implemented, however manually characterizing each tool's signature per illumination condition is extremely tedious, and is subject human errors. The challenge is to design a system to perform the corrections automatically. In the previous paper(1), we have outlined concepts of the system scheme. The system has subsequently been developed and tested using exposure tools. In this paper test results are shown using automated distortion correction. By analyzing the results, suggestions for further improvements and further developments are shown.

Applications that require overlay measurement between layers separated by absorbing interlayer films (such as α- carbon) pose significant challenges for sub-50nm processes. In this paper scatterometry methods are investigated as an alternative to meet these stringent overlay metrology requirements. In this article, a spectroscopic Diffraction Based Overlay (DBO) measurement technique is used where registration errors are extracted from specially designed diffraction targets. DBO measurements are performed on detailed set of wafers with varying α-carbon (ACL) thicknesses. The correlation in overlay values between wafers with varying ACL thicknesses will be discussed. The total measurement uncertainty (TMU) requirements for these layers are discussed and the DBO TMU results from sub-50nm samples are reviewed.

In immersion lithography process, film stacking architecture will be necessary due to film peeling. However, the architecture will restrict lithographic area within a wafer due to top side EBR accuracy In this paper, we report an effective film stacking architecture that also allows maximum lithographic area. This study used a new bevel rinse system on RF3 for all materials to make suitable film stacking on the top side bevel. This evaluation showed that the new bevel rinse system allows the maximum lithographic area and a clean wafer edge. Patterning defects were improved with suitable film stacking.

Challenges in back-end-of-line process flow are becoming more critical as the 65 and 45 nm process control requirements become more stringent. Unoptimized copper CMP processing contributes to a significant portion of yield losses downstream, if electrical device performance does not address the technology node targets. Adequate metrology is required to meet the challenge of consistent wafer uniformity control in removing the excess copper on 300 mm wafers while preserving the material interface dielectrics at sub-nanometer levels. Dishing of the metal lines, which show the predictive nature of isolated in-die metal line loss, and erosion of the dielectric oxide across multiple oxide-metal line arrays are two key parameters indicative of the planarization process. As feature sizes continue to shrink, micro-dishing and edge-over-erosion become important to characterize and control. For process development, the knowledge of the macro and micro planarity will be increasingly essential to preventing lithography depth of focus issues. In manufacturing, the need for CMP process stability increases as a process excursion could occur at any time. In-line monitoring of macro and micro-level surface topography, dishing, erosion, micro-dishing, and edge-over-erosion parameter values allows fine tuning, optimization, and process control.

Semiconductor manufacturing technology has shifted towards finer design rules, and demands for critical dimension uniformity (CDU) of resist patterns have become greater than ever. One of the methods for improving CDU of resist pattern is to control the temperature of post-exposure bake (PEB). When ArF resist is used, there is a certain relationship between critical dimension (CD) and PEB temperature. By utilizing this relationship, Resist Pattern CDU can be improved through control of within-wafer temperature distribution in the PEB process. We have already applied this method to Resist Pattern CDU improvement and have achieved these results. In this evaluation, we aim at: 1. Clarifying the relationship between the improvement in Resist Pattern CDU through PEB temperature control and the improvement in Etching Pattern CDU. 2. Verifying whether Resist Pattern CDU improvement through PEB temperature control has any effect on the reduction in wiring resistance variation. The evaluation procedure is: 1. Preparation of wafers with base film of doped Poly-Si (D-Poly). 2. Creation of two sets of samples on the base, a set of samples with good Resist Pattern CDU and a set of samples with poor Resist Pattern CDU. 3. Etching of the two sets under the same conditions. 4. Measurements of CD and wiring resistance. We used Optical CD Measurement (OCD) for measurement of resist pattern and etching pattern for the reason that OCD is minimally affected by Line Edge Roughness (LER). As a result, we found that; 1. The improvement in Resist Pattern CDU leads to the improvement in Etching Pattern CDU . 2. The improvement in Resist Pattern CDU has an effect on the reduction in wiring resistance variation. There is a cause-and-effect relationship between wiring resistance variation and transistor characteristics. From this relationship, we expect that the improvement in Resist Pattern CDU through PEB temperature control can contribute to device performance improvement.

The concern over molecular contamination on the surfaces of optics continues to grow. Most recently, this concern has focused on siloxane contamination resulting from hexamethyldisilazane (HMDS) which is commonly used as a wafer treatment to improve photoresist adhesion onto wafers. From this process, HMDS vapor can be found within FABs and process tools where it has been linked to issues related to lens hazing. This type of surface contamination is significantly detrimental to the imaging process and is generally corrected by extensive surface cleaning or even lens replacement. Additionally, this type of repair also requires adjustment of the optical axis, thereby contributing to an extended downtime. HMDS is known to be very sensitive to the presence of water and is therefore believed to degrade in humid airstreams. This research focuses on rationalizing the reaction mechanisms of HMDS in dry and humid airstreams and in the presence of several adsorbent surfaces. It is shown that HMDS hydrolyzes in humid air to trimethylsilanol (TMS) and ammonia (NH₃). Furthermore, it is shown that TMS can dimerize in air, or on specific types of adsorption media, to form hexamethyldisiloxane (HMDSO). Additionally, we report on the relative impact of these reaction mechanisms on the removal of both HMDS and its hydrolysis products (TMS, HMDSO and NH₃).

Recently, stressed silicon wafers have begun being used and it is necessary to measure the strain in the surface film for process control. We developed a stress measurement system with a built in film thickness measurement tool. In pursuing this development we concentrated on the high-throughput and stable results required for semiconductor process control tools. We achieved the desired results by using a collimator in the microscope. Our system can measure the stress in 1 dimension line on a 300 mm wafer in less than 30 seconds. Then we proceed to measure wafer patterns with the same system. We describe this system and the measurement data it provides.

Semiconductor manufacturing technology has shifted towards finer design rules, and demands for critical dimension uniformity (CDU) of resist patterns have become greater than ever. One of the methods for improving Resist Pattern CDU is to control post-exposure bake (PEB) temperature. When ArF resist is used, there is a certain relationship between critical dimension (CD) and PEB temperature. By utilizing this relationship, Resist Pattern CDU can be improved through control of within-wafer temperature distribution in the PEB process. Resist Pattern CDU improvement contributes to Etching Pattern CDU improvement to a certain degree. To further improve Etching Pattern CDU, etcher-specific CD variation needs to be controlled. In this evaluation, 1. We verified whether etcher-specific CD variation can be controlled and consequently Etching Pattern CDU can be further improved by controlling resist patterns through PEB control. 2. Verifying whether Etching Pattern CDU improvement through has any effect on the reduction in wiring resistance variation. The evaluation procedure is as follows.1. Wafers with base film of Doped Poly-Si (D-Poly) were prepared. 2. Resist patterns were created on them. 3. To determine etcher-specific characteristics, the first etching was performed, and after cleaning off the resist and BARC, CD of etched D-Poly was measured. 4. Using the obtained within-wafer CD distribution of the etching patterns, within-wafer temperature distribution in the PEB process was modified. 5. Resist patterns were created again, followed by the second etching and cleaning, which was followed by CD measurement. We used Optical CD Measurement (OCD) for measurement of resist patterns and etching patterns as OCD is minimally affected by Line Edge Roughness (LER). As a result, 1. We confirmed the effect of Resist Pattern CD control through PEB control on the reduction in etcher-specific CD variation and the improvement in Etching Pattern CDU. 2. The improvement in Etching Pattern CDU has an effect on the reduction in wiring resistance variation. The method for Etching Pattern CDU improvement through PEB control reduces within-wafer variation of MOS transistor's gate length. Therefore, with this method, we can expect to observe uniform within-wafer MOS transistor characteristics.

A shrinking design rule has decreased film thickness specifications and is creating challenges as multi-layer structures and new materials are introduced. We have developed a spectroscopic ellipsometer, the RE-5200, which can measure several parameters with spot sizes down to 30 um. The advantages of the RE-5200 include high long-term stability, high accuracy, short measurement time, and low COO. The high precision aspheric mirrors were developed specifically for this system and allow the measurement of very small areas on the device. In addition, the stress measurement function meets some of the latest demands, which are high throughput, high accuracy and pattern independent. This paper presents the optical design and performance of the RE-5200, including measurement results.

We proposed an in-situ method to control the wafer spatial temperature uniformity during thermal cycling of silicon substrate in the lithography sequence. These thermal steps are usually conducted by the placement of the substrate on the heating plate for a given period of time. We have previously proposed an approach for controling the steady-state wafer temperature uniformity in steady-state. In this paper, we extend the approach by considering the dynamic properties of the system. A detailed physical model of the thermal system is first developed by considering energy balances on the system. Next, by monitoring the bake-plate temperature and fitting the data into the model, the temperature of the wafer can be estimated and controlled in real-time. This is useful as production wafers usually do not have temperature sensors embedded on it, these bake-plates are usually calibrated based on test wafers with embedded sensors. However, as processes are subjected to process drifts, disturbances, and wafer warpages, real-time correction of the bake-plate temperatures to achieve uniform wafer temperature is not possible in current baking systems. Any correction is done based on run-to-run control techniques which depends on the sampling frequency of the wafers. Our approach is real-time and can correct for any variations in the desired wafer temperature performance during both transient and steady state. Experimental results demonstrate the feasibility of the approach.

The objective of this work is the creation of predictive models that can forecast the electrical or physical parameters of wafers using data collected from the relevant processing tools. In this way, direct measurements from the wafer can be minimized or eliminated altogether, hence the term "virtual" metrology. Challenges include the selection of the appropriate process step to monitor, the pre-treatment of the raw data, and the deployment of a Virtual Metrology Model (VMM) that can track a manufacturing process as it ages. A key step in any VM application is dimensionality reduction, i.e. ensuring that the proper subset of predictors is included in the model. In this paper, a software tool developed with MATLAB is demonstrated for interactive data prescreening and selection. This is combined with a variety of automated statistical techniques. These include step-wise regression and genetic selection in conjunction with linear modeling such as Principal Component Regression (PCR) and Partial Least Squares (PLS). Modeling results based on industrial datasets are used to demonstrate the effectiveness of these methods.

Recently several DBMs(Design Based Metrologies) are introduced for the wafer verification and feed back to DFM. The major applications of DBM are OPC accuracy feed back, process window qualification and advanced process control feed back. In general, however, DBM brings out huge amount of measurement data and it is necessary to provide special server system for uploading and handling the raw data. And since it also takes much time and labor to analyze the raw data for valuable feed back, it is desirable to connect to EDA tools such as OPC tools or MBV(Model Based Verification) tools for data analysis. If they can communicate with a common language between them, the DBM measurement result can be sent back to OPC or MBV tools for better model calibration. For advanced process control of wafer CDU, DBM measurement results of field CDU can be fed back to scanner for illumination uniformity correction. In this work, we discuss tool integration of DBM with other tools like EDA tools. These tool integrations are targeted for the verification procedure automation and as a result for faster and more exact analysis of measurement data. The procedures of tool integration and automatic data conversion between them will be presented in detail.

The objective of this study was to examine the defect reduction effect of the wafer edge polishing step on the immersion lithography process. The experimental wafers were processed through a typical front end of line device manufacturing process and half of the wafers were processed with the wafer edge polishing just prior to the immersion lithography process. The experimental wafers were then run through two immersion lithography experiments and the defect adders on these wafers were compared and analyzed. The experimental results indicated a strong effect of the edge polishing process on reducing the particle migration from the wafer edge region to the wafer surface during the immersion lithography process.

The traditional approach to semiconductor wafer inspection is based on the use of stand-alone metrology tools, which while highly sensitive, are large, expensive and slow, requiring inspection to be performed off-line and on a lot sampling basis. Due to the long cycle times and sparse sampling, the current wafer inspection approach is not suited to rapid detection of process excursions that affect yield. The semiconductor industry is gradually moving towards deploying integrated metrology tools for real-time "monitoring" of product wafers during the manufacturing process. Integrated metrology aims to provide end-users with rapid feedback of problems during the manufacturing process, and the benefit of increased yield, and reduced rework and scrap. The approach of monitoring 100% of the wafers being processed requires some trade-off in sensitivity compared to traditional standalone metrology tools, but not by much. This paper describes a compact, low-cost wafer defect monitor suitable for integrated metrology applications and capable of detecting submicron defects on semiconductor wafers at an inspection rate of about 10 seconds per wafer (or 360 wafers per hour). The wafer monitor uses a whole wafer imaging approach to detect defects on both un-patterned and patterned wafers. Laboratory tests with a prototype system have demonstrated sensitivity down to 0.3 µm on un-patterned wafers and down to 1 µm on patterned wafers, at inspection rates of 10 seconds per wafer. An ideal application for this technology is preventing photolithography defects such as "hot spots" by implementing a wafer backside monitoring step prior to exposing wafers in the lithography step.

The demands on optical metrology of etched structures continue to increase as microelectronics become more complex and use higher aspect ratios. We will show the ability of the Dainippon Screen trench measurement tool to measure linear trench device dimensions, such as trench depth, width monitoring, and mesa oxide thickness, with high precision and accuracy. The advantages of our tool are high throughput, cost effectiveness and ease of use, because of its optimization using an optical interference calculation. This tool used has demonstrated repeatability on the order of 3σ < 1 nm in Trench Depth and SiO2 thickness measurements.

We proposed a model for highly sensitive detection of residue defects in electron beam defect inspection of photo resist patterns on a metal hard mask and verified the principle of that model. When there are photo resist residue defects on the bottom anti-reflective coating (BARC), the thickness of total organic layer is thicker at the defect pattern than in areas where there is no residue. The model proposed here focuses on this increase in layer thickness. The landing energy of the primary electrons allows electron penetration to the under layer (TiN) in the patterns where there is no defect (thin layer), but does not allow such penetration in the defective patterns (thick layer). In that landing energy region, SEM image contrast differs according to the primary electron penetration or nonpenetration in the non-defective patterns and in the defective patterns. This method detects defects according to the contrast change (penetration contrast method). The principle of this model (i.e., the penetration contrast method) is verified in this report. The behavior of the defect that caused with the variation of an actual exposure condition was compared with this method and without this method. This method was also applied for quantitative detection of defects considered to be caused by dose amount of lithography process. This method was shown to be clearly effective in ADI for the metal hard mask.

In advanced DRAM manufacturing, the process scaling to increase memory cell density creates a difficult challenge for conventional optical or SEM metrology tools to characterize wafer surface profiles after plasma etching. Dry plasma etch processes are used to form critical contact plugs within a stacked capacitor DRAM cell, two of which will be discussed in this article. One contact plug connects a buried digit line to an active area in array, while another contact plug connects a capacitor container to an active area through the first plug. In both cases, the etched surface structure features a complex three-dimensional (3D) topography with a minimum space at ~50nm (see Figure 1). Etch profiles are directly related to the DRAM yield and must be monitored inline. Scanning probe based atomic force microscopy (AFM) is particularly beneficial for this type of dimension measurements. This article presents the methodology and recent results of applying AFM as inline metrology for contact etch control at 70nm node and below. AFM is an advanced, high-resolution 3D imaging tool. It provides nondestructive and direct in-die measurements of the active circuit region on product wafers at the contact etch steps and other critical process layers. Calculated automatically from AFM images, the dry etch depth is used as inline metrology for process control and is a critical metric for process optimization.

The merits of hyper NA imaging using 193nm exposure wavelength with water immersion for 45nm is clear. Scanner focus and dose control is always improving to allow small DOF manufacturing in immersion lithography. However, other process parameters can affect focus and dose control and a real-time monitor capability to detect local focus and exposure conditions on production wafers is required. In this paper we evaluated a focus-exposure monitor technique based on Spectroscopic Critical Dimension (SCD) metrology following the promising results obtained by Kelvin Hung [1] et al. The key attributes of this technique are the implementation on standard production wafers, the high sensitivity to pattern profile modifications and the unique capability of spectroscopic ellipsometry to provide all the information needed to decouple the effects on pattern formation coming from process variations of Advanced Patterning Films (APF) [2], largely adopted for 65/45nm patterning, from coating and, finally, from the pure scanner imaging contributors like focus and exposure. We will present the characterization of this technique for 2 critical layers: active and contacts of a non-volatile memory device, 45nm technology.

We measured the pitch of a 144-nm pitch, two-dimensional grid in two different laboratories. Optical Diffraction gave very high accuracy for mean pitch and Atomic Force Microscopy measured individual pitch values, gaining additional information about local pitch variation. The measurements were made traceable to the international meter. Optical diffraction gave mean value 143.928 ± 0.015 nm (95% confidence limit, per GUM). AFM gave mean value 143.895 ± 0.079 nm. Individual pitch values had standard deviation 0.55 nm and expanded uncertainty ± 1.1 nm. Mean values measured by the two methods agreed within 0.033 nm. Because this was less than the uncertainty due to random variation in the AFM results, it suggests that the AFM measuring and analysis procedures have successfully corrected all systematic errors of practical significance in microscopy. We also discuss what precision may be expected from the AFM method when it is applied to measure smaller pitches.

In this paper, a scatterometry software named ODP^(R) by Timbre Technologies was used to develop BEOL applications to measure the trench and complicated dual damascene structures. Diffraction spectra were collected with Nanometrics normal incidence polarized reflectometer system in the wavelength range of 220~800nm. The measured spectra were analyzed and used as target spectra by ODP-PAS^(R) system. Then the associated models were built to generate the simulated spectra which were used to match the measured spectra. We studied four different structures related to the post trench-and-via etch and post copper CMP processes, including two two-dimensional (2D) line\space structures and two three-dimensional (3D) trench-over-via dual damascene structures. Cross-section TEM (transmitted electron microscopy) measurements were performed to evaluate the performance of ODP measurements. The results show that the correlation between TEM and ODP of CD measurements is good, and the correlation between TEM and ODP of the trench depth measurements is also good. ODP is able to measure the trench and complicated dual damascene structures and further to be used to optimize the process conditions.

With the advancement of lithography, the overlay budget is becoming extremely tight. As the accuracy of overlay is important for achieving a good yield, the demand for the accuracy of overlay is ever increasing. According to the International Technology Roadmap for Semiconductors (ITRS), the overlay control budget for the 32nm technology node will be 5.7nm. The overlay metrology budget is typically 1/10 of the overlay control budget resulting in overlay metrology total measurement uncertainty (TMU) requirements of 0.57nm for the most challenging use cases of the 32nm node. The current state of the art imaging overlay metrology technology does not meet this strict requirement, and further technology development is required to bring it to this level. Especially for exposure tool inspection (e.g. alignment, overlay, wafer stage and distortion), more high accuracy should be required using 'resist to resist' pattern. In this work we simulated the measurement sensitivity for two types of scatterometry based overlay metrology, one is differential signal scatterometry overlay (SCOL), the other is double exposure type (DET).

As semiconductor technology has advanced, the films have become thinner and changed to multi-layer films, such as gate dielectric construction. To deal with these trends, we are continuing development of our spectroscopic ellipsometer with elliptical polarization. We chose a Rotating-Analyzer Ellipsometer (RAE) configuration. The incident light in this type of device is usually polarized linearly, because polarizers do not disperse the light. But the incident light in the ellipsometer described in this paper is elliptical, which has a nearly circular polarization. In this paper, we introduce a technique for solving the dispersion problem.

In the sub-90 nm technology nodes, optical metrology techniques are essential for process control of gate formation steps, from lithography to etch layers such as gate, trench, and dielectric interconnect layers and to spacers and straining layer depositions. Conventionally, optical metrology is based on measurements of periodic line or hole arrays (i.e., gratings) using spectroscopic ellipsometers or polarized reflectometers, collecting data across wide wavelength spectra at a single angle of incidence. In this paper, we present results of measurements on periodic etched amorphous-Si gate line arrays using focused beam ellipsometry (FBE), illuminating at three discrete laser wavelengths while data is collected over angles of incidence ranging from 45° to 65°. Results on thoroughly characterized samples representative of 65 and 45 nm technology are presented. These samples include a variety of both line critical dimensions (CDs) (from 18-50 nm) and line pitches (from 200-700nm) for dense and isolated lines arrays. We discuss precision and accuracy in terms of total measurement uncertainty; spot size, navigation, and tool matching are also presented. FBE-based metrology will meet current process control requirements within a substantial margin.

Optical metrology techniques are essential for process control of the gate formation process steps from lithography to the dielectric, spacers, gate and straining layer deposition in the sub-65nm technology nodes. Traditionally, optical metrology is based on the measurements of periodic lines or hole arrays using a spectroscopic ellipsometer or reflectometer, collecting data across a wavelength range at a single angle of incidence. In this paper, we discuss measurements using Focused Beam Ellipsometry (FBE), illuminating at discrete laser wavelengths while data is collected over a wide angle of incidence range. We verify precision estimates of the different model parameters with actual values obtained from measured data. We show sensitivity ranges for different applications over the space of measured wavelength spectrum from DUV to IR, angle of incidence range, and sample azimuthal orientations. Major factors contributing to the projected recipe performance - wavelength, orientation of the incident beam are discussed.

The interpretation of scatterometry measurements generally assumes that the grating extends over an area large enough to intercept all the illumination provided by an incident beam. However, in practice, the gratings used in scatterometry are relatively small. Thus, the detected light also includes both that scattered by the grating as well as that from a region surrounding the grating because, generally, the incident beam illuminates both the grating and the surrounding region. To model the effects of such real structures, simulations of the effective reflectance were performed whereby the reflection from the grating was considered to be the sum of the diffraction by the grating and the diffraction of the surrounding region, taking into account the beam profile. To demonstrate the model, the illumination field was assumed to be Gaussian. Results are shown for a specific target design consisting of a 50 μm square measured by normal incidence reflectometry. Significant errors occur when the incident profile has wings that fall outside of the profile and when the scattered light is partially apertured.

Optical metrology techniques are essential for process control of gate formation process steps from lithography to the dielectric, spacers, gate and straining layer deposition in sub-90nm technology nodes. Traditionally, optical metrology is based on the measurement of periodic lines or hole arrays using a spectroscopic ellipsometer or reflectometer, collecting data across a wide wavelength spectrum at a single angle of incidence. In this paper, we present results of measurements on periodic Poly-Si gate line arrays using laser based Focused Beam Scatterometry (FBS), illuminating at 3 discrete laser wavelengths while data is collected over an angle of incidence range from 45° to 65°. Accuracy, repeatability, and tool-to-tool matching results for the poly-Si gate line arrays are discussed. Comparison with the CD-SEM and cross-section TEM result for measurement/modeling accuracy is also presented.

Scatterometry is one of the advanced optical metrology techniques has been implemented in semiconductor manufacturing for monitoring and controlling critical dimensions, sidewall angle and grating heights as well as thicknesses of underlying films, due to its non-destructive nature, high measurement precision and speed. In traditional scatterometry approach, the optical properties (n&k's) of film stack have been used as fixed inputs in a scatterometry model, therefore, the process engineers have to assume that there is no significant impact on measurement results by small deviation from pre-extracted n&k's. However, n&k's of actual production wafers will always vary from the fixed values used in the model. The magnitude of the variations and its impact on the accuracy of scatterometry measurements has not been well-characterized yet. In this study, a low-k dielectric stack with noticeable n&k's variations was generated. The low-k dielectric stack has the refractive index (n) variation around 0.01 @ 633nm within a wafer, and is under two layers of patterned PR and BARC. Different scatterometry models with fixed and floated n&k's have been analyzed. Although comparable repeatability was obtained with either fixed or floated n&k's model, the correlation (R²) to CD-SEM result has been improved by floating n&k in the model in comparison to that of fixed n&k model. In this paper, we also discuss some differences in applying various optical models (i.e, EMA and Cauchy) in scatterometry measurements.

Gate critical dimension (CD) common window (UDOF) is less than 0.25μm below 110nm-node. It's a serious impact by scanner leveling tilt due to it'll result in defocus, profile changed and then suffer etch bias. Here, we provide an easy and convenient method to monitor daily leveling tilt of ASML 193nm by SCD. Of course, it can also be used for other vendors' scanner including DUV 248nm, 193nm & immersion 193nm. SCD can measure side wall angle (SWA) of photo resist and it's a factor of focus. We can design one mask with SCD grating pattern and layout them at four corners of mask. Collect the SWA data of four corners by different tilt at x and y direction and then we can find the correlation within SWA bias and leveling. It's an easy method to monitor scanner leveling issue and early alert for excursion case.

In this paper, we analyze the nonstandard finite-difference time-domain (NS-FDTD) method for the rectangular prismatic and cylindrical medium mounts that are put on the substrate periodically. FDTD is useful for analyzing the light scattering from arbitrary shape grooves and mounts. Using the NS-FDTD algorithms, we can get the deep null in the dispersion error at the design frequency and the error is nearly sixth power of grid size with a same computational cost. First, the 3D NS-FDTD formulation is obtained from Maxwell equation for the conducting medium. We analyze structures of rectangular prismatic and cylindrical mounts on the substrate. We show the propagation characteristic calculated by NS-FDTD. Next, the standard (S) FDTD and NS-FDTD reflectance convergences are checked for the grid size h (=Δx=Δy=Δz) changes. The reflectance is compared with the RCWA results. For the case that the layer lattice and the substrate were the same silicon and had some extinction coefficient, the NS-FDTD reflectance convergences are better than the S-FDTD convergences. Finally, we calculate the reflectance from the cubic and cylindrical periodic mounts put on the silicon substrate.

Increase of Depth of Focus (DOF) and higher Numerical Aperture (NA), make of immersion lithography a sub-50nm technology node enabler. At the same time it introduces a range of new defect types, also known as immersion defects. According to the ITRS roadmap, the Smallest Defect Of Interest (SDOI) for the 45nm node has a size of 30nm [1] which is the minimal defect size which poses risk to the integrity of the post litho chain processes. A novel approach of Immersion Defectivity Baseline creation and monitoring has been developed for the 45nm technology node by ASML, supported by Applied Materials. An Immersion Defectivity Baseline consists of: a qualified stack, a dedicated defectivity reticle, a Defect Inspection Tool with an optimized inspection recipe, a Defect Review SEM with an optimized defect review recipe and a defect qualification scheme. The new approach to Immersion Defectivity Baseline creation is based on the combined capabilities of highest resolution bright-field inspection and SEM (Scanning Electron Microscopy) review that are available today, with a unique qualification methodology using printed programmed defects that cover the full printable size range. The inspection tool's SDOI detection sensitivity has been optimized for engineering, production as well as monitoring modes, with negligible nuisance rate and basic classification capability followed by highly accurate SEM review and classification. As a result, it enables a stringently controlled, highly efficient, automated defect classification for baseline monitoring and increased productivity. The SEM material analysis sub-apparatus complete the control loop for baseline creation and excursion control. This paper presents a protocol for Immersion Defectivity Baseline creation and control methodologies used for the latest ASML immersion scanner.

The growing demands of metrology have tightened the allowable tolerances of depth and step height measurements in semiconductor and nanotechnology fabrication. With manufacturing tolerances in the range of 1 nm to 3 nm, special care is required to achieve calibration traceable to the SI (Systeme International d'Unites, or International System of Units) meter in order to meet manufacturing requirements. This paper describes the steps taken to achieve this level of measurement capability. The methodology used to achieve this traceable calibration is to use an inclined plane to establish linearity over the step height range of interest of a reference critical dimension atomic force microscope (CDAFM) and then to link a single traceable step height somewhere within this range. The deviations from perfect linearity in the vertical position are shown in the paper. Then using this newly calibrated reference CD-AFM, various step height structures were used to transfer the traceable calibration from the reference CD-AFM to one-dimensional AFMs (1DAFM) used for manufacturing process control. A traceable step height calibration, with an expanded uncertainty of 2.24 nm (k = 3) is demonstrated for the reference CD-AFM. From this result, a traceable calibration of the manufacturing AFMs with a combined expanded uncertainty of 2.8 nm (k = 3) for a nominal 164 nm step height is developed.

Patterning of contact hole is always the most difficult process among many types of pattern formations. Specially for the Extreme Ultra-Violet Lithography (EUVL), it will be even more difficult to make perfectly circled contact hole due to the shadow effect. The shape of contact hole will be elliptical because the vertical axis opening is different from the horizontal axis opening. We studied this behavior for 22 nm node contact hole patterns. We varied the pitch of the regular contact hole array. The dependency of the position and density is studied for the random array. In addition to that the thickness of the absorber and the reflectivity of the multilayer are varied to see non-circular contact hole. In order to make desired circular contact hole with uniform width, direction dependent mask bias is applied in addition to the normal optical proximity correction.

As the advanced IC device process shrinks to below sub-micron dimensions (65nm, 45 nm and beyond), the overall CD error budget becomes more and more challenging. The impact of lithography process parameters other than exposure energy and defocus on final CD results cannot be ignored any more. In this paper we continue the development of the advanced lithography parameters model which we presented last year. This year we achieved to decouple 4 lithography parameters: exposure, focus, PEB temperature and laser bandwidth (or z-blur). To improve the accuracy and precision of the model, new scatterometry marks are designed to reduce the pitch dependent accuracy impact of sidewall angle and photoresist height for scatterometry metrology. The concept of this kind of scatterometry mark design is from T.A. Brunner's paper "Process Monitor Gating" [SPIE Vol. 6518, 2007]. With this concept, new scatterometry marks are designed to increase the accuracy of scatterometry measurement without sacrificing the process sensitivity and thus improve the model prediction accuracy.

As the Integrated Circuit manufacturing market has begun a concerted effort toward the mass production of 45nm node material, the emergence of inaccurate defect sizing and subsequent mis-identification of surface and subsurface defects from Surface Scanning Inspection Systems (SSIS) has become a major impediment for accurate Scanning Electron Microscope (SEM) Automated Defect Redetection (ADR) and Automated Defect Classification (ADC). Due to the increased manufacturing cost of Silicon Wafers (Silicon on Insulator, Strained Silicon, Strained Silicon on Oxide, Silicon on Silicon Germanium) and the desire from IC manufacturing companies for a continually increasing level of Incoming Quality Assurance (IQA) wafer cleanliness, the cost of IC manufacturing has dramatically risen in recent years. The increased cost of manufacturing for both IC manufacturing and Silicon Wafer manufacturing is driving the requirement for a high throughput Defect Review SEM that is able to independently overcome the defect sizing and defect classification challenges from both the 45nm and 90nm nodes. The benefits of improved SEM ADR and ADC performance must not come at the expense of the SSIS throughput. This paper provides a study of the methods employed in multiple manufacturing lines to provide rapid feedback of yield impacting defects, allowing for improved root cause analysis and improved fab productivity.