This PDF file contains the front matter associated with SPIE Proceedings Volume 7379, including the Title Page, Copyright information, Table of Contents, and Conference Committee listing.

Cost and imaging are becoming big concerns in lithographic patterning of 32-nm half pitch and beyond, affecting the choice of lithographic patterning tools and the corresponding mask technology. In this paper, the cost and imaging aspects of ArF immersion double patterning, multiple e-beam maskless lithography, and extreme-uv lithography are discussed with proposals to make the cost acceptable. The impacts of these technologies to the masking industry are quite different. They are also given here. Some comments are made on nano-imprint lithography.

As the device design rule shrinks, photomask manufacturers need to have advanced defect controllability during the Cr and MoSi etch in the process of phase shift mask(PSM). In order to decrease the number of defects, which may be originated from the mechanical transferring, plasma ignition and cross-contamination of resist stripping or cleaning process, a novel plasma etching process was developed in a commercial photomask etcher. In this process named as the "In-situ. etching", Cr and Mosi is etched stepwise in a chamber. The In-situ. etching processes produce better defect level than that of the conventional process without deteriorating other mask quality such as CD performance, profile and process reproducibility. Particle generated by plasma ignition in in-situ. etching lead to defect which is an obstacle in Cr etch. Because plasma is stable from Cr etch to Mosi etch, no defect is added in Mosi etch. Furthermore quantitative analysis of by-products deposited and eroded by the chamber position shows that by-products are comprised of Al, chlorine, carbon. These byproducts can be removed by fluorine-containing plasma.

Use of optical photomasks will extend to the 22-nm node and beyond. Mask minimum resolution and critical dimension (CD) requirements for this node are very challenging to the mask industry. Optimization of resist materials and resist thickness are key factors for improving CD performance. In general, thinner resists result in better minimum resolution performance. The minimum useable resist thickness is often linked to the chrome hard mask dry etching performance. More specifically, improvement of chrome etch rate selectivity to resist while simultaneously maintaining good CD performance is difficult. In order to use a very thin e-beam resist, the underlying chrome hard mask material thickness needs to be thin or it needs to be comprised of a material that has a fast etch rate and good dry etch selectivity to resist. Use of thin and/or fast etch rate hard mask materials that are capable of reducing dry etch induced CD error such as etch bias, etch bias uniformity, etch bias linearity, and etch global loading effect is required for meeting 22-nm mask requirements. In this paper, the dry etching effect dependence on hard mask thickness, hard mask material composition and resist thickness for building advanced binary masks for 22-nm node is studied. The results from this work will show that dry etch induced CD error such as etch bias, etch bias uniformity, etch bias linearity, and etch global loading effect are significantly improved by use of an ultra thin or high etch rate hard mask material.

Previous work has shown that photomask blank flatness as well as photomask patterning and pelliclization all play an important role in finished photomask flatness. Additional studies have shown that pellicle mounting techniques, pellicle adhesives, frame flatness and shape and pellicle mounting tools play a role as well. It has become clear that frame flexibility, coupled with frame mounting surface flatness and shape are the principal factors influencing the pellicle effect on the mask distortion. Pellicle suppliers have begun to evaluate various polymers as potential replacements for the standard aluminum frame in current use. The elasticity of the frame adhesive has also been adjusted to evaluate its effect on the pellicle influence on mask flatness. This paper describes some joint evaluations between IBM, Toppan and ShinEtsu, performed to determine the effect of pellicle frame composition,, mount surface flatness, adhesive elasticity and adhesive surface flatness on the distortion of photolithography masks. It demonstrates that polymer pellicle frames with more flexible adhesive improve finished mask flatness approximately the same amount as reducing the total frame standoff height of aluminum frames with conventional adhesive.

Most problems in photomask fabrication such as pattern collapse, haze, and cleaning damage are related to the behavior of surfaces and interfaces of resists, opaque layers, and quartz substrates. Therefore, it is important to control the corresponding surface and interface energies in photomask fabrication processes. In particular, adhesion analysis in microscopic regions is strongly desirable to optimize material and process designs in photomask fabrication. We applied the direct peeling (DP) method with a scanning probe microscope (SPM) tip and measured the adhesion of resist patterns on Cr and quartz surfaces for photomask process optimization. We measured adhesion and frictional forces between the resulting collapsed resist pillar and the Cr or the quartz surface before and after the sliding. We also studied the effect of surface property of the Cr and quartz surfaces to resist adhesion. The adhesion could be controlled by surface modification using silanes and surface roughness on Cr blanks. We also discuss the relationship between the adhesion observed with the DP method and the properties of the modified surfaces including water contact angles and local adhesive forces measured from force-distance curves with an SPM.

Photomask feature size has decreased in accordance with constant downscaling of semiconductor device size with generation changes in every 2-3 years, as in the ITRS Roadmap. However, since exposure wavelength has been unable to keep its pace with decreasing feature size, resolution enhancement techniques have been used to bring the generation changes in photomask technologies. A typical resolution enhancement technique of using sub-resolution assist features (SRAF) requires patterning of small features and that increases difficulties in mask manufacturing. Under such circumstances, we are presenting a study focusing on EB-resist development in the manufacturing process. In this paper, we study and report development methods aiming to improve develop loading effect and resolution limit.

In recent years, photomask resist strip and cleaning technology development was substantially driven by the industry's need to prevent surface haze formation through the elimination of sulfuric acid from these processes. As a result, ozone water was introduced to the resist strip and cleaning processes as a promising alternative to a Sulfuric - Peroxide Mixture (SPM). However, with the introduction of 193i double patterning, EUVL (Extreme Ultraviolet Lithography) and NanoImprint Lithography (NIL) the demand on CD-linewidth control and surface layer integrity is significantly expanded and the use of ozone water is questionable. Ozone water has been found to cause significant damage to metal based mask surface layers, leading to significant changes in optical properties and CD-linewidth shift. In this paper HamaTech APE demonstrates the use of an alternative acid-free resist strip and cleaning process, which not only overcomes the named drawbacks of conventional ozone water use, but reduces resist strip time by 50% to 75%. The surface materials investigated during this study are; chrome absorber layers on binary masks, MoSi based shifters, chrome hard mask layers on EPSM, and ruthenium capping layers on EUV masks. Surface material integrity and CD-stability results using this new, acid-free approach are presented in the following pages.

The authors are reporting on the comparison of various industry methods of managing, controlling and limiting haze growth on 193nm reticles. This comparison includes reporting on the results from the Reticle Haze Treatment (RigHT) process developed at Micron / Photronics Mask Technology Center and transferred to Photronics, Inc. This process provides 193nm PSM reticles that have shown no haze growth after excessive wafer exposures and are usable for the life of the reticle.

As we approach the 22nm half-pitch (hp) technology node, the industry is rapidly running out of patterning options. Of the several lithography techniques highlighted in the International Technology Roadmap for Semiconductors (ITRS), the leading contender for the 22nm hp insertion is extreme ultraviolet lithography (EUVL). Despite recent advances with EUV resist and improvements in source power, achieving defect free EUV mask blank and enabling the EUV mask infrastructure still remain critical issues. To meet the desired EUV high volume manufacturing (HVM) insertion target date of 2013, these obstacles must be resolved on a timely bases. Many of the EUV mask related challenges remain in the pre-competitive stage and a collaborative industry based consortia, such as SEMATECH can play an important role to enable the EUVL landscape. SEMATECH based in Albany, NY is an international consortium representing several of the largest manufacturers in the semiconductor market. Full members include Intel, Samsung, AMD, IBM, Panasonic, HP, TI, UMC, CNSE (College of Nanoscience and Engineering), and Fuller Road Management. Within the SEMATECH lithography division a major thrust is centered on enabling the EUVL ecosystem from mask development, EUV resist development and addressing EUV manufacturability concerns. An important area of focus for the SEMATECH mask program has been the Mask Blank Development Center (MBDC). At the MBDC key issues in EUV blank development such as defect reduction and inspection capabilities are actively pursued together with research partners, key suppliers and member companies. In addition the mask program continues a successful track record of working with the mask community to manage and fund critical mask tools programs. This paper will highlight recent status of mask projects and longer term strategic direction at the MBDC. It is important that mask technology be ready to support pilot line development HVM by 2013. In several areas progress has been made but a continued collaborative effort will be needed along with timely infrastructure investments to meet these challenging goals.

We have developed an actinic full-field mask blank inspection system to detect multilayer phase defects with dark field imaging. Using this system a non-commercial mask was inspected and real defects were detected by setting the system at low false detection threshold. A 1.5 mm square area (containing no absorber) was inspected three times, and probabilities of defect detection and false detection were evaluated. Of the total number detected, 81.5 % of them exhibited 100% percent probability of detection, while 0.8 % of them indicated false detection. The same area was also inspected with a conventional inspection system, and both inspection results then were compared. Among the defects detected, 94 % of them could be detected only with the actinic system, while 1.1 % of them could be detected only with the conventional laser-based inspection system. The detected defects were observed with AFM and SEM. In summary, phase defects smaller than 100 nm could be detected only with the actinic system, while particles smaller than 200 nm could be detected only with the conventional system.

Extreme ultraviolet lithography (EUVL) is a leading technology to succeed optical lithography for high volume production of 22 nm node and beyond. One of the top risks for EUVL is the readiness of defect-free masks, especially the availability of Mo/Si mask blanks with acceptable defect level. Fast, accurate and repeatable defect inspection of substrate and multi-layer (ML) blank is critical for process development by both blank suppliers and mask makers. In this paper we report the results of performance improvements on a latest generation mask blank inspection tool from Lasertec Corporation; the MAGICS M7360 at Intel Corporation's EUV Mask Pilot Line. Inspection repeatability and sensitivity for both quartz substrates (Qz) and ML blanks are measured and compared with the previous Phase I tool M7360. Preliminary results of high speed scan correction mirror implementation are also presented

We reported that we were successful in our 45nm technology node device demonstration in February 2008 and 22nm node technology node device patterning in February 2009 using ASML's Alpha Demo Tool (ADT).1, 2, 3 In order to insert extreme ultraviolet (EUV) lithography at the 15nm technology node and beyond, we have thoroughly characterized one EUV mask, a so-called NOVACD mask. In this paper, we report on three topics. The first topic is an analysis of line edge roughness (LER) using a mask Scanning Electron Microscope (SEM), an Atomic Force Microscope (AFM) and the Actinic Inspection Tool (AIT) to compare resist images printed with the ASML ADT. The results of the analysis show a good correlation between the mask AFM and the mask SEM measurements. However, the resist printing results for the isolated space patterns are slightly different. The cause of this discrepancy may be resist blur, image log slope and SEM image quality and so on. The second topic is an analysis of mask topography using an AFM and relative reflectivity of mirror and absorber surface using the AIT. The AFM data show 6 and 7 angstrom rms roughness for mirror and absorber, respectively. The reflectivity measurements show that the mirror reflects EUV light about 20 times higher than absorber. The last topic is an analysis of a 32nm technology node SRAM cell which includes a comparison of mask SEM image, AIT image, resist image and simulation results. The ADT images of the SRAM pattern were of high quality even though the mask patters were not corrected for OPC or any EUV-specific effects. Image simulation results were in good agreement with the printing results.

About the patterned media magnetic recording technology, which is anticipated one of the new generation technologies to replace conventional perpendicular magnetic recording beyond 1Tb/in², the technology back ground, two major options, performance expectations were discussed. Then the requirements for the template (mold) for the nano-imprint lithography, which is irreplaceable technology for pattern media, were discussed.

Nanoimprint lithography (NIL) is one promising candidate for fabricating a patterned media to be used in the next generation of hard disk drives. It is expected that the pitch, characterizing the feature size of the media will become as low as 40-50 nm for Discrete-Track Media (DTM) by 2010 and 25 nm for Bit-Patterned Media (BPM) by 2012. Electron beam lithography is usually employed for fabricating the nanoimprint mold used for nanoimprint lithography. ZEP520A, the high-resolution resist that is commonly used for this fabrication has a low throughput; caused by the low sensitivity when used at the high acceleration voltage of 100 kV. To solve this problem, we evaluated a new high-resolution, chemically amplified resist (CAR) developed by TOKYO OHKA KOGYO Co., LTD., that was specifically developed for high resolution, instead of high sensitivity, with over twice the sensitivity of ZEP520A and a resolution of 50 nm pitch or less. A spot-electron beam (EB) writer with an acceleration voltage of 100 kV (100 kV-SB) was employed and the new CAR and ZEP520A were compared for resolution and sensitivity. Results indicated that the new CAR patterns were resolved down to a 48 nm pitch, but were collapsed even at a64 nm pitch. To prevent the collapse, we attempted to optimize the baking conditions and examined the primers as promoters of the adhesion between the resist patterns and the substrate surface. As a result, a resist pattern as low as a 48 nm pitch was obtained. We report on the performance of the new CAR and the fabrication of the Si mold by using the new CAR.

Step and Flash Imprint involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed leaving a patterned solid on the substrate. Compatibility with existing CMOS processes requires a mask infrastructure in which resolution, inspection and repair are all addressed. The purpose of this paper is to understand the progress made in inspection and repair of 1X imprint masks A 32 nm programmed defect mask was fabricated. Patterns included in the mask consisted of an SRAM Metal 1 cell, dense lines, and dense arrays of pillars. Programmed defect sizes started at 4 nm and increased to 48 nm in increments of 4 nm. These defects were then inspected using three different electron beam inspection systems. Defect sizes as small as 8 nm were detected, and detection limits were found to be a function of defect type. Both subtractive and additive repairs were attempted on SRAM Metal 1 cells. Repairs as small as 32nm were demonstrated, and the repair process was successfully tested for several hundreds of imprints.

Achieving line-edge/width roughness (LER/LWR) specifications remains as one of the most significant challenges facing the commercialization of extreme ultraviolet (EUV) lithography. LER is typically viewed as a resist problem; however, recent simulation results have shown that the mask can also be a significant contributor. Problems arise from both mask absorber LER as well as mask multilayer roughness leading to random phase variations in the reflected beam and consequently speckle. Here we describe these effects in detail and explore how they will impact EUV mask requirements for the 22-nm half-pitch node and beyond. Process window analysis yields mask multilayer roughness specifications on the order of 50 pm.

We estimated aberrations using Zernike sensitivity analysis. We found the difference of the tolerated aberration with line direction for illumination. The tolerated aberration of perpendicular line for illumination is much smaller than that of parallel line. We consider this difference to be attributable to the mask 3D effect. We call it mask-induced aberration. In the case of the perpendicular line for illumination, there was a difference in CD between right line and left line without aberration. In this report, we discuss the possibility of pattern formation in NA 0.25 generation EUV lithography tool. In perpendicular pattern for EUV light, the dominant part of aberration is mask-induced aberration. In EUV lithography, pattern correction based on the mask topography effect will be more important.

In extreme ultraviolet lithography (EUVL), mask non-flatness contributes to overlay errors in EUVL scanners. Tight non-flatness targets are required to meet future overlay; for example, the International Technology Roadmap for Semiconductors (ITRS) requires that substrate non-flatness will need to decrease to 36 nm peak-to-valley in 2013. To meet these tight non-flatness values, suppliers must use aggressive polishing steps, adversely impacting substrate yield and mask blank cost of ownership. An alternative option is to use image placement corrections at the writing step of the reticle to compensate for the predicted impact of the non-flatness pattern placement errors, which would allow the specifications to be relaxed. In this paper, we will present the results of using e-beam image placement corrections during mask writing to compensate for mask non-flatness. A low thermal expansion material (LTEM) substrate with about 500 nm of nonflatness was employed. Three different compensation methods were used to calculate the predicted image placement errors based upon the mask non-flatness, including the expected errors from scanner chucking. The mask was designed to use a repeating set of four ASML alignment marks (XPA marks) across the mask. During e-beam writin, one mark was left uncompensated, and the three different compensation methods were applied to the remaining marks. The masks were exposed using the ASML alpha demo tool (ADT). An overview of the viability of e-beam correction methodologies to compensate for mask non-flatness is presented based upon the wafer overlay results.

Full-field printing on the ASML Alpha Demo Tool, followed by wafer inspection on a KLA-T 2800, is used to qualify typical defectivity levels of EUV reticles. Mask defects are found as repeaters among multiple dies on wafer. The uniform pattern consists of dense lines and spaces. In a first reticle with 40nm linewidth, high levels of natural defects have been found of which a relatively large share was considered as multilayer (ML) type defects, because they printed as rings. Simulation of ML defects could explain this printing behavior as a function of height, size and slope. The main parameter determining the printing behavior of a ML defect is its height. A local distortion of the upper part of the ML, as thin as ~2nm can already print. On-reticle analysis of the ring defects by SEM showed that the defects are present on the absorber, which already explains the printing result. Yet, still several other defects were found to print on the wafer, whereas they were not visible on the reticle and considered local distortions of the ML. Printing results with a second version of the mask that additionally includes programmed multilayer defects with 3nm height confirmed the pronounced printing impact of ML defects as they were simulated. Encouragingly low numbers of natural defects have been found on a third reticle. With this reticle also a first correlation has become possible between the defect maps obtained from wafer inspection, (direct) mask inspection, and blank inspection. This is a viable method to highlight potential gaps between the capability of these tools and printability of defects.

Mask set price is soaring along with technology node advancement. One reason is that the number of masks per set is increasing with the geometry scaling. Another reason is that low k1 lithography with highly complex OPCs tightens dimensional mask specifications as to result in higher mask-making tool costs and lower production yield. Under these circumstances, tool cost reduction and production yield improvement are immensely required to reduce mask cost. Expensive quality-assured tools are indispensable to achieve the desired accuracy. Then, higher throughput and technical applicability of the same tool over multiple generations are definitely needed to improve total tool CoO. Meanwhile, not only such conventional basic approaches as improving field level and process performance but optimizing mask specifications efficiently is emerging as a key factor for keeping mask production yield high. Usually mask specifications are determined by the error budget allocated from the total lithography budget. In order to cope with the tighter specifications some sensible approaches have recently been proposed. Mask DFM is receiving particular attention as a new method being strongly linked to lithography and wafer fabrication technologies (1)(2)(3)(4). In this presentation, logical way to define the main mask specifications such as CD, defect and image placement accuracy is shown and sensible ways to sustain them are referred.

Mask order automation has increased steadily over the years through a variety of individual mask customer implementations. These have been supported by customer-specific software at the mask suppliers to support the variety of customer output formats. Some customers use the SEMI P10 ¹ standard, some use supplier-specific formats, and some use customer-specific formats. Some customers use little automation and depend instead on close customer-supplier relationships. Implementations are varied in quality and effectiveness. A major factor which has prolonged the adoption of more advanced and effective solutions has been a lack of understanding of the economic benefits. Some customers think standardized automation mainly benefits the mask supplier in order entry automation, but this ignores a number of other significant benefits which differ dramatically for each party in the supply chain. This paper discusses the nature of those differing advantages and presents simple models suited to four business cases: integrated device manufacturers (IDM), fabless companies, foundries and mask suppliers. Examples and estimates of the financial advantages for these business types will be shown.

Turn around time (TAT) of mask qualification is one of the most important factors for high-end mask installation to LSI production lines. Accurate mask qualification with shorter TAT for mask process updates brings about steep rampup of LSI volume production. In this paper, an innovative approach is described for mask qualification with a die-todatabase (D2DB) inspection system that can accomplish both qualification accuracy and short TAT in low k1 lithography. The D2DB inspection system, NGR2100[1], has features satisfying the above requirements owing to larger field of view (FOV) and higher probe current than those of CD-SEM. Compared with the conventional optical inspection tool, the system provided higher accuracy in extracting fatal defects called "hotspots". Also, hotspots extracted by the system covered all killer hotspots extracted by electrical and physical analysis [2]. The contours of hotspots extracted by NGR2100 are transferred to GDS data format to compare hotspots between conventional mask process and updated mask process. If the differences between the contours are within an assumed tolerance, the system provides the qualification for updated mask process. As a result, qualification TAT was reduced by as much as two months compared with the conventional electrical qualification on wafers.

The cost of production of a photomask set has been soaring over the last few years, and now reaches $1 million to $2 million, almost 10% of the overall cost of a new project development. And new projects have seen their profitability lifetime reduced over time to 3 to 6 months. Any uncontrolled increase in cost or delay can make the difference between a profitable or non profitable project, and can even lead to the cancellation of the entire project. For the last few years, silicon manufacturability issues have been taken into account in the design process through a widespread use of Design For Manufacturing tools, but so far the impact of design on mask manufacturability has not been thoroughly studied. This article presents a novel Design For Mask Manufacturing approach, which defines a robust process encompassing design rules and constraints, validation procedures, exchange mechanisms between all actors in the flow (designers, mask shops, and foundry) in order to minimize the number and impact of mask design issues, to trace their root causes and severity, and automation of the handoff of design and administrative data to the mask shop. A demonstrator for the DFMM flow is being shown.

As the Manufacturing Rule Check (MRC) error counts are very huge, it has been getting difficult to review by each point and maybe some of the design errors will be ignored. It's necessary to reduce the review error counts and improve the checking methods. The paper presents an error classification function and auto-waived mechanism for decreasing the repeated MRC errors in MRC report. In auto-waived mechanism, the report will omit the error point if it is same as previous report and the defect location output will keep all of the error points for Do Not Inspection Area (DNIR) reference. (DNIR needs customer's approval). Furthermore, it is possible to develop an auto-waived function to skip the confirmed errors which is provided by customer with a marking information table or GDS/OASIS database. Besides, this paper also presents how these errors can be grouping and reducing checking time.

Smaller design pattern feature sizes continue to increase mask data file sizes, which increases mask data processing (MDP) times. To satisfy the need for faster turn-around-time, MDP has progressively migrated from single-computer computation, to multi-threading, and then to distributed processing on multiple computers. The availability of low cost multi-core processors can be used advantageously to reduce Mask Data Preparation runtime. Compared to single core processors, multi-core processor have higher performance, however, total available memory and I/O bandwidth need to be increased proportionally with the additional cores. Memory per core and available I/O bandwidth limit the maximum number of cores that can be effective with distributed processing. When a single job is broken down to 2 or more tasks, the granularity of the tasks influences the efficiency of the processing. Smaller tasks allow for smaller memory footprint, better distribution of tasks and increased scalability, but increase input file access time and reduce output data compaction. By choosing a combination of multi-threading and distributed processing, faster run-time and better scalability can be achieved, as compared to either technique alone. The optimal configuration depends on the number of cores per processor, number of processors and memory per core.

The aim of this paper is to explore the use of the Graphic Processing Unit (GPU) for mask design using inverse lithography technique (ILT). We extend a newly proposed ILT algorithm called cost-function-reduction method (CFRM) to general partial-coherence image systems. To release heavy computational cost in this algorithm such as intensity computation, the algorithm is modified for GPU implementation. The scalability of the GPU implementation is demonstrated using different sizes of matrix in incoherence image system and partial-coherence image system. The total GPU optimization time for a 25μm×25μm mask in partial-coherence image model is about 8.2 second. About 15X performance increase have been achieved than that of an algorithm solely implemented on a high-end CPU. The maximum mask size is limited by GPU card memory.

We quantify the OPC accuracy improvement obtained by including the stepper signatures in the OPC model. The analysis takes into account the complete cycle of OPC model calibration, OPC execution, and image verification of the OPCed photomask. We use the Nikon Scanner Signature File (NSSF) version 1.5 for the NSR-S610C immersion scanner; and an OPC model that accounts for vectorial imaging, the polarization map of the illumination, and the pupil Jones matrix map of the projection optics. We verify that the OPC model closely agrees with a commercial lithography simulator. We use a 42 nm half-pitch NAND-flash layout to illustrate our point. Post-OPC CD errors obtained when excluding information about the stepper signature are 11.9 nm (max) and 2.8 nm (RMS). These values drop to 1.9 nm (max) and 0.7 nm (RMS) when the NSSF is included in the OPC model. In practice, OPC models are calibrated using CD measurements taken on printed test patterns, which are affected by the scanner signature. OPC model calibration indirectly and partially captures the scanner signature; however, including the NSSF directly in the model increases accuracy. In addition, the number of edge-placement errors (EPE) exceeding 1 nm dropped by an order of magnitude when the NSSF was directly included in the OPC model, as compared to capturing the same information incompletely using the model calibration instead.

Lithography compliance check (LCC), which is verification of layouts using lithography simulation, is an essential step under the current low k1 lithography condition. In general, LCC starts from primitive cell block level and checks bigger block level in the final stage. However, hotspots may be found by chip level LCC although LCC does not find any hotspots in a primitive cell block check, because conventional LCC for primitive cell blocks cannot consider the influence of the optical proximity effect from neighboring cell structures at the chip level. This paper proposes a new verification method in order to resolve this issue. It consists of three steps. The first step is the same as the conventional method; run LCC and judge if there are hotspots, which need to be fixed. The second step is judge if there are warmspots, which represent the pattern structures with borderline litho margin, and if warmspots are found, add a pattern that makes process margin worst. The third step is to fix the hotspots changing from warmspots by adding the worst pattern. Based on this method, primitive cell block LCC can guarantee that there are no hotspots at the chip level without chip level LCC. We discuss the detail of process flow of this verification method and validate the effect of this method.

Flash memory is an important driver of the lithography roadmap, with its dramatic acceleration in dimensional shrink, pushing for ever smaller feature sizes. The introduction of hyper-NA immersion lithography has brought the 45nm node and below within reach for memory makers using single exposure. At these feature sizes mask topology and the material properties of the film stack on the mask play an important role on imaging performance. Furthermore, the break up of the array pitch regularity in the NAND-type flash memory cell by two thick wordlines and a central space, leads to feature-center placement (overlay) errors, that are inherent to the design. An integral optimization approach is needed to mitigate these effects and to control both the CD and placement errors tightly. In this paper we will show that aerial image measurements at mask-level are useful for characterizing the gate layer of a NAND-Flash design before exposure. The aerial image measurements are performed with the AIMSTM 45-193i. and compared to CD measurements on the wafer obtained with an XT:1900Gi hyper-NA immersion system. An excellent correlation is demonstrated for feature-center placement errors and CD variations across the mask (see Figure 1) for several features in the gate layer down to 40nm half pitch. This shows the potential to use aerial image measurements at mask-level in combination with correction techniques on the photomask, like the CDC200 tool in combination with exposure tool correction techniques, such as DoseMapperTM, to improve both across field and across wafer CD uniformity of critical layers.

The information of the chromium top layer is important in photomask fabrication. Resist coating process and optical transmittance change of chromium after mask cleaning process depend on the surface morphology and thickness. In this paper, we present that ellipsometry, the nondestructive optical measurement method, is an effective and convenient method for the inspection of chromium oxide on the quartz blank. We checked data obtained by ellipsometry for chromium surface morphology with atomic force microscope, for surface energy with contact angle measurement, and for optical density change with optical transmittance measurement. It turns out that ellipsometry gives successfully the information of chromium oxide on the quartz blank.

State-of-the-art pattern registration tools have to fulfill stringent requirements both in terms of reproducibility and accuracy, as photomask sets are often fabricated in a distributed fashion worldwide and yet have to perfectly match in their respective overlay properties. One option to calibrate the various metrology tools with respect to each other is to utilize a standard, a "golden mask." Alternatively, "self-calibration" strategies can be employed, which offer certain distinct advantages. This concept of calibration is illustrated by several examples. Merit functions are defined to compare the quality of the calibration procedures, and it is shown how they can be used to optimize the calibration with respect to its efficiency in filtering measurement noise. A symmetry based analysis is introduced to reveal systematic weaknesses of potential calibration sequences, also indicating the necessary steps to overcome these problems. An extension of the theory is given that allows to suppress a certain class of systematical errors, and it is studied under which conditions it can be applied.

Pattern placement on reticles is considered a key performance issue for Double Patterning Lithography (DPL) for the 32nm node and beyond. Pattern placement metrology on reticles may therefore become an important yield enabling factor for 32nm node semiconductor device manufacturing. Today in the case of logic designs, mask metrology is performed on dedicated registration test patterns in the kerf area between active dies, or on metrology cells inside the active array. However, with the introduction of DPL, the overlay requirements will become more stringent and therefore reticles need to be characterized in greater detail. In order to achieve the tighter overlay performance targets of less than 7nm [1] on the wafer for the 32nm node, registration metrology on the mask is expected to include "active" structures in the die. These structures may not have parallel edges and thus standard edge detection algorithms for registration metrology may not be applicable. We will explain the measurement principle and report on the first measurement results obtained on from the actual state-of-the-art registration metrology tool on test reticles simulating metrology in the dense active array. These data will be analyzed and compared with results achieved using standard registration pattern. Data evaluation software algorithms are already available to compare pattern placement performance between reticle layers.

Immersion lithography has moved into 45nm node and will soon go into 32nm node. Alternating Phase Shifting Masks (alt. PSM's) are one of the most effective methods to enhance resolution and process window. . However there are two major challenges: intensity balancing and quartz dry etch process. The dry etch process requires not only an uniform quartz etch but also a good linearity over a wide range of feature sizes to ensure a 180° phase shift through pitch and duty cycle. Phase errors lead to an image placement error during printing becoming even worse through focus. As feature sizes shrink imaging effects and 3D mask effects impact the phase shift and accurate phase shift measurement becomes extremely important. In this paper we report on phase shift measurements through pitch and duty cycle on alt. PSM taken on the newly developed phase metrology system Phame® and compare them to rigorous 3D simulations. Furthermore we correlate the phase shift measurements to process window data such as maximum exposure latitude. Through pitch investigations on alt. PSM show that for print pitches below 200nm (wafer level) the phase shift drops significantly below 180° which will lead to an image placement error during printing and a shrinking process window. Furthermore a strong correlation between phase shift and maximum exposure latitude is shown. Largest maximum exposure latitude is achieved for phase shift close to 180°. Phame® enables optical phase shift measurement in critical production features down to 120nm half pitch providing the opportunity to optimize the quartz dry etch process in terms of signature and linearity. This will help to optimize the phase shift of critical features on alt. PSM for largest process window and hence increase end of line yields for reducing overall chip manufacturing costs.

Recent Low k1 era requires aggressive OPC technology with advanced lithography technology. The aggressive OPC contains the rounded pattern and a lot of assistant pattern which are the main source to increase the shot division. We have defined the shot complexity, which is defined by the ratio of number of shot between the interested pattern and the 1:1 L/S pattern. Based on shot complexity parameter, we have estimated the writing time as the device node decreases. We expect that the aggressive OPC and the high dose could generate severely the writing time issue in 32nm node era.

In the Mask D2I project at ASET, we are developing a novel electron beam exposure system using the concepts of MCC (multi column cell), CP (character projection), and VSB (variable shaped beam) to improve the throughput of electron beam exposure systems. In this paper we present the outline of a proof-of-concept system of MCC, results of the evaluation of fundamental functions of the system, and early writing results including multi column stitching. In the evaluation of fundamental functions of the system, we found that there is no interference on beam positions among the CCs, and that the beam position stability is quite good. In our early writing experiments, we had presented the first writing result of MCC and the first stitching result of a multi column system ever reported.

As pattern density and OPC complexity grow, photomask write times on electron beam tools increase in proportion. Reducing the write time would decrease mask-making costs, but the performance of any alternative mask writer must meet all of the technical requirements on both mask and wafer. In addition, it is desirable to use existing OPC models in order to avoid the costs of developing and maintaining separate OPC models for each writer. The Sigma7500 deep-UV pattern generator provides the highest resolution available from a laser-based tool, and it has the advantage of maintaining about a 3 hour write time even as the feature count increases. In this study, the Sigma7500 and a variable shaped e-beam (VSB) tool are compared on 65nm metal1 and via1 layers. In the first phase, the Sigma pattern positioning was matched to a SMIC reference grid and a registration value of 10 nm (3s) was achieved with scales removed. In the second phase, M1 and V1 masks were printed with both laser and e-beam writers using the same pattern data and compared on CD uniformity, linearity and proximity. The Sigma7500 met all of the photomask requirements for these layers. The masks were then printed on wafers and the wafer data was evaluated. The results were comparable to those for the e-beam masks and were within the requirements, indicating that the Sigma7500 can handle these layers without the need to revise the e-beam mask OPC models.

The requirement for image placement accuracy on photomask has been rising. The ITRS road map says that we need to achieve 4.3nm accuracy in 2012 for HP 36nm device with single exposure process, further more we must achieve 3.0nm accuracy if double patterning process is selected. Fig.1 shows the today's performance of image placement accuracy. Some sample photomasks which have same pattern shape are produced during 3 months, and the mask to mask overlay accuracy of them was measured. The average of them was 3.6nm. This data shows the possibility to achieve the accuracy of photomask for HP 36nm devices. The image placement accuracy of actual device pattern during same period is showed in Fig.2. The image placement accuracy of actual device pattern is worse than that showed before. We categorized these data according to the pattern density, low density pattern and the high density pattern. The density of the test pattern is categorized into very low density pattern. The results are showed in Fig.3. We can see the degrading of image place accuracy according to the pattern density. This degrading of image placement accuracy is caused by resist charging effect. In photomask production process, electron beam writer is mainly used as lithography tool. Each pattern on photomask is formed by step by step exposure of electron beam. The surface of resist film will be charged with exposed electron beam, and electric field will be generated around that charged area. So the orbit of electron beam for next exposure will be bended by the electric field which generated by previous beam shot, and image placement accuracy will degrade. To achieve the demanded image placement accuracy, we need to remove the error caused by this phenomenon. We researched in resist charging effect for correcting it, and we studied that this phenomenon have so complex feature. After that we tried to research in it on EBM-7000, newly developed electron beam writer, and we found out the reduction of the image placement error caused by the resist charging effect on EBM-7000.

We report the development of Mask-LMC for defect printability evaluation from sub-200nm wavelength mask inspection images. Both transmitted and reflected images are utilized, and both die-to-die and die-to-database inspection modes are supported. The first step of the process is to recover the patterns on the mask from high resolution T and R images by de-convolving inspection optical effects. This step uses a mask reconstruction model, which is based on rigorous Hopkins-modeling of the inspection optics, and is pre-determined before the full mask inspection. After mask reconstruction, wafer scanner optics and wafer resist simulations are performed on the reconstructed mask, with a wafer lithography model. This step leverages Brion's industry-proven, hardware-accelerated LMC (Lithography Manufacturability Check) technology1. Existing litho process models that are in use for Brion's OPC+ and verification products may be used for this simulation. In the final step, special detectors are used to compare simulation results on the reference and defect dice. We have developed detectors for contact CD, contact area, line and space CD, and edge placement errors. The detection result has been validated with AIMS^TM.

Inspection of aggressive Optical Proximity Correction (OPC) designs, improvement of usable sensitivity, and reduction of cost of ownership are the three major challenges for today's mask inspection methodologies. In this paper we will discuss using aerial-plane inspection and wafer-plane inspection as novel approaches to address these challenges for advanced reticles. Wafer-plane inspection (WPI) and aerial-plane inspection (API) are two lithographic inspection modes. This suite of new inspection modes is based on high resolution reflected and transmitted light images in the reticle plane. These images together with scanner parameters are used to generate the aerial plane image using either vector or scalar models. Then information about the resist is applied to complete construction of the wafer plane image. API reports defects based on intensity differences between test and reference images at the aerial plane, whereas WPI applies a resist model to the aerial image to enhance discrimination between printable and non-printable defects at the wafer plane. The combination of WPI and API along with the industry standard Reticle Plane Inspection (RPI) is designed to handle complex OPC features, improve usable sensitivity and reduce the cost of ownership. This paper will explore the application of aerial-plane and wafer-plane die-to-die inspections on advanced reticles. Inspection sensitivity, inspectability, and comparison with Aerial Imaging Measurement System (AIMSTM[1]) or wafer-print-line will be analyzed. Most importantly, the implementation strategy of a combination of WPI and API along with RPI leading-edge mask manufacturing will be discussed.

Non-uniformity in reticle CDs can cause yield loss and/or performance degradation during chip manufacturing. As a result, CD Uniformity (CDU) across a reticle is a very important specification for photomask manufacturing. In addition the photomask CDU data can be used in a feedback loop to improve and optimize the mask manufacturing process. A typical application is utilizing CDU data to adjust the mask writer dose and compensate for non-uniformity in the CDs, resulting in improved quality of subsequent masks. Mask makers are currently using the CD-SEM for data collection. While the resolution of SEM data ensures its position as the industry standard, an output map of CDU using the reticle inspection tool has the advantage of denser sampling over larger areas on the mask. High NA reticle inspection systems scan the entire reticle at high throughput, and are ideally suited for collecting CDU data on a dense grid. In this paper, we describe the basic theory of a prototype reticle inspection-based CDU tool, and results on advanced memory masks. We discuss possible applications of CDU maps for optimizing the mask manufacturing process or in adjusting scanner dose to improve wafer CD uniformity.

At the most advanced technology nodes, such as 45nm and below, aggressive OPC and Sub-Resolution Assist Features (SRAFs) are required. However, their use results in significantly increased mask complexity, making mask defect disposition more challenging than ever. In an attempt to mitigate such difficulties, new mask inspection technologies that rely on hardware emulation and software simulation to obtain aerial image at the wafer plane have been developed; however, automatic mask disposition based on aerial image is still problematic because aerial image does not give the final resist CD or contour, which are commonly used in lithography verification on post OPC masks. In this paper, an automated mask defect disposition system that remedies these shortcomings is described. The system, currently in use for mask production, works in both die-to-die and die-to-database modes, and can operate on aerial images from both AIMSTM and aerial-image-based inline mask inspection tools. The disposition criteria are primarily based on waferplane CD variance. The system also connects to a post-OPC lithography verification tool that can provide gauges and CD specs, which are then used in the mask defect disposition.

While photomask prices continue to increase and their lifetime continues to be shortened due to molecular contamination, it is a key issue to understand the chemical mechanism of the mask damage caused by haze problem to save fabrication cost. We show a unique method for in-situ Airborne Molecular Contamination, or AMC, measurement in the mask carrier mini-environment as well as the small volume confined under the pellicle protective film. Additionally, an ultimate solution to decontaminate the photomask and surrounding environment with a vacuum purging system shows preliminary positive results on the extension of photomask life time by elimination of the haze problem cause.

The present practice of managing reticle haze defectivity involves reticle inspection at regular intervals, coupled with inspection of print-down wafers in between reticle inspections. The sensitivity of the reticle inspection tool allows it to detect haze defects before they are large enough to print on the wafer. Cleaning the reticle as soon as the reticle inspector detects haze defects could result in a shorter reticle lifetime. Thus there is strong motivation to develop a methodology to determine what size defect on the reticle results in a printable defect on the wafer. Printability depends upon several variables in the litho process as well as whether the defect resides in a high-MEEF (Mask Error Enhancement Factor) or low-MEEF area of the die.1 Trying to use wafer inspection to identify the first appearance of haze defects may require inspector recipe settings that are not suited to a practical wafer scan. A novel method of managing such defects is to map the coordinates of the defects from the reticle onto the wafer, and apply a separate, hyper-sensitive threshold to a small area surrounding the given coordinates. With this method, one can start to correlate the size of the defects printed on the wafer to the light transmission rate from the corresponding site on the reticle scan, and thus can predict the starting point at which the haze defects on the reticle are likely to print on the wafer. The experiment described in this paper is a first step in exploring the feasibility of this method to help track the growth of nascent haze defects and optimize the timing to rework the reticles. The methodology may have extendibility to other applications in which hyper-sensitive wafer inspection at localized areas within the die would be beneficial, such as monitoring weak spots found by Optical Rule Check, Process Window Qualification, electrical test or failure analysis.

As the mask technology matures, critical printing features and sub-resolution assist features (SRAF) shrink below 100 nm, forcing critical cleaning processes to face significant challenges. These challenges include use of new materials, oxidation, chemical contamination sensitivity, proportionally decreasing printable defect size, and a requirement for a damage-free clean. CO₂ cryogenic aerosol cleaning has the potential to offer a wide process window for meeting these new challenges, if residue adder issues and damage can be eliminated. Some key differentiations of CO₂ cryogenic aerosol cleaning are the non-oxidizing and non-etching properties compared to conventional chemical wet clean processes with or without megasonics. In prior work, the feasibility of CO₂ cryogenic aerosol in post AFM repair photomask cleaning was demonstrated. In this paper, recent advancements of CO₂ cryogenic aerosol cleaning technology are presented, focusing on the traditional problem areas of particle adders, electrostatic discharge (ESD), and mask damage mitigation. Key aspects of successful CO₂ cryogenic aerosol cleaning include the spray nozzle design, CO₂ liquid purity, and system design. The design of the nozzle directly controls the size, density, and velocity of the CO₂ snow particles. Methodology and measurements of the solid CO₂ particle size and velocity distributions will be presented, and their responses to various control parameters will be discussed. Adder control can be achieved only through use of highly purified CO₂ and careful materials selection. Recent advances in CO₂ purity will be discussed and data shown. The mask cleaning efficiency by CO₂ cryogenic aerosol and damage control is essentially an optimization of the momentum of the solid CO₂ particles and elimination of adders. The previous damage threshold of 150 nm SRAF structures has been reduced to 70nm and data will be shown indicating 60 nm is possible in the near future. Data on CO₂ tribocharge mitigation, the main cause of ESD, will also be presented and application to current technology nodes discussed.

Makers and users of advanced technology photomasks have seen increased difficulties with the removal of persistent, or stubborn, nano-particle contamination. Shrinking pattern geometries, and new mask clean technologies to minimize haze, have both increased the number of problems and loss of mask yield due to these non-removable nano-particles. A novel technique (BitClean^TM) has been developed using a scanning probe microscope system originally designed for nanomachining photomask defect repair. Progress in the technical development of this approach into a manufacture-able solution is reviewed and its effectiveness is shown in selectively removing adherent particles without touching surrounding sensitive structures. Methods for generating targeted edge test particles along with considerations for removal of particles in various pattern geometries and materials are also discussed.

The mask error budget continues to shrink with shrinking DRAM half pitch and MPU gate size year by year. The ITRS roadmap calls for mask CDU to be cut in half by 2014[1]. Both mask maker and mask user must take advantage of various mask properties, OPC strategies and resolution enhancement techniques to drive improvements. Mask material selection impacts both lithographic performance and mask manufacturability. In turn mask material properties and manufacturing techniques impact our ability to meet the technology roadmap. Studies have shown the advantages of polarized light[2,3] as well as the impact of various mask materials on high NA lithography[4]. In this paper we select the recently introduced binary mask material made from a MoSi absorber called Opaque MoSi On Glass (OMOG) for comparison with the conventional 6% att. PSM and 20% att. MoSi PSM. Through simulation and wafer prints, we optimized mask feature from viewpoint of MEEF and maximum exposure latitude (EL). The MoSi att. PSMs suffer from higher MEEF, which is attributed to the negative effect of TE polarization for mask duty cycle of 50% for 50 nm half pitch and below. Therefore a lower mask duty cycle is required for att. PSM to bring the MEEF performance back to acceptable levels. Experimental results confirm simulation results. As a result of the lower mask duty cycle, the att. MoSi PSMs exhibit poor Sub Resolution Assist Feature (SRAF) printability. On the contrary, the MoSi binary mask delivers both acceptable MEEF and acceptable SRAF printing performance. Moreover, we found that the mask structure impact of OMOG to wafer CD is smallest among three masks. OMOG gives the best combination of lithographic performance and delivery compared to the MoSi att. PSMs.

Improvements in resolution of exposure systems have not kept pace with increasing density of semiconductor products. In order to keep shrinking circuits using equipment with the same basic resolution, lithographers have turned to options such as double-patterning, and have moved beyond model-based OPC in the search for optimal mask patterns. Inverse Lithography Technology (ILT) is becoming one of the strong candidates in 32nm and below single patterning, low-k1 lithography regime. It enables computation of optimum mask patterns to minimize deviations of images from their targets not only at nominal but also over a range of process variations, such as dose, defocus, and mask CD errors. When optimizing for a factor, such as process window, more complex mask patterns are often necessary to achieve the desired depth of focus. Complex mask patterns require more shots when written with VSB systems, increasing the component of mask cost associated with writing time. It can also be more difficult to inspect or repair certain types of complex patterns. Inspection and repair may take more time, or require more expensive equipment compared to the case with simpler masks. For these reasons, we desire to determine the simplest mask patterns that meet necessary lithographic manufacturing objectives. Luminescent ILT provides means to constrain complexity of mask solutions, each of which is optimized to meet lithographic objectives within the bounds of the constraints. Results presented here show trade-offs to process window performance with varying degrees of mask complexity. The paper details ILT mask simplification schemes on contact arrays and random logic, comparing process window trade-offs in each case. Ultimately this method enables litho and mask engineers balance lithographic requirements with mask manufacturing complexity and related cost.

A variety of innovations including the reduction of actinic wavelength, an increase in lens NA, an introduction of immersion process, and an aggressive OPC/RET technique have enabled device shrinkage down to the current 45nm node. The immaturity of EUV and high index immersion, have made logic manufacturers look at other ways of leveraging existing exposure technologies as they strive to develop process technology for 32nm and below. For design rules for sub-nodes from 32nm to 22nm, the need to define critical layers with double photolithography and etch process becomes increasingly evident. Double patterning can come in a variety of forms or 'flavors'. For 32/28nm node, the patterning of 2D features is so challenging that opposing line-ends can only be defined using an additional litho and etch step to cut them. For 22nm node, even line/space gratings are below the theoretical k1=0.25 imaging limit. Therefore pitch-doubling double patterning decomposition is absolutely required. Each double patterning technology has its own set of challenges. Most of all, an existing design often cannot be shrunk blindly and then successfully decomposed, so an additional set of restrictions is required to make layouts double patterning compliant. To decompose a logic layout into two masks, polygons often need to be cut so that they can be patterned using both masks. The electric performance of this cut circuitry may be highly dependent on the quality of layout decomposition, the circuit characteristics and its sensitivity to misalignment between the two patterning steps. We used representative logic layouts of metal level and realistic models to demonstrate the issues involved and attempt to define formal rules to help enable lineend splitting and pitch-doubling double patterning decomposition. This study used a variety of shrink approaches to existing legacy layouts to evaluate double patterning compliance and a careful set-up of parameters for the pitch splitting decomposition engine. The quality of the resultant imaging was tuned using double patterning aware OPC and printability verification tools.

Novel optical proximity correction (OPC) and design for manufacturability (DfM) methodology for threedimensional (3D) memory device is proposed to overcome emerging hotspot issues caused by larger process proximity effect (PPE) due to unavoidable high-aspect patterning process. To realize robust pattern formation for lithography and reactive-ion etching (RIE) processes, the following methodologies are introduced: i) OPC is carried out by using averaged or designed optics not ideal to make robust pattern formation for optical variation of exposure tool, ii) lithography compliance check (LCC) is done under the worst optical condition to detect hotspots induced by optical variation of exposure tool, and modification of layout and OPC condition is performed to remove hotspots, iii) hotspots induced by RIE process are checked by using etching simulation with empirical RIE model, and modification of layout, PPC and OPC scheme is performed to remove hotspots. In this study, it is confirmed that our proposed novel OPC and DfM methodology is promising for robust pattern formation in upcoming 3D memory device.

It has recently been reported [1] that production reticles are subject to progressive CD degradation during use and intense study is under way to try and identify the causes of it. One damage mechanism which has already been identified and quantified [2] is electric field induced migration of chrome (EFM). This can be caused by electric fields that are more than 100x weaker than those that cause ESD. Such low level electric fields can be experienced by a reticle during normal handling and processing steps, as well as coming from external sources during transportation and storage. The field strength of concern is lower than most electrostatic field meters are designed to measure and it can be difficult or impossible to measure such fields inside the cramped environment of equipment. To measure this risk a new sensor device ("E-Reticle") has been developed having the same materials of construction and form factor as a standard chrome-on-quartz reticle. It allows the electric field that a reticle would experience during normal use and handling to be measured and recorded. Results from testing of this device in a semiconductor production facility are reported, showing that certain processes like reticle washing are inherently hazardous. It also enables identification of problems with electrostatic protection measures inside equipment, such as unbalanced ionizers or poor load port grounding. The device is shown to be capable of recording electric fields in the reticle handling environment that are below the recommended maximum that is being proposed for the 2009 ITRS guidelines.

The resolution of photomask patterns were improved with a hardmask (HM) system. The system which is thin Sicompounds layer is easily etched by the hyper-thin resist (below 100nm thickness). The HM material has sufficient etching selectivity against the chrome-compounds which is the second layer chrome absorber for the phase-shifter. This hardmask layer has been completely removed during the phase-shifter etching. It means that the conventional phase-shit mask (PSM) has been made with the ultimately high-resolution without configuration changes. Below 50nm resolution of PSM was made with 90nm thickness resist on HM layer in this paper. The CD bias between a resist feature CD and a chrome feature CD was almost zero (below 1nm) in the optimized etching condition. We confirmed that the mask performances were the equal to COMS (Cr-HM on MoSi binary mask) in resolution and CD linearity. The performances of hardmask blanks will be defined by resist performance because of almost zero bias.

As technology advances, the demand for tighter photomask final flatness specifications becomes greater. Studies have shown that the process of mounting a pellicle induces the largest change in flatness in photomask fabrication. Photomask pellicles play an important role in flatness due to the many components in the mounting process. For example, pellicle frame flatness, pellicle adhesive, mounting force, mounting time, mounting orientation and mask backing shape during mount all can play a role in changing the mask shape during pellicle mount. Many of these factors have been investigated over the last several years [1][2][3][4]. Recent studies have demonstrated that the height of the pellicle frame also has a significant impact on the final flatness with lower stand off frames resulting in reduced pellicle influence on mask distortion [5]. This paper will examine the flatness influence factor as a function of mounting direction and mask backing variations. For these experiments, the same pellicle frame was remounted for each set of experiments to eliminate external pellicle frame flatness factors and to minimize the amount of data deviations. Four different types of mask backing types were selected that differed in the contact area with the mask in particular pressure points. The mask backing types consist of a border frame, 4 point pressure points, a full backing plate (quartz substrate), and a pellicle frame. In addition to using the four different types of mask backings, the pellicles were also mounted both in the vertical and horizontal directions in determining final photomask flatness. This work demonstrates that frame flatness and shape play the largest roles and mounting force, backing plate and mounting orientation have less of an effect.

As the nano-lithography technology continues to develop towards advanced generation of ArF immersion lithography, the quality of ArF EAPSM becomes the most valuable factor for worldwide Maskshop. Therefore outturn of ArF EAPMS increase continuously, and people who work in the fields of semiconductor engineering give consequence to good quality of ArF EAPSM until the EUV lithography generation. Because 300mm wafer litho-facility use higher exposure energy, wider shot field and more shots per a wafer for achieving more memory(DRAM or Flash) chips than 200mm exposure facility, photo engineer wants unchanged initial condition of mask quality(CD MTT, CD Uniformity, repeating defect, phase shift and transmittance). In other words, mask manufacturer must focus on the concept of ArF EAPSM 'life time'. We have investigated the influence grade inducing the lithographic variation between the growth of exposure energy based Haze phenomena, thin organic pellicle membrane characteristics, and we have verified that the ArF pellicle durability is one of the most important evidence for improvement of life time of ArF EAPSM. In this study, related with ArF EAPSM life time, we tried to evaluate the influence of ArF pellicle characteristic consisting of pellicle membrane transmittance strength (durability against ArF laser source) and non acid mask condition for the period of non Haze contamination without added re-pellicle → re-cleaning cycle. Metrological inspection and evaluation was conducted with several equipment and analysis including mask inspection, Scatterometer, IC, ArF laser accelerator.

A method is described to monitor etch selectivity real time in Applied Materials' advanced Tetra^TM mask etcher module. With the built-in Transmission Endpoint (TEP) capability, the transmission information for a wide range of spectra is collected. As resist thickness continues to be reduced during photomask etching process, interference fringes can be observed at selected wavelengths on the TEP spectrum. Based on known value from n & k simulation, the peak/valley positions of interference fringes can be defined. With the help from an algorithm developed to determine the corresponding time for each peak/valley position, the average resist etch rate can be obtained. In addition, the starting and ending resist thickness on the plate being etched can be calculated, so the incoming resist quality can be verified and being monitored. Combined with Cr etch rate derived from the endpoint time with plasma emission spectra, the Cr to photoresist etch selectivity can be monitored for each production plate automatically.

Optical emission represents the bulk property of plasma, which in turn can be correlated to the chamber surface condition and can be exploited for monitoring and characterizing chamber condition. This presentation demonstrates the approach of utilizing plasma optical emission spectra (OES) for the application on Applied Materials' Tetra^TM etcher chamber condition monitor. Time-resolved plasma optical emission spectra are collected with a spectrometry unit built in to the TetraTM photomask etch module. Studies on OES analysis show that information related to chamber surface condition can be correlated to the changes in emission spectrum of plasma. The effectiveness of this methodology can be verified by Cr etch rates. Results can lead to procedure development for chamber monitoring, chamber recovery and chamber seasoning applications.

For 45nm and 32nm node technology, the challenges for resolution and CD control of mask patterns become the steeper mountain path. Especially, Sub Resolution Assist Feature (SRAF) is the smallest pattern on mask and amplifies the difficulty of mask fabrication. In order to improve the resolution of fine patterns, the influence of wet processing cannot be neglected, because it causes the pattern collapsing. Wet processing of mask-making can be divided into resist development and cleaning. In this study, the root causes of pattern collapsing are investigated at each wet processing. It is confirmed that thin resist can enhance the resolution limit of resist pattern and hard-mask blank, such as OMOG: Opaque MoSi On Glass, is suitable for thinner resist under 1500A. The pattern collapsing of OMOG is compared with that of Att.PSM at the cleaning before and after Cr stripping. Mask inspection finds that pattern collapsing can be suppressed by OMOG at both cleanings. It is because OMOG has lower cleaning stress than Att.PSM due to lower aspect-ratio. This benefit is demonstrated by cleaning stress simulation. Additionally, it is found that the SRAF size of OMOG can be wider than Att.PSM by optical simulation. From these results, OMOG has much advantage of fine pattern fabrication and is the optimal blank for 32nm node and beyond.

Traditional flat etch signature was preferred in photomask plasma assisted etch process to avoid introducing undesirable signatures in final results. However, for continuous shrinking tolerance requirements, some CD issues initiated by other factors can be compensated by the etch signatures. This effect needs to be explored more accurately. As mask plasma etching occurs in a very complicated system, and to optimize dry etch process sometimes has to meet tradeoff among some parameters, proper statistical method is helpful on exploring etch signatures and predicting its complexity. Due to Cr etch process importance and complexity, in this paper we demonstrate a detailed design of experiment (DOE) with Box-Behnken design to characterize Cr etch process on EAPSM blank. The SAS software is the tool used for the experiment data analysis, exploration, modeling and optimization. It is intended to more fully describe and predict the Cr etch behavior on the mask dry etcher including etch CD global uniformity, etch CD movement (bias), isolated/dense etch CD bias and etch CD bias linearity which are currently critical mask etch specifications. The regression models of these responses and the optimal results are obtained in this experiment. Some interactions are found among these responses from the response prediction profiler in the SAS software. Etch uniformity radial error contribution is also studied in this paper.

Mask development process for 2x nm node devices needs stringent CD uniformity and CD linearity. To evaluate and improve these CD qualities, we proposed to introduce electric-field-induced-development method into proximity gap suction development system (PGSD). It is the way to develop with applying electric potential to the metallic development nozzle to stimulate the movement of hydroxide ions. In this paper, we will report the effect of electric-field-induced-development method on CD uniformity and CD linearity.

Along with the increased miniaturization of electronic devices, two-fluid cleaning technology is garnering the spotlight as a solution for the manufacturing process of Photomask. This is because it is now known that implementing energy control of the particles that are sprayed on the substrate allows cleaning of miniature patterns. However, it is not yet clear just how miniature of a pattern is cleanable with two-fluid cleaning technology. This study discusses mechanisms to miniaturize the droplets created by a two-fluid nozzle. In addition, this study also considers the impact of droplet size on pattern damage to the Photomask and speaks on the potential for applying two-fluid cleaning technology in the future.

To extend the effectiveness of photo lithography, Optical Proximity Effect Correction (OPC) and Resolution Enhancement Technique (RET) incorporate increasingly complicated process steps, handling large volumes of data. This poses a challenge for mask making with EB lithography in two areas: data transfer speed and the reliability of pattern data processed by hardware. Traditionally, JEOL's variable shaped beam mask writers used single board CPU control to save in buffer memory pattern data per field on a magnetic disk. We developed a new parallel transfer technique using a dual board CPU to enhance the data transfer speed to buffer memory. This technique improved the data transfer speed from 40 MB/sec to 80 MB/sec or higher. To insure the reliability of pattern data processed by hardware, we also devised a way to save in the hard disk the shot position, size, and dose of patterns processed in the data transfer system. We verified that the system was able to record in real time 250G shot pattern data (size and positional data of figures to be exposed).

An e-beam exposure module has been developed for an existing lithography simulator, covering aspects of e-beam inter-action with the stack, exposure of the resist by the e-beam as well as development of the resist. The goal of the simulation is to complement experimental data with insights that are difficult or impossible to obtain experimentally and to provide advanced capabilities for process optimization. Simulations are performed for an iso-dense pattern to show that in the case of 5kV acceleration voltage, a standard dose correction works well for tight beams with 5nm blur but is very challenging for 30nm beam blur. Geometric corrections will most likely be needed for a wide beam blur.

The verification of not only two-dimensional feature but also three-dimensional feature, sidewall angle (SWA), has been becoming increasingly important in NGL mask fabrication. The OMOG (Opaque MoSi on Glass) mask for ArF immersion lithography with double patterning and the reflective type mask for EUV (Extreme Ultra- Violet) lithography are especially in need of it. There are several metrology tools e.g. SEM, AFM, and Scatterometry for sidewall angle (SWA) measurement. We evaluated a new SWA measurement method using white-band width (WBW), which is equivalent to mask pattern edge width, by CD-SEM. In general, WBW correlates with SWA. It narrows as SWA becomes steeper. However, the correlation deteriorates when SWA is vertically near. This is due to the resolution limit of electron beam diameter used for measurement. We analyzed the new approach to measure SWA by CD-SEM to solve this problem. And the analysis revealed that WBW changes proportionately electron beam current value. The amount of width change depends on SWA. In this paper, we will describe the new SWA measurement method and its evaluation results as well as SWA measurement results of OMOG and EUV masks.

There is no objection that Mean to Target (MTT) and Uniformity of CD (Critical Dimension) are the most important parameters to confirm the quality of mask. So process engineer try to improve these value and metrology engineer have been struggled to provide the accurate and repeatable CD information. One of method for this goal is auto-measurement with job from pattern design. Auto-measurement helps to remove error from human and improve reproducibility of CD. The recent tools are capable to interface with marking generation program so we can measure with auto-marked job without any manual measurement. However, the enhancement design rule of lithography requests the smaller CD size and more complicated pattern layout. These worst factors can be brought about inaccurate CD result due to wrong measurement job from auto-marking program. Therefore metrology engineer have to consider more optimized auto-measurement methodology as well as to use the most advanced measurement tool. In this paper, we are focused on the CD measurement methodology which is the optimized measurement condition according to pattern shape by using the advanced marking parameter when generate auto-measurement job. In order to find the best condition, we designed test patterns containing OPC (Optical Proximity Correction) and printed on the plate. And we made two types of auto-measurement jobs. One is applied with the advanced marking parameters and the other is applied with the normal marking parameters. We measured the plate with these two jobs for each test item on LWM9000. Finally, we compared results from advanced and normal parameter and calculate how much CD can be different for each test item. Through the test result, we can find the best measurement parameter for each kinds of pattern and get more accurate CD result.

A new direct Phase-shift/Transmittance measurement tool "MPM193EX" has been developed to respond to the growing demand for higher precision measurements of finer patterns in ArF Lithography. Specifications of MPM193EX are listed below along with corresponding specifications of the conventional tool MPM193. 1) Phase-shift [3 Sigma]: 0.5 deg. (MPM193) => 0.2 deg. (MPM193EX) 2) Transmittance [3 Sigma]: 0.20 % (MPM193) => 0.04 % (MPM193EX) 3) Minimum measurement pattern width: 7.5 μm (MPM193) => 1.0 μm (MPM193EX) Furthermore, new design optics using an ArF Laser and an objective lens with long working distance allows measurements of masks with pellicles. The new method for improving the measurement repeatability is based on elimination of influence from instantaneous fluctuation in interferometer fringes by scanning two adjacent areas simultaneously. Also, MPM193EX is equipped with high-resolution and stable optics. The newly employed auto-focus system in MPM193EX accurately adjusts, by a new image processing method using high-resolution optics, the focus height that is one of the most important factors for measurements in a micro pattern.

Industry data suggests that Mask Inspection represents the second biggest component of Mask Cost and Mask Turn Around Time (TAT). Ever decreasing defect size targets lead to more sensitive mask inspection across the chip, thus generating too many defects. Hence, more operator time is being spent in analyzing and disposition of defects. Also, the fact that multiple Mask Inspection Systems and Defect Analysis strategies would typically be in use in a Mask Shop or a Wafer Foundry further complicates the situation. In this scenario, there is a need for a versatile, user friendly and extensible Defect Analysis software that reduces operator analysis time and enables correct classification and disposition of mask defects by providing intuitive visual and analysis aids. We propose a new vendor-neutral defect analysis software, NxDAT, based on an open architecture. The open architecture of NxDAT makes it easily extensible to support defect analysis for mask inspection systems from different vendors. The capability to load results from mask inspection systems from different vendors either directly or through a common interface enables the functionality of establishing correlation between inspections carried out by mask inspection systems from different vendors. This capability of NxDAT enhances the effectiveness of defect analysis as it directly addresses the real-life scenario where multiple types of mask inspection systems from different vendors co-exist in mask shops or wafer foundries. The open architecture also potentially enables loading wafer inspection results as well as loading data from other related tools such as Review Tools, Repair Tools, CD-SEM tools etc, and correlating them with the corresponding mask inspection results. A unique concept of Plug-In interface to NxDAT further enhances the openness of the architecture of NxDAT by enabling end-users to add their own proprietary defect analysis and image processing algorithms. The plug-in interface makes it possible for the end-users to make use of their collected knowledge through the years of experience in mask inspection process by encapsulating the knowledge into software utilities and plugging them into NxDAT. The plug-in interface is designed with the intent of enabling the pro-active mask defect analysis teams to build competitive differentiation into their defect analysis process while protecting their knowledge internally within their company. By providing interface with all major standard layout and mask data formats, NxDAT enables correlation of defect data on reticles with design and mask databases, further extending the effectiveness of defect analysis for D2DB inspection. NxDAT also includes many other advanced features for easy and fast navigation, visual display of defects, defect selection, multi-tier classification, defect clustering and gridding, sophisticated CD and contact measurement analysis, repeatability analysis such as adder analysis, defect trend, capture rate etc.

As a result of demand for ever decreasing of feature sizes in photomasks, inspection has become more important as a key element of manufacturing 32nm node and beyond. In order to provide a better solution for it, we have developed a new method to create programmed defects having attributes very similar to those seen in natural defects. We have named the new method as NLPD (Natural-Like Programmed Defect). One of the noteworthy features of NLPD is that it is possible to make reticles with different heights which have never been made by conventional method. Natural like defects are desirable for new inspection modes including ones using shorter wavelength and aerial plane inspection technology. These new inspection modes are equipped with recently released inspection tools. They are expected to meet the requirements which are needed by future advanced masks, and these requirements have been inadequately fulfilled with inspection tools for current generation masks. Those requirements include responding to currently dominant reticle types for 32nm node: CoG: 6% EPSM: and OMOG (Opaque MoSi On Glass). Other possible reticle types for 32nm node contain EUV, Enhancer, complex tri-tone, high transmission, and CPL. In the future, aggressive model based OPC (Optical Proximity Correction) will be typically used which include jogs, serifs, and SRAF (Sub-Resolution Assist Features) accompanying extremely small gaps between adjacent structures. When those advanced technologies are adopted, NLPD definitely contributes to making inspection more efficient and effective as evaluation method dealing with advanced inspection tools. This paper provides NLPD results with comparison of newly released inspection tools equipped with new inspection modes. The new inspection modes include hi-resolution inspection and aerial inspection which are designed to fulfill the requirements of inspection for advanced masks. These results confirm that hi-resolution inspection is suited for process development or improvement and aerial inspection is good for the volume production.

This paper describes a novel technology Variable Sensitivity Detection (VSD) for de-sensing SRAF nuisance defects in a mask inspection system. The point of our approach is to search the nearest thin-line to each defect candidate and estimate the line-width with transmitted and reflected images. The dependence of transmitted and reflected image contract on line-width is calculated with a rigorous model. This technology de-senses lineend shortening and edge roughness of SRAF patterns without compromising sensitivity to main features. Total counts of SRAF nuisance detection were drastically reduced. The VSD technology was implemented to a platform of Nuflare NPI-5000PLUS.

The cost of mask is increasing dramatically along with the continuous semiconductor scaling. ASET started a 4-year project to reduce mask manufacturing cost and TAT by optimizing Mask Data Preparation (MDP), mask writing, and mask inspection in 2006, with the support from the New Energy and Industrial Technology Development Organization (NEDO). Concerning the mask inspection, the project aims at shortening the review time after inspection. In mask inspection it approaches the limit to inspect the entire surface of a mask in the unique defect judgment algorithm without a pseudo defect. In addition, a nuisance defect including a pseudo defect increases by raising the defect detection sensitivity, and the review time after inspection increases. Mask inspection total time increases too and this will raise the mask inspection cost. Practical mask inspection can be conducted now by inputting the judgment level based on directions of design data there and by making a defect judgment level of every domestic area changeable. We can also shorten the review time by analyzing the printability on the wafer of the detected defect by the simulation, and by using the result for the defect judgment. In this report, we will show the latest research result about an inspection system technology that the defect judgment level for each domestic area can be changed, and a method to input the defect judgment level based on the pattern importance, which a device designer intended, into inspection equipment. In addition, we will show a design of the interface technology that hand over the information of the detected defect to a process simulator (wafer image simulator).

As optical lithography progresses towards 32nm node and beyond, shrinking feature size on photomasks and growing database size provides new challenges for reticle manufacture and inspection. The new TeraScanXR extends the inspection capability and sensitivity of the TeraScanHR to meet these challenges. TeraScanXR launches a new function that can dynamically adjust defect sensitivities based on the image contrast (MEEF) -- applying higher sensitivity to dense pattern regions, and lower sensitivity to sparse regions which are lithographically less significant. The defect sensitivity of TeraScanXR for Die-to-Die (DD) and Die-to-Database (DDB) inspection mode is improved by 20-30%, compared with TeraScanHR. In addition, a new capability is introduced to increase sensitivity specifically to long CD defects. Without sacrificing the inspection performance, the new TeraScanXR boosts the inspection throughput by 35%- 75% (depending upon the inspection mode) and the dataprep speed by 6X, as well as the capability to process 0.5-1 Terabyte preps for DDB inspection.

In general photomask defect repair process flow, repaired portion is evaluated with AIMS^TM and if AIMS^TM's result is out of specification, the repaired portion must be re-repaired. With shrinking pattern on device, tighter specification is required. Therefore re-repair cycle time increases and turn around time of defect repair process becomes much longer. To solve this problem, we propose a noble evaluation method that enables us to judge without using AIMS^TM with repair tool images. Images of EB repair tool is available for our propose because EB repair tool dose not give any damage on substrate and the resolution of image is quite high compared to other repair tools, FIB and Nanomachining tool. We made lithography simulation and practical experiments with line & space pattern of ArFatt. PSM with programmed defects. Consequently, we can predict AIMS-Results immediately after repair and there is a possibility to reduce the turn around time of defect repair process.

Using aerial image metrology to qualify repairs of defects on photomasks is an industry standard. Aerial image metrology provides reasonable matching of lithographic imaging performance without the need for wafer prints. Utilization of this capability by photomask manufacturers has risen due to the increased complexity of layouts incorporating RET and phase shift technologies. Tighter specifications by end-users have pushed aerial image metrology activities to now include CD performance results in addition to the traditional intensity performance results. Discussed is the computer implemented semi-automated analysis of aerial images for repair verification activities. Newly designed user interfaces and algorithms could guide users through predefined analysis routines as to minimize errors. There are two main routines discussed here, one allowing multiple reference sites along with a test/defect site on a single image of repeating features. The second routine compares a test/defect measurement image with a reference measurement image. This paper highlights new functionality desirable for aerial image analysis as well as describes possible ways of its realization. Using structured analysis processes and innovative analysis tools could lead to a highly efficient and more reliable result reporting of repair verification metrology.

One of main issues of EUV lithography is to reduce so-called shadowing effect attributed to oblique incidence of EUV light on a mask. In order to mitigate shadowing, a thinner absorber layer thickness for EUV mask is preferred. In order to realize EUV masks with thinner absorber stack, we introduced SnO film as a high absorptive material for EUV light. Thorough actual measurement of EUV reflectance and subsequent data fitting to theoretical curve, we confirmed that SnO has large k (extinction coefficient) value. As a result, SnO absorber can do with about a half thickness compared to Ta-based absorber having the same OD value. Using SnO film, we designed a binary mask consisting of SnO/CrN-buffer pattern and an att.PSM consisting of SnO/Ru-shifter pattern. SnO has also considerable transparency in the range of DUV wavelength for use of defect inspection. We confirmed both binary mask and att.PSM have low reflectance in the range of DUV wavelength even without top AR coating. The att.PSM can realize appropriate reflectance (nearby 6%) at a phase shift of 180 deg with the total patterned (SnO/Ru) thickness of below 41 nm even with 6 nm thick SiN top coating. Furthermore, we evaluated dry etched cross sectional profile of the binary mask and the att.PSM. The initial etch profiles look encouraging.

EUV exposure tools are the leading contenders for patterning critical layers at the 22nm technology node. Operating at the wavelength of 13.5nm, with modest projection optics numerical aperture (NA), EUV projectors allow less stringent image formation conditions. On the other hand, the imaging performance requirements will place high demands on the mechanical and optical properties of these imaging systems. A key characteristic of EUV projection optics is the application of a reflective mask, which consists of a reflective multilayer stack on which the IC layout is represented by the reflectivity discontinuities1. Several mask concepts can provide such characteristics, such as thick absorbers on top of a reflective multi-layer stack, masks with embedded absorbers, or absorber-free masks with patterns etched in a reflective multilayer. This report analyzes imaging performance and tradeoffs of such new mask designs. Various mask types and geometries are evaluated through imaging simulations. The applied mask models take into account the topographic nature of the mask structures, as well as the fundamental, vectorial characteristics of the EUV imaging process. Resulting EUV images are compared in terms of their process stability as well as their sensitivities to the EUV-specific effects, such as pattern shift and image tilt, driven by the reflective design of the exposure system and the mask topography. The simulations of images formed in EUV exposure tools are analyzed from the point of view of the EUV mask users. The fundamental requirements of EUV mask technologies are discussed. These investigations spotlight the tradeoffs of each mask concept and could serve as guidelines for EUV mask engineering.

Extreme Ultra Violet Lithography (EUVL) is the most leading next generation lithographic technology post ArF immersion lithography. The Structure of EUV mask differ from traditional photomask., especially backside coating. E-chuck is employed to fix the EUV mask on the scanner. Therefore a conductive film on backside of the EUV mask blank is needed. We investigated what have an influence on mask manufacturing process caused by the backside coating differed from a traditional photomask. From our experiment, at the mask fabrication process, especially RIE process to etch Ta absorber, the CD variation is occurred by electric conduction between the backside conductive coating and the absorber on the Mo/Si multi-layer. As a result, the EUV mask blank without electric conduction between the backside conductive coating and the absorber on the Mo/Si multilayer is necessary.

We constructed an extreme ultraviolet microscope (EUVM) system for actinic mask inspection that consists of Schwarzschild optics and an X-ray zooming tube. This system was used to inspect finished extreme ultraviolet lithography (EUVL) masks and Mo/Si coated substrates of ULE glass. And we have fabricated programmed phase defects on the blanks used for inspection. The EUVM was able to resolve a programmed line-pit defect with a width of 40 nm and a depth of 10 nm, and also with a width of 70 nm and a depth of 2.0 nm. However, a 75-nm-wide 1.5-nm-deep pit defect was not resolved. Also, the EUVM was able to resolve a programmed hole-pit defects with widths ranging from 35 nm to 170 nm and depths ranging from 2.5 nm to 2.2 nm. However, 20-nm-wide 1.5-nm-deep hole-pit defects were not resolved. These results agree with the simulation results perfectly. Thus, in this study, one critical dimension of a pit defects was experimentaly estimated to be a width of 20 nm and a depth of 2.0 nm.

In this paper, we will report on our experimental and simulation results on the impact of EUVL mask absorber structure and of inspection system optics on mask defect detection sensitivity. We employed a commercial simulator EM-Suite (Panoramic Technology, Inc.) which calculated rigorously using FDTD (Finite-difference time-domain) method. By using various optical constants of absorber stacks, we calculated image contrasts and defect image signals as obtained from the mask defect inspection system. We evaluated the image contrast and the capability of detecting defects on the EUVL masks by using a new inspection tool made by NuFlare Technology, Inc. (NFT) and Advanced Mask Inspection Technology, Inc. (AMiT). This tool is based on NPI-5000 which is the leading-edge photomask defect inspection system using 199nm wavelength inspection optics. The programmed defect masks with LR-TaBN and LRTaSi absorbers were used which had various sized opaque and clear extension defects on hp-160nm, hp-225nm, and hp- 325nm line and space patterns. According to the analysis, reflectivity of EUVL mask absorber structures and the inspection optics have large influence on image contrast and defect sensitivity. It is very important to optimize absorber structure and inspection optics for the development of EUVL mask inspection technology, and for the improvement of performance of EUV lithographic systems.

We evaluated a FIB-CVD (Focused Ion Beam-Chemical Vapor Deposition) process for repairing clear defects on EUV masks. For the CVD film, we selected Carbon material. Our simulation result showed that the properties of wafer-prints depended on the density of the carbon films deposited for repairing the clear defects. Especially, when the density of carbon film was higher than that of graphite the properties of the wafer-prints came out to be almost same as obtained from Ta-based absorbers. For CVD, in this work we employed typical carbon based precursor that has been routinely used for repairing photomask patterns. The defects created for our evaluation were line-cut defects in a hp225nm L/S pattern. The performance of defect repair was evaluated by SFET (Small Field Exposure Tool) printability test. The study showed that the focus characteristic of repaired region deteriorated as the thickness of the deposition film decreased, especially when the thickness went below the thickness of the absorber. However, when the deposition film thickness was same as that of the absorber film, focus characteristic was found to be excellent. The study also revealed that wafer-print CDs could be controlled by controlling the CDs of the deposition films. The durability of deposition films against the buffer layer etching process and hydrogen radical cleaning process is also discussed.

A mask patterning process based on proton multi-beam exposure in combination with Opaque-Molybdenum-Over-Glass (OMOG) hard mask blank material has been developed. As non-chemically amplified resist, HSQ has been selected. Using the IMS Nanofabrication proof of concept proton Multi Beam System which is designed for 43,000 programmable ion beams, an acceptable exposure dose of around 25μC/cm² has been determined for 10 keV protons. Assessment of the process flow has been done in terms of dose latitude, LER, LWR, CD variation, and resolution capability.

Recently, patterned media have gained attention as a possible candidate for use in the next generation of hard disk drives (HDD). Feature sizes on media are predicted to be 20-25 nm half pitch (hp) for discrete-track media in 2010. One method of fabricating such a fine pattern is by using a nanoimprint. The imprint mold for the patterned media is created from a 150-millimeter, rounded, quartz wafer. The purpose of the process introduced here was to construct a quartz wafer mold and to fabricate line and space (LS) patterns at 24 nmhp for DTM. Additionally, we attempted to achieve a dense hole (HOLE) pattern at 12.5 nmhp for BPM for use in 2012. The manufacturing process of molds for patterned media is almost the same as that for semiconductors, with the exception of the dry-etching process. A 150-millimeter quartz wafer was etched on a special tray made from carving a 6025 substrate, by using the photo-mask tool. We also optimized the quartz etching conditions. As a result, 24 nmhp LS and HOLE patterns were manufactured on the quartz wafer. In conclusion, the quartz wafer mold manufacturing process was established. It is suggested that the etching condition should be further optimized to achieve a higher resolution of HOLE patterns.

Nano-imprint lithography (NIL) has been counted as one of the lithography candidates for hp32nm node and beyond and has showed excellent resolution capability with remarkable low line edge roughness that is attracting many researchers in the industry who were searching for the finest patterning technology. Therefore, recently we have been focusing on the resolution improvement on the NIL templates with the 100keV acceleration voltage spot beam (SB) EB writer and the 50keV acceleration voltage variable shaped beam (VSB) EB writer. The 100keV SB writers have high resolution capability, but they show fatally low throughput if we need full chip writing. Usually templates for resolution pioneers needed just a small field (several hundred microns square or so), but recently requirements for full chip templates are increasing. For full chip writing, we have also started the resolution improvement with the 50keV VSB writers used in current 4X photomask manufacturing. The 50keV VSB writers could generate full chip pattern in a reasonable time though resolution limits are inferior to that with the 100keV SB writers. In this paper, we will show latest results with both the 100keV SB and the 50keV VSB EB writers. With the 100keV SB EB writer, we have achieved down to hp15nm resolution for line and space pattern, but found that to achieve further improvement, an innovation in pattern generation method or material would be inevitable. With the 50keV VSB EB writer, we have achieved down to hp22nm resolution for line and space pattern. Though NIL has excellent resolution capability, solutions for defect inspection and repair are not clearly shown yet. In this paper, we will show preliminary inspection results with an EB inspection tool. We tested an EB inspection tool by Hermes Microvision, Inc. (HMI), which was originally developed for and are currently used as a wafer inspection tool, and now have been started to seek the application for mask use, using a programmed defect template.

Many issues need to be resolved for a production-worthy model based assist feature insertion flow for single and double exposure patterning process to extend low k1 process at 193 nm immersion technology. Model based assist feature insertion is not trivial to implement either for single and double exposure patterning compared to rule based methods. As shown in Fig. 1, pixel based mask inversion technology in itself has difficulties in mask writing and inspection although it presents as one of key technology to extend single exposure for contact layer. Thus far, inversion technology is tried as a cooptimization of target mask to simultaneously generate optimized main and sub-resolution assists features for a desired process window. Alternatively, its technology can also be used to optimize for a target feature after an assist feature types are inserted in order to simplify the mask complexity. Simplification of inversion mask is one of major issue with applying inversion technology to device development even if a smaller mask feature can be fabricated since the mask writing time is also a major factor. As shown in Figure 2, mask writing time may be a limiting factor in determining whether or not an inversion solution is viable. It can be reasoned that increased number of shot counts relates to increase in margin for inversion methodology. On the other hand, there is a limit on how complex a mask can be in order to be production worthy. There is also source and mask co-optimization which influences the final mask patterns and assist feature sizes and positions for a given target. In this study, we will discuss assist feature insertion methods for sub 40-nm technology.

The data volume is increasing exponentially in mask data preparation (MDP) flows for sub-45nm technologies, but time to market drives the acceptable total turnaround time. As a reasonable response, more computing resources are purchased to address these two issues. How to effectively use these resources including the latest CPUs, high-speed networking, and the fastest data storage devices is becoming an urgent problem to solve. A detailed study is conducted in an attempt to find an optimal solution to this problem. In particular, how CPU speed, bandwidth of network connections, and I/O speed of data storage devices affect the total turnaround time (TAT) in a mask data preparation flow is researched. For a given High Performance Computing (HPC) budget and MDP flow TAT constraints, methodologies to optimize HPC resources are proposed.

We present a model-based method of generating and optimizing sub-resolution assist features. Assist feature generation is based on a focus sensitivity map derived from a cost function that minimizes the variations in the printed pattern with respect to focus change. We also demonstrate a method to generate mask-friendly SRAF polygons from the focus sensitivity map. After model-based placement, assist features and the main polygons are optimized together by moving their edge segments. One of the optimization goals is that side-lobes and assist features should not print. This is enforced by computing image on a two dimensional grid. We demonstrate the process window improvement for a contact layer example.

We compared a simulator's predictions with the critical dimension (CD) value measured on the wafer. We used sub resolution assist features (SRAF) in the experiment to keep the focus margin, the minimum size of the mask was small and comparable with the absorber's thickness. Therefore, it seems that we need a rigorous model and a variety of parameters for high prediction accuracy. We investigated the prediction error and found its behavior was not complicated. The dependence of the prediction errors was related to the space until the next feature, but the relationship was not linear; rather, it went up and down periodically like a Bessel function. This fact gave us the idea that it might be possible to improve the simulation accuracy by using a special convolution kernel but not a Gaussian function. We used a complementary kernel and tried to find a suitable shape to match the prediction error. The convolution kernel consisted of a complex number in order to represent phase change and amplitude loss. The kernel was applied to the simulator's mask plain. The results showed a significant improvement in simulation accuracy and a reduction in the route mean square (RMS) of the CD fitting error for all features with or without SRAFs. We used this model for optical proximity correction (OPC) and verified its accuracy with a printed wafer image. The range of the final CD variation of 40 nm line on the wafer was 1.9 nm, and the model also showed good agreement with the experimental two-dimensional feature shape.

We have evaluated a unified mask pattern data format named "OASIS.MASK"1 and a unified job deck format named "MALY"² for mask tools as the input data formats of the inspection tool using the mask data and the photomask produced with the 65nm design rule. The data conversion time and the data volume for the inspection data files were evaluated by comparing with the results for using the native EB data and the native job deck data. The inspection speed and the defect number of the inspection tool were also evaluated with the actual inspection tool. We have confirmed that there is no large issue in applying OASIS.MASK and MALY to the input data formats of the inspection tool and they can become the common intermediate format in our MDP flow. The detail of evaluation results will be mainly introduced in this paper.

The problem of mask cost has been highlighted recently due to the complex manufacturing process as the semiconductor node is getting smaller and smaller. It has been said that DFM methods can be useful for mask cost reduction. One of the ASET/Mask D2I target is the mask data prioritization and its effective uses for mask manufacturing issues from the viewpoints of mask DFM. The Mask D2I and STARC have been working together to build efficient data flow based on the information transition from the design to the manufacturing level. By converting design level information called as "Design Intent" to the priority information of mask manufacturing data called as "Mask Data Rank (MDR)", MDP or manufacturing process based on the importance of reticle patterns is possible. Our main purpose is to build a novel data flow with the priority information of mask patterns extracted from the design intent. In this paper, we introduce a design intent extraction flow which has been newly developed and we show the effectiveness of the fully automated MDR flow with actual chip data. In addition, we show how MDR flow can be applied to analog circuits.

Owing to reduction of LSI device pattern, verification of mask pattern after optical proximity correction, OPC, by using Litho-Simulation becomes common practice. The verification using Litho-Simulation does not only increase reliability, but also the verification time. To solve this problem, we extract error patterns and categorize them, and we review only the representative pattern of each category to save time. But further reduction of device pattern might increase the verification time. There is loose matching method to save the time, but it has a week point such that accuracy of categorization is trade-off with error pattern number to be reviewed. We tried a method of categorization referring to original pattern, CROP. The CROP method categorizes error patterns referring to original pattern extracted by the position data of the error pattern. For this reason, categorization of error patterns is accurate, and the number category of a product pattern is reduced to1/50 compared with pattern matching method, which is loose matching method with 0 nm matching size.

The category and objective of DFM production management are shown. DFM is not limited to an activity within a particular unit process in design and process. A new framework for DFM is required. DFM should be a total solution for the common problems of all processes. Each of them must be linked to one another organically. After passing through the whole of each process on the manufacturing platform, quality of final products is guaranteed and products are shipped to the market. The information platform is layered with DFM, APC, and AEC. Advanced DFM is not DFM for partial optimization of the lithography process and the design, etc. and it should be Organized DFM. They are managed with high-level organizational IQ. The interim quality between each step of the flow should be visualized. DFM will be quality engineering if it is Organized DFM and common metrics of the quality are provided. DFM becomes quality engineering through effective implementation of common industrial metrics and standardized technology. DFM is differential technology, but can leverage standards for efficient development.

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect^(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.