This PDF file contains the front matter associated with SPIE Proceedings Volume 7748, including the Title Page, Copyright information, Table of Contents, and the Conference Committee listing.

In Si-LSI industry, the variation of device characteristics has been one of the issues because of 10-year-lifetime LSI and high-yield mass production, and it has been continuously developing the several methods to mitigate and straighten out it. Currently, the local and random variation has been still the critical issue, compared to the global variation and the systematic one, because devices are so scaled down and the packing-density of devices is very high in LSI's. In FEOL, this variation leads to the performance degradation of SRAM, which consists of six transistors in small cells and works as the main memory on chip. This is because the local and random variation can cause the mismatch of pair transistors. In BEOL, the variation causes the degradation of interconnect performance and reliability, and leads to the performance degradation of many circuits. It is suggested that the main mechanism in that variation can be line edge roughness (LER) and random dopant fluctuation (RDF). Both LER and RDF are related to a lot of process technologies, such as lithography, etching, annealing and so on. In order to analyze the relationship between this variation and process technology and to reduce the variation, we should develop the new analysis methods for variations in <50nm CMOS devices and the new control methods. This paper presents the current status of variations and variation mechanisms, and discusses future requirements for the advanced CMOS-LSI.

We have been developing an actinic full-field mask blank inspection system to detect multilayer phase defects with dark field imaging. Detection probability with no false detection at full-field of a mask blank was improved, and then a probability of capturing 1.5 nm-high and 60 nm-wide defects was attained to be 100 %. A mask blank was inspected, and a small native defect with its top dimensions of 1.1 nm in height and 20 nm in width was successfully detected. The bottom dimensions of the smallest two defects were estimated with simulation so that the experimental and simulated signal intensities could be correlated. Using the estimated bottom dimension, the defects were found to impact on CD of 22 nm L/S pattern. Assuming that the bottom dimension was the same as the top dimension, CD variation due to the defects was found to be approximately half of those of the estimated bottom dimension. This means that some internal structure within the defect is a key factor in the estimation of impact on wafer. The detection probability improvement also attained 100% detection of the both defects.

Photo-induced defect for optic mask mainly depends on the surface residual ions coming from cleaning process, pellicle outgassing, or storage environments. Similar defect for EUV mask triggered by accumulated photon energy during photolithography process has drawn interest recently but this defect is somewhat different from normal photo-induced defect for optic mask. The photo-induced defect for EUV mask is known to be created by the chemical deposition of Carbon atoms originating from cracking of hydrocarbons by EUV light and secondary electrons on capping layer. It is very likely that Carbon contamination would be dominant under normal EUV exposure condition. On the other hand, it is expected that another kind of photo-induced defects would rise to surface under controlled environment where Carbon contamination growth is severely suppressed. We may have to understand the behavior of surface residual ions under EUV light in order to cope with another probable EUV photo-induced defect. In this paper, we will investigate whether surface ions remaining after cleaning process like sulfate or ammonium ions would create printable defects or decompose into evaporable species under EUV light. In case they create certain defects on mask surface, their effect on EUV reflectivity and absorber pattern CD variation will be also examined. Finally, improved cleaning process to impede photo-induced defect creation on EUV mask will be introduced.

When a thinner absorber mask is applied to EUVL for ULSI chip production, it becomes essential to introduce EUV light-shield border in order to suppress the leakage of EUV light from the adjacent exposure shots. Thin absorber mask with light-shield border of etched multilayer adds to the process flexibility of a mask with high CD accuracy. In this paper, we demonstrate the lithographic performance of a thin absorber mask with light-shield border of etched multilayer using a full-field exposure tool (EUV1) operating under the current working condition of EUV source.

This paper employs rigorous electromagnetic field (EMF) solvers to investigate the printing behavior of EUV multilayer defects. A compression model is applied to compute the defect induced deformation of the multilayer. A fully rigorous Waveguide method is used to simulate the light diffraction from the defective EUV mask. This fully rigorous method is compared with two other methods: A decomposition method combined with the Waveguide algorithm and a hybrid method which computes the multilayer with an analytical method based on the Fresnel-formulas and the mask absorber with a finite-difference time-domain (FDTD) algorithm. Cross sections and the critical dimensions (CD) of the printed wafer features are evaluated by the application of a threshold model to the computed aerial images. The printability of the multilayer defects and their impact on the CD of printed absorber features are investigated versus the defect position, size and other parameters of the defect model. Finally, the influence of the mask absorber properties on the defect-induced CD variation is investigated. It is shown that the printability of the defect depends on the absorber properties.

Two types of blanks, EUV A and EUV B, are the leading EUV blanks contenders. They are evaluated and compared with OMOG blank for their suitability as a photomask blanks. For defect inspection evaluation, contrast for pattern image and sensitivity for detection were evaluated using the newly developed inspection tools. With these tools, it is learnt that the sensitivity varies according to a set of conditions. For repair performance evaluations, EUV mask was assessed through E-beam repair tools, those that are most widely used. The results on both types of masks demonstrate good repair shape that is almost same quality as repair on OMOG mask. Moreover, under the two types of repair conditions used in this study, no degradation on pattern was found for the optimized condition as result of repair work.

Data and simulation results characterizing the capability of a DUV system to inspect EUV mask blanks and substrates are reported. Phase defects and particles on multilayer (ML) surfaces, ARC-coated absorber, and substrate material are considered. Phase defects on a quartz substrate surface are shown. The principle of phase detection is described. Results demonstrating the Teron 600's readiness for meeting 32nm hp requirements for bump / pit phase defect detection are shown. Simulations show that the 22-nm node requirement for phase defect detection should be met, assuming a reduction in the multilayer roughness. Preliminary data on the sensitivity of SiO₂ sphere detection on ML and quartz are reported. Simulation results show relative sensitivities for detecting SiO₂ spheres of different diameters on various EUV materials.

Bit patterned media (BPM) is a candidate for high-density magnetic recording. One of the critical issues concerning high-density BPM is a fine pattern drawing process for an etching mask. A self-assembled polymer is a solution for the fine etching mask material realizing a density of more than several Tb/in². The remaining issue concerning the self-assembled mask is servo pattern formation with the self-assembled dots. This paper reports fabrication of a ridge-and-groove servo pattern with arrays of 35nm-pitch self-assembled CoPt magnetic dots and signal properties of the servo pattern are estimated. Dot size and alignment was not uniform in the servo pattern because of the deviation of the guide width and the taper at the guide edge. This feature will result in a distorted servo signal profile. However, the numerical estimation based on the fabricated servo patterns revealed that the linearity of the position error signal was fairly good. The distortion in waveform does not degrade the phase information of the servo signal, provided the guide is positioned with high precision. Thus the ridge-and-groove servo is suitable for self-assembled bit patterned media.

Imprint lithography has been shown to be an effective technique for the replication of nano-scale features. Acceptance of imprint lithography for manufacturing will require a demonstration of defect levels commensurate with cost-effective device production. This work summarizes the results of defect inspections of hard disks patterned using Jet and Flash Imprint Lithography (J-FIL^TM). Inspections were performed with optical based automated inspection tools. For the hard drive market, it is important to understand the defectivity of both the template and the imprinted disk. This work presents a methodology for automated pattern inspection and defect classification for imprint-patterned media. Candela CS20 and 6120 tools from KLA-Tencor map the optical properties of the disk surface, producing highresolution grayscale images of surface reflectivity and scattered light. Defects that have been identified in this manner are further characterized according to the morphology. The imprint process was tested after optimizing both the disk cleaning and adhesion layers processes that precede imprinting. An extended imprint run was performed and both the defect types and trends are reported.

Photomask flatness and image placement specifications for advanced technology masks are becoming more stringent. Therefore, it is important to understand the various factors that affect final photomask flatness due to the direct impact it has on image placement. Past studies have demonstrated that final photomask flatness can be controlled by modifying the mounting process of photomask pellicle as well as changing the pellicle material itself [1][2][3][4]. In particular, our previous results demonstrate the ability to successfully eliminate data deviations by remounting the same pellicle for each experiment. This paper focuses on the relationship between mounting pressure and time on final photomask flatness. Our initial results indicate that mounting time has minimal influence on final photomask flatness; however, final photomask flatness is greatly impacted by varying mounting pressure. Finally we explore the relationship between the final photomask flatness and the image placement for post pellicle mounting onto the photomask.

The miniaturization of pattern size on photomask is advanced year by year. It becomes more important to improve Line Edge Roughness (LER) and resolution because of their impacts on lithography performances. When miniaturization is advanced, high sensitivity inspection is also indispensable. Therefore, LER becomes the key factor to reduce the nuisance defect for high sensitivity mask inspection. Basically, LER originates from resist materials and EB writer. If resist pattern LER is good, final pattern LER can be good too. One of the easiest solutions for LER is using thick resist. Thick resist can vertically smooth down the LER. However, it deteriorates resolution due to the high aspect-ratio. Another solution for LER is using low sensitivity resist. Low sensitivity resist needs many electron exposures by EB writer. Therefore, electronic density of EB pattern increases and pattern edge becomes clear. However, it deteriorates throughput, which is essential to production. Only by mask resist, it is difficult to satisfy all items, that is mask LER, resolution and throughput. In this study, the improvement of LER without deterioration of resolution is tried by dry etching process. It is found that remaining resist after Cr etching has its limitation for mask LER. And Cr over etching and source power of Cr and MoSi etching are effective factors for mask LER. On the basis of these results, the optimal etching process is determined. It is confirmed that mask LER can be improved without deterioration of resolution by the optimal etching process.

The optical performance stability of a photomask is one of the most critical factors in the photolithography process and stringent specifications create greater challenges with each advancing technology node. Throughout its lifetime, a photomask is exposed to a variety of cleaning cycles. It is essential that the integrity of the mask is preserved throughout each of these processes. Standard mask cleaning treatments include surface preparation with 172nm VUV for better wetting, organic resist/particle removal with aqueous ozone (DIO₃) and residual ion removal for haze control. However, high energy radiations from 172nm VUV have been reported to cause overlay shift and wet oxidizing chemistries adversely affect mask CD and optical properties, ultimately influencing lithography performance. Previously, HamaTech APE successfully demonstrated an advanced cleaning method using photolyzed DIO₃ with minimal metal layer damage. In this paper, performance of different media under the UV photolysis effect is explored for various steps in the cleaning process. Photolyzed DI water based surface preparation of photomask under atmospheric conditions without any overlay shift is demonstrated. Alternative chemicals with higher photolysis rates are explored for resist stripping applications. Phase/Transmission and CD change on a PSM (Phase Shift Mask) are compared between regular and modified processes. Potential improvements in residual ion removal using combination of radiation and hot DI water are also presented.

Since introduction of 193nm exposure wavelength, the haze formation becomes a serious challenge especially at mask used for big number of exposures. Several compounds present in air as low concentration contaminants are leading to haze building. Well understood is the sulphate based haze formation, however, still causing significant losses and demanding for re-cleaning of the mask during mask life time. There are plenty of publications taking different approaches to reduction of the final sulphate concentration on the mask and reduction of the use of sulphuric acid during the mask manufacturing. Beside traditional process as hot water extraction, UV exposure, baking, IR exposure at vacuum, Ammonia solution treatment more exotic method were published as surface treatment preventing migration of the sulphate ions on mask surface. The number of exposures till haze crystals growth prevents further use of the mask is not solely dependent on the sulphate concentration on the freshly manufactured mask. Additional factors as storage and use conditions are significantly influencing the period till re-clean of the mask is needed. In this work we try to assess above mentioned approaches and provide rough estimate of their limits.

A developing reality with advancing DUV femto-second pulsed laser repair of advanced photomasks after pelliclization is a significant operational cost savings. This economic advantage comes from the elimination of a previously critical inspection step before mounting the pellicle on the mask. The laser repair processes developed allow reduce the number of times masks are cycled through mask inspection tools and prevent recontamination of the mask surface due to handling during and after the inspection before pelliclization. The latter would require, without effective through-pellicle repair, removal of the pellicle, repair and/or reclean, then re-inspection and re-pelliclization of the mask (assuming success with the first cycle of repair and/or reclean). Meanwhile, the cost and lack of feasibility for this additional process both increase the investment in the mask while at the same time bringing it closer to being completely scrapped. Recently developed processes that allow for effective through-pellicle laser repair on advanced photomask technologies (sub 65 nm node) are reviewed, that have economic advantages and also make the repair of lower-end (and higher volume) photomasks significantly more profitable to the typical mask maker.

In 2009 substantial experience was obtained with projection electron and ion multi-beam test systems providing 43-thousand programmable beams of 12.5 nm beam size. Grey scale and redundancy exposure was demonstrated with 20 nm hp resolution. The results were in excellent agreement with design and expectations. Based on this experience, an electron-optical column for an electron Mask Exposure Tool (eMET) has been designed for the 16 nm hp technology node and below. An advanced Aperture Plate System (APS) is being developed for eMET providing ca. 256-thousand programmable 50 keV e-beams of 20nm and 10nm beam size. The development starts with the realization of a proof-of-concept system (eMET POC) for which a low cost but very precise vacuum stage will be made available. The potential eMET writing speed as governed by APS and data path speed is > 40 cm²/h when writing with 20nm-sized beams on a 10 nm grid, and > 10 cm²/h when writing with 10nm-sized beams on a 5 nm grid.

Lithography technologies promising for the half pitch (HP) 32 nm generation include 193 nm immersion with water, extreme ultraviolet lithography (EUVL), and nano-imprint lithography (NIL). Among these, 193 nm immersion with water is considered a mainstream for hp 32 nm device fabrication in terms of performance and device production costs. Meanwhile, according to the International Technology Roadmap for Semiconductors (ITRS) 2009, the optical masks for hp 32 nm devices need to meet extremely strict requirements; for example, an image placement accuracy of 3.8 nm (2.7 nm for double patterning), and CD uniformities of 1.5 nm (isolated lines) and 2.4 nm (dense lines). To meet these accuracy requirements, we have developed JBX-3200MV, a variable shaped beam mask writer featuring an accelerating voltage of 50 kV and a current density of 70 A/cm². For this new writer, we developed a new digital-to-analog converter (DAC) amplifier designed to reduce noises input to electron beam optics components such as the main and sub positioning deflectors and the beam shaping deflectors. The stage and exposure chambers were enhanced in rigidity to reduce mechanical noises. The position of the stage is measured by laser devices with a finer resolution of 0.15 nm, and the measured results are fed back to the beam position. In addition, data transfer speed and proximity correction speed were improved to handle larger data volumes. Our exposure test results demonstrate that the new lithography system, installed at the leading-edge mask production facility, achieved the hp 32 nm mask accuracies required by the ITRS 2009.

As semiconductor features shrink in size and pitch, the extreme control of CD uniformity and MTT is needed for mask fabrication with e-beam lithography. And because of huge shot density of data, the writing time of e-beam lithography for mask fabrication will be increased rapidly in future design node. The beam drift caused by charging of optic system and current density drift can affect the beam size, position and exposure dose stability. From the empirical data, those are the function of writing time. Although e-beam lithography tool has the correction function which can be applied during writing, there are remained errors after correction which result in CD uniformity error. According to the writing time increasing, the residual error of correction will be more important and give the limit of CD uniformity and MTT. In this study, we study the beam size and exposure dose error as a function of time. Those are mainly caused by charging and current density drift. And we present the predicted writing time of e-beam lithography below 32nm node and estimate its effect on CD control error. From the relation between writing time and CD control error, we achieve the limit of CD uniformity with e-beam mask writer. And we suggest the method to achieve required CD uniformity at 22nm node and beyond.

The extension of optical projection lithography beyond the 22-nm node requires strong Resolution Enhancement Techniques (RETs) such as aggressive Optical Proximity Correction (OPC), computational lithography, double patterning and others. These strong RETs make photomask patterns more complex, photomask specifications tighter, and the metrology demands greater. Currently Photomask Critical Dimension (CD) and image placement are characterized by measuring a few hundred points sampled across the entire mask area; however more sampling points in active patterns or even full area inspection will be required to support strong RETs. Inspection tools are developing capabilities in CD and Image placement mapping. Although measurement precision, resolution, stage position accuracy and other metrology functions would be inferior to a metrology tool, the sampling is intrinsically larger, including the entire active area. The inspection tool could satisfy the large sampling requirements while a subset of patterns could be measured with traditional CD and Image placement metrology tools with the required precision. Therefore the fusion of metrology and inspection tools would satisfy both the full area CD and Image placement measurement: coarse inspection in CD and Image placement with the inspection tool and verification with metrology tools measuring the CD and/or Image placement errors identified by the inspection tool. Next generation metrology tool and inspection tools also leverage the aerial plane image for inspection and metrology. This is important since the strong RETs generate very complex patterns that are difficult to measure reliably with a CDSEM. The aerial image retains a simple shape though photomask patterns are extremely complex. Using aerial image metrology techniques simplifies CD measurement on complex patterns and enables measurement of lithographically critical features. Measuring what matters most of wafer could lead to relaxed mask CD specifications and permit more sophisticated CD correction methods.

Double Patterning Lithography (DPL) for next-generation wafer exposure is placing greater demands on the requirements for pattern placement accuracy on photomasks: the DPL mask pair must now meet the pattern placement specifications that a single mask was required to meet in previous generations. As a result, each mask in the mask pair must individually conform to much tighter mask registration specs. Minimizing all sources of systematic overlay error has become critical. In addition, the mask-to-mask overlay between the two masks comprising the DPL pair must be measured-a methodology shift from the current practice of referencing mask registration error only to design data. Characterizing mask-to-mask overlay error requires the ability to measure pattern placement errors using in-die structures on reticle pairs. Today's analysis methods do not allow for comparison of registration maps based on different site locations. This gap has created a lack of information about the true overlay impact of mask-to-mask registration errors on masks with few or no common features. A new mask-to-mask overlay analysis method is demonstrated that provides new flexibility for mask-to-mask comparison. This new method enables mask manufacturers to meet fab requirements for DPL, and it enables semiconductor manufacturers to verify if overlay deviations are within acceptable limits.

SEMATECH has identified the need for a high resolution photomask pattern placement metrology tool to support SEMATECH member companies' photomask production as well as research and development work. Performance measures of the tool are driven by double exposure/double patterning approaches that will help extend 193nm lithography according to International Technology Roadmap for Semiconductors (ITRS) requirements. Based on its superior and extendable concept, PROVETM, a new photomask registration and overlay metrology system from Carl Zeiss SMS, was chosen as the winning proposal for tool development by an evaluation team of mask makers and SEMATECH member companies. The scope of the PROVETM project is to design and build a photomask pattern placement metrology tool to serve the 32 nm node and below. The tool is designed for 193 nm illumination and imaging optics, which enable at-wavelength metrology for current photomask needs. The optical beam path offers registration and critical dimension (CD) metrology using transmitted or reflected light. The short wavelength together with an NA of 0.6 also allows sufficient resolution even at working distances compatible with the use of pellicles, hence enabling the tool for qualification of final masks. The open concept together with the use of 193 nm wavelength enables a higher NA for pellicle-free applications, including extreme ultraviolet (EUV) masks. This paper reports the current status of PROVETM, highlighting its resolution capabilities while measuring production features as well as key registration specifications.

The Critical Dimension Uniformity (CDU) specification on photo-mask is getting increasingly tighter which each successive node. The ITRS roadmap for optical masks indicates that, the CDU (3 sigma) for dense lines for binary or attenuated phase shift mask is 3.4nm for 45nm half-pitch (45HP) node and will go down to 2.4nm for 32HP node. The current variability in mask shop processes results in CDU variation across the photo-mask of ~2-3nm. Hence, we are entering in a phase where the mask CDU specification is approaching the limit of the capability of the current POR (process on record). Hence, mask shops have started exploring more active mechanisms to improve or compensate for the CDU of the masks. A typical application is in feeding back the CDU data to adjust the mask writer dose and compensate for non-uniformity in the CDs, resulting in improved quality of subsequent masks. Another option is to feed the CD uniformity information forward into the wafer FAB and adjust the scanner dose to correct for reticle non-uniformity. For these purposes mask makers prefer a dense measurement of CDs across the reticle in a short time. Mask makers are currently using the CD-SEM tool for data collection. While the resolution of SEM data ensures its position as the industry standard, an output map of CDU from a reticle inspection tool has the advantage of denser sampling over larger areas on the mask. High NA reticle inspection systems scan the entire reticle at high throughput, and are ideally suited for collecting CDU data on a dense grid. In this paper, we describe the basic theory of a new, reticle inspection-based CDU tool, and results on advanced memory masks. We discuss possible applications of CDU maps for optimizing the mask manufacturing and wafer production processes.

The demand for aggressive image placement (IP) accuracy and the CD uniformity of Mask is being increasingly accelerated by DPT deployment. It is becoming feasible to improve CD accuracy, by feeding back CD information to mask writer, or by feed-forwarding CD information on a mask to lithography scanner. Moreover, it is also becoming realistically available to improve position accuracy, by feeding back Mask IP information to mask writer. It was necessary to prepare certain special pattern to measure CD and IP, and to measure the pattern with a conventional metrology tool, requiring long measurement time in the event the number of measurement points is large as can be seen with the lately emerging advanced masks. We are developing a function to acquire both CD information and IP information on the mask at the same time the image data acquired are analyzed by mask defect inspection equipment, so that no special pattern may be needed and no additional measurement time is required. We will report on the result of obtaining IP data of a product-like pattern using this function.

Traditional patterned mask inspection has been off-wavelength. For the better part of the past 25years mask inspection systems never adhered to the wavelength of the exposure tools. While in the days of contact and proximity printing this was not a major issue, with the arrival of steppers and scanners and the slow migration from 436nm, 405nm, 365nm and 248nm to ultimately 193nm, on-wavelength inspection has become a necessity. At first there was the option with defect and printline review using an at-wavelength AIMS tool [Fig 1], but now the industry has moved towards Patterned Mask Inspection to be at-wavelength too. With ever decreasing wavelength, more and more materials have become opaque, and especially the 266/257nm inspection to 193nm printing wavelength has proven to be a reliability issue. The industry took a major step forward with the adoption of at-wavelength aerial inspection, a paradigm shift in mask inspection, as it uses a hardware emulation to parallel the scanner's true illumination settings [Fig 2]. The technology has found wide-spread acceptance by now, and 19xnm inspection is now the industry standard.

At 32nm node and beyond, a common approach in defect inspection (high resolution inspection mode) to cope with aggressively OPCed mask patterns including SRAFs, is the utilization of small pixel size inspection. In fact the sensitivity is increased by using smaller pixel size for the high resolution inspection, but at the same time the throughput of the defect inspection tool falls. In this paper, we propose that one of the solutions to improve inspection throughput is pixel migration. KLA-Tencor's TeraScan[1] XR improves SNR (Signal to Noise Ratio) for higher sensitivity as comparison with TeraScanHR, so that pixel migration is possible. For tool performance confirmation, TeraScanXR has improved in defect sensitivity and SRAF MRC (Mask Rule Check) limitation as comparison with TeraScanHR. We confirmed that pixel migration is one of the solutions to control inspection time growth of next generation mask. For printability simulation of pixel migration, we confirmed the possibility of Brion's Mask-LMC[2] (Mask-Lithography Manufacturability Check) defect classification by lower SNR image. For experiment to achieve higher sensitivity, we confirmed defect sensitivity improvement with experimental condition and considered the model to achieve higher sensitivity.

Wafer lithography process windows can be enlarged by using source mask co-optimization (SMO). Recently, SMO including freeform wafer scanner illumination sources has been developed. Freeform sources are generated by a programmable illumination system using a micro-mirror array or by custom Diffractive Optical Elements (DOE). The combination of freeform sources and complex masks generated by SMO show increased wafer lithography process window and reduced MEEF. Full-chip mask optimization using source optimized by SMO can generate complex masks with small variable feature size sub-resolution assist features (SRAF). These complex masks create challenges for accurate mask pattern writing and low false-defect inspection. The accuracy of the small variable-sized mask SRAF patterns is degraded by short range mask process proximity effects. To address the accuracy needed for these complex masks, we developed a highly accurate mask process correction (MPC) capability. It is also difficult to achieve low false-defect inspections of complex masks with conventional mask defect inspection systems. A printability check system, Mask Lithography Manufacturability Check (M-LMC), is developed and integrated with 199-nm high NA inspection system, NPI. M-LMC successfully identifies printable defects from all of the masses of raw defect images collected during the inspection of a complex mask. Long range mask CD uniformity errors are compensated by scanner dose control. A mask CD uniformity error map obtained by mask metrology system is used as input data to the scanner. Using this method, wafer CD uniformity is improved. As reviewed above, mask-litho integration technology with computational lithography is becoming increasingly important.

Computational spacer patterning technology (SPT) has been developed for the first time to address the challenges concerning hotspots and mask specifications in SPT. A simulation combined with a lithography, etching and deposition model shows the strong correlation of 0.999, 0.993, 0.980 with the experimental critical dimension (CD), mask error-enhancement factor (MEEF) and defect printability through a series of spacer processes, respectively. Furthermore, a design for manufacturability (DfM) flow using computational SPT can find hotspots caused by spacer patterning processes as well as those caused by lithography process and help designers make the circuit layout more robust. Besides, a newly defined MEEF and defect printability, which are primary metrics for mask specification, can be predicted so accurately by using computational SPT that the new scheme to determine appropriate mask specifications is shown to be feasible under the spacer patterning process condition. Thus, computational SPT is found to be promising for addressing the challenges concerning hotspot removal and mask specification in the upcoming 20-30nm node and beyond.

In this paper the co-optimization of the source, mask, and design is discussed. In particular the printing of the pdBRIX logic templates and SRAM cell is investigated through Tachyon SMO for the contact and metal 1 layer. Both the SRAM and pdBRIX logic templates were designed for the 22nm logic node with a 40nm half-pitch. The source and mask were optimized for an ASML /1950 at maximum NA of 1.35 and with FlexRay illumination. The use of pdBRIX logic templates are designed on a regular fabric consistent with the SRAM to enable process window improvement as well as faster convergence of SMO with the desired effect of reducing the lithographic process development time. To this end, various feedback loops in the design and lithography co-optimization are considered. All these feedback loops were eliminated by studying both the SRAM layout with random logic created from pdBRIX templates. One feedback loop of insufficient process window (PW) for the contact layer is corrected by using a bright field mask and negative process which increases the PW area by three times. The improper coloring of a contact hole layer through double patterning is found through SMO, and corrected by modifying the color scheme. A redesign of the SRAM while preserving the area of the SRAM cell is suggested by SMO in which the redesign improves the PW by 19.5%. Finally, we discuss the improvement in PW for simultaneous SMO on pdBRIX logic and SRAM.

As optical lithography feature size shrinks further, Resolution Enhancement Technologies (RETs) are pushed more aggressively and often have to be considered simultaneously. In this work, we explored a point-source approach for source-mask optimization (SMO) for use with complex low K1 mask patterns. The method consists of three steps: 1). optimizing the source by computing the image log slope (ILS) at multi-critical mask locations. 2). Using the optimized source to correct the mask for the edge placement error (EPE) utilizing standard OPC software. 3). Repeat 1) and 2) until the merit function reaches a certain condition. The image simulations were carried out by a physical model based lithography simulation where the resist process effect and the rigorous topography mask model are included. The process windows and the 3D resist profiles are simulated and used for lithography verifications. The motivation of the study is to explore the capacity of physical model based lithography process simulation software for SMO. We aim to find a simple approach for the determination of the best source shape for complex mask patterns. The simulation results demonstrate that the current commonly-used off-axis illumination shapes can be further optimized by considering multiple locations of a complex mask patterns.

The contact layer for the 22 nm logic node faces many technological hurdles. Even using techniques such as multiple-exposure patterning and 193 nm immersion, it will be difficult to achieve the depth of focus and CD uniformity required for 22 nm production. Such difficulties can be mitigated by recent advances in Inverse Lithography Technology (ILT). For example, circular main features combined with complex curvilinear assist features can provide superior CD uniformity with the required depth of focus, particularly for isolated contacts. However, such a solution can lead to long mask write times, because the curvilinear shapes necessitate a higher shot count induced by inefficient data fracturing, even without considering the circular main features. The current approach is to Manhattanize the curvilinear features resulting in a nearly equivalent image quality on the wafer; but a further reduction in mask write times could help lower costs. This paper describes a novel mask-writing method that uses a production e-beam mask writer to write main features as circles, with curvilinear assist features, while reducing shot count compared to traditional Manhattanized masks. As a result the new method makes manufacturing of ideal ILT-type masks feasible from a technical as well as from an economic standpoint. Resist-exposed SEM images are presented that validate the new method.

The metal 1 layer for the 22 nm logic node will require complex "wavy" shapes. These shapes are decorations on main features and require highly accurate printing in order to meet CD requirements. Despite attempts to reduce mask shot count by lining up the left-right or top-bottom jogs of the edges, the explosion in the required shot count is considered inevitable. This paper demonstrates a new mask writing method using model-based mask data preparation (MB-MDP), on a production e-beam mask writer. MB-MDP is a complementary technology to conventional fracturing. It incorporates e-beam simulation as an integrated part in order to determine the dose and shape of the overlapping shots to draw complex mask shapes with less shot count. Specifically, the new method writes these "wavy" metal 1 wires accurately with a significant reduction in shot count. Resist-exposed SEM images will be shown that validate the mask simulation results. A shot count comparison will be made with conventional methods.

In May 2006, the Mask Design, Drawing, and Inspection Technology Research Department (Mask D2I) at the Association of Super-Advanced Electronics Technologies (ASET) launched a 4-year program for reducing mask manufacturing cost and TAT by concurrent optimization of Mask Data Preparation (MDP), mask writing, and mask inspection [1]. Figure 1 shows an outline of the project at Mask D2I at ASET. As one of the tasks being pursued at the Mask Design Data Technology Research Laboratory we have evaluated the effect of reducing the writing shot counts by utilizing the repeating patterns, and that showed positive impact on mask making by using CP writing. During the past four years, we have developed a software to extract repeating patterns from fractured OPCed mask data and have evaluated the efficiency of reducing the writing shot counts using the repeating patterns with this software. In this evaluation, we have used many actual device production data obtained from the member companies of Mask D2I. To the extraction software, we added new functions for extracting common repeating patterns from a set of multiple masks, and studied how this step affects the ratio of reducing the shot counts in comparison to the case of utilization of the repeating patterns for single mask. We have also developed a software that uses the result of extracting repeating patterns and prepares writing-data for the MCC/CP writing system which has been developed at the Mask Writing Equipment Technology Research Laboratory. With this software, we have examined how EB proximity effect on CP writing affects in reducing the shot count where CP shots with large CD errors have to be divided into VSB shots. In this paper we will report on making common CP mask from a set of multiple actual device data by using these software, and will also report on the results of CP writing and calculation of writing-TAT by MCC/CP writing system.

The recent trend towards the shrinkage of semiconductor devices is sparking the miniaturization of photomask patterns. In turn, this has resulted in a demand for photomask cleaning technology that can eliminate contamination without causing damage, such as mask pattern collapsing and degradation of photomask optical properties. A two-fluid cleaning technology that can remove contamination without causing pattern collapsing has been gaining attention as a recent physical cleaning technology. It is now known that the advanced technology photomask cleaning is possible by controlling the diameter and the flow velocity of the liquid droplets discharged from the nozzle with two-fluid cleaning. However, it becomes impossible to explain damage only by the diameter of liquid droplets and flow velocity. In order to achieve a further improvement of the two-fluid cleaning technology, it is necessary to understand the mechanism of the damage accurately. We pay attention the study on a new parameter of damage and particle removal. The new parameter is liquid film thickness. We can rigorously describe the relation between damage and particle removal in terms of liquid droplet diameter, flow velocity and liquid film thickness by this study.

With the advancement of technology, the need to produce flatter photomasks is critical to meet strict mask manufacturing requirements. Components such as pellicle mounting techniques, pellicle frame height, frame material and adhesive all play an important role in finished photomask flatness.1-5 In particular, recent studies have shown that adhesive flexibility affect final photomask flatness significantly.6 This has motivated pellicle suppliers to optimize adhesive properties in addition to evaluate new adhesives. The paper describes the joint evaluations between IBM, Toppan and MLI, performed to determine the effect of a new MLI adhesive on the distortion of photomasks. Due to the nature of this adhesive, minimal mounting force is required. As a result of utilizing extreme low mounting pressure, benefits such as decreased flatness distortion and ease of adhesive removal are observed. The goal of this paper is to evaluate this new adhesive offering and understand the various impacts it has on pelliclized photomasks for advanced technologies.

In our paper we make an analysis of conditions for the haze development on photomask fabricated on Mo-Si containing substrates. We bring in focus cases of haze formation on masks with intrinsically very low contaminants level and being exposed in very well controlled atmosphere. There are clear indications that this new type of haze formation deviates from the generally accepted models not only with respect to the formation mechanisms but also with regard to the chemical composition of the haze products. In our analysis we speculate that the new haze type formation is closely related to the earlier reported CD degradation observed on Mo-Si masks. We also analyze the hypothesis that the ingredients for the haze formation are not only airborne contaminants and/or traces on the mask surface, but are also provided by the substrate material. Finally we present and discuss experimental data in the view of the advanced models.

Positive CAR(Chemically Amplified Resist) is exposed by electron beam and PAGs(Photo Acid Generator) of photoresist release acids. Protecting groups of exposed polymers are de-protected by the acids and unexposed polymers still keep having protecting groups. It brings out dissolution difference between exposed and unexposed photoresist in develop process. Unexposed photoresist should be remained after develop process as much as needed for patterning. However, we have observed that unexposed photoresist also can be dissolved by developer droplet with hundreds micrometer size. It resulted in photoresist pinholes after develop process and clear defects after dry etching and photoresist stripping. Firstly, we have studied the pinhole defect formation mechanism by verifying the difference between normal develop process and developer droplet. It was confirmed that the dissolution difference are caused by phase environment difference, 2 phases(solid - liquid) for normal develop process and 3 phases(solid - liquid - air) at meniscus boundary for developer droplet. It also can be explained on different dissolution rate by droplet size. Also, possible defect types by developer droplet have been reviewed through process simulation to narrow down the critical steps in develop process. Besides, some of easy accessible process parameters have been evaluated to see whether they are effective or not for clear defect reduction.

Simulation of etch profiles and the variation of critical dimensions (CD) due to the etch process is an important task in maskmaking. The tolerance to CD variation is on the order of 1 nm, while etch itself can contribute a few nm if not properly corrected. Simulations of dry etch should compliment experiments in order to shorten process development time, optimize the etch process, and predict CD variation due to dry etch. TRAVIT software is described which considers multilayered substrates, the profile of the resist before etch, nonuniformity of materials throughout the thickness, GDS pattern, and etch effects like microtrenching, dispersion, and footing. The microloading effect that defines CD dependence on the pattern is also considered. The results of simulation include etched profiles at any time during the etch process and CDs of etched and remaining patterns. A new functionality was added to simulate complex technological processes such as MEMS etch and spacer patterning technology (SPT). Results regarding pattern density dependence on CD variation in chrome for dense lines, isolated lines, and spaces are presented. Optimization of CD variation and the placement error in SPT is also described.

In order to support complex optical masks today and EUV masks in the near future, it is critical to correct mask patterning errors with a magnitude of up to 20nm over a range of 2000nm at mask scale caused by short range mask process proximity effects. A new mask process correction technology, MPC+, has been developed to achieve the target requirements for the next generation node. In this paper, the accuracy and throughput performance of MPC+ technology is evaluated using the most advanced mask writing tool, the EBM-7000¹), and high quality mask metrology . The accuracy of MPC+ is achieved by using a new comprehensive mask model. The results of through-pitch and through-linewidth linearity curves and error statistics for multiple pattern layouts (including both 1D and 2D patterns) are demonstrated and show post-correction accuracy of 2.34nm 3σ for through-pitch/through-linewidth linearity. Implementing faster mask model simulation and more efficient correction recipes; full mask area (100cm²) processing run time is less than 7 hours for 32nm half-pitch technology node. From these results, it can be concluded that MPC+ with its higher precision and speed is a practical technology for the 32nm node and future technology generations, including EUV, when used with advance mask writing processes like the EBM-7000.

As the designs of future mask nodes become more and more complex the corresponding pattern writing times will rise significantly when using single beam writing tools. Projection multi-beam lithography [1] is one promising technology to enhance the throughput compared to state of the art VSB pattern generators. One key component of the projection multi-beam tool is an Aperture Plate System (APS) to form and switch thousands of individual beamlets. In our present setup a highly parallel beam is divided into 43,008 individual beamlets by a Siaperture- plate. These micrometer sized beams pass through larger openings in a blanking-plate and are individually switched on and off by applying a voltage to blanking-electrodes which are placed around the blanking-plate openings. A charged particle 200x reduction optics demagnifies the beamlet array to the substrate. The switched off beams are filtered out in the projection optics so that only the beams which are unaffected by the blanking-plate are projected to the substrate with 200x reduction. The blanking-plate is basically a CMOS device for handling the writing data. In our work the blanking-electrodes are fabricated using CMOS compatible add on processes like SiO₂-etching or metal deposition and structuring. A new approach is the implementation of buried tungsten electrodes for beam blanking.

In the Mask D2I project at ASET, the authors evaluated an e-beam multi column cell exposure system with character projection to expose photomask patterns of 65nm and 45nm node logic devices with OPC corrections. They prepared more than 2,000 characters in a deflection area of a character projection mask extracted from the 65nm node logic device pattern. The character projection in the multi column cell system could expose patterns equivalent to those by the conventional variable shaped beams. In a typical pattern layout of photomasks of 45nm node logic devices, the four column cell system required the exposure time of about 1/3 of the time required by a single column system. The character projection could reduce the exposure time corresponding to the reduction of shot counts. The pattern priorities also reduced the exposure time as the result of shot count reduction and minimizing wait time for deflection settling.

The accuracies of image placement and line-width on masks become very serious with continued reduction of design rules in semiconductor device fabrication. Even a tiny deviation from the prescribed circumstances during a maskexposure process can result in severe damage to masks and require re-works, and result in increased mask manufacturing cost. In 2006, Mask Design, Drawing, and Inspection Technology Research Department (Mask D2I) at the Association of Super-Advanced Electronics Technologies (ASET), launched a 4-year development program for the optimization of mask design, drawing, and inspection to reduce the costs in photo-mask manufacturing. We have developed a self-diagnostic technology to monitor the process of data transfer and check the environmental condition during exposure to improve the reliability of the mask writer. The technology can improve the efficiency of mask inspection if the deviation points are known prior to the inspection. Our monitor and self-diagnostic system consists of a verification system for data processing, writing simulator, monitor for circumstances, and integrated diagnostic system. Each part in the monitor and self-diagnostic system monitors and diagnoses the status of data processing and circumstances. We evaluated the reliability of monitoring the outer circumstances using an actual mask writing tool. The details and results will be reported in this paper.

With the constantly improving maturity of e-beam direct write exposure tools and processes for applications in high volume manufacturing, new challenges with regard to speed, throughput, correction and verification have to be faced. One objective of the MAGIC high-throughput maskless lithography project [1] is the application of the physics-based simulation in a virtual e-beam direct write environment to investigate proximity effects and develop comprehensive correction methodologies [2]. To support this, a rigorous e-beam lithography simulator for the feature scale has been developed [3]. The patterning behavior is determined by modeling electron scattering, exposure, and resist processing inside the film stack, in analogy with corresponding simulation capabilities for the optical and EUV case. Some model parameters, in particular for the resist modeling cannot be derived from first principles or direct measurements but need to be determined through a calibration process. To gain experience with the calibration of chemically amplified resists (CAR) for e-beam lithography, test pattern exposures have been performed for a negative tone CAR using a variable-shaped beam writer operating at 50kV. A recently implemented model calibration methodology has been applied to determine the optimum set of resist model parameters. While the calibration is based on 1D (lines & spaces) patterns only, the model results are compared to 2D test structures for verification.

As semiconductor features shrink in size and pitch, there are strong needs for an advanced mask writer which has better patterning quality. Among various requirements for next photomask writer, we have focused on the requirements of ebeam size and position accuracy for hp 32nm and beyond generation. At the era of DPT, EUV, and complex OPC, the photomask is required to have extreme control of critical dimension (CD). Based on simulation and experiment, we present the e-beam requirements for advanced mask writer, in view point of stability and accuracy. In detail, the control of e-beam size in mask writer should be decreased to 0.5nm because the size error of e-beam gives rise to large CD error according to the high complexity of mask pattern. Furthermore, the drift error of beam position should be smaller than 1nm to obtain the tight pattern placement error and to minimize the edge roughness of mask pattern for the era of computational lithography and EUV lithography.

The application of Mask CD-SEM for process management of photomask using two dimensional measurements as photomask patterns become smaller and more complex, [1]. Also, WPI technology application using an optical Mask inspection tool simulates wafer plane images using photomask images [2]. In order to simulate the MEEF influence for aggressive OPC and High-end photomask patterns in 32nm node and beyond, a requirement exists for wide Field of View (FOV) GDS data and tone information generated from high precision SEM images. In light of these requirements, we developed a GDS data extraction algorithm with sub-nanometer accuracy using wide FOV images, for example, greater than 10um square. As a result, we over come the difficulty of generating large contour data without the distortion that is normally associated with acquired SEM images. Also, it will be shown that the evaluation result can be effective for 32 nm applications and beyond using Mask CD-SEM E3620 manufactured by Advantest. On the other hand, we investigate the application example of the wide FOV GDS data. In order to easily compare the acquired GDS data with design data, we explain the separate algorithm with three layer structures for Tri-tone (Ternary) photomask pattern, consisting of an outer pattern and another pattern.

In EUV lithography (EUVL) it is important to protect a mask from the adhesion of particles because it is difficult to use a pellicle. At Selete, we evaluated a dual-pod carrier and reported on its ability to protect a mask from particles. In the evaluation the average number of particles added to the mask during several hundred handling-cycles was 0.4. Therefore, it is very important to precisely count the number of particle adders. However, according to the specification of the inspection tool, the counting error was greater than the average number of particle adders in the evaluation. In addition, it is known that the error increases for particles with a size near the detection limit. In the evaluation, we inspected a mask substrate four times and regarded signals detected multiple times as real particles. We studied the counting error by assuming that the detection probability followed a static statistical fluctuation. We found that the expected value of counting error was represented with the equation by the number of initial particles, particle adders, capture rate, and inspection times. Under our evaluation condition, even if no quasi-particles existed, the counting error by a single inspection was estimated to be approximately 4. However, the counting error by our evaluation (four inspections) was estimated to be approximately 0.05. Therefore, we found that the reliability by multiple inspections was much higher than that by a single inspection and that the number of particles near the detection limit could be found precisely by multiple inspections. * This work was supported by NEDO.

The E-Reticle^TM system was used to assess the electrostatic risks from mask manufacturing equipment and processes. Test results showed that some mechanical operations of the equipment examined may cause electrostatic potential differences in a production reticle higher than the ITRS recommended specifications, which may bring electrostatic risks to the reticle. E-Reticle^TM data also indicated that the processes play an important role in controlling electrostatic potentials in the reticle. The E-Reticle^TM system can be used as an in-situ equipment assessment tool, as well as a process optimization device.

Concept of asynchronous DB defects inspection machine was contrived to the purpose of reducing the price which had large scale flash memory buffer. This memory buffer was located in between reference data rendering computer and scanner; also it was located in scanner and image computer. As first step to make the concept model real, an experimental system was built which had virtual scanner.

As the feature size is smaller, the overlay budget of lithography for the rigorous manufacturing control becomes so small. And, overlay accuracy has become more important due to small overlap margin and double patterning process. Recently, a scanner maker has developed several effective solutions to correct the errors of overlay in field. But, the error induced by photomask still remains, so the accuracy of photomask image placement is required below than several nm for the HP 3X nm memory device generation. But, current e-beam writers don't meet this specification. There are various sources of image placement errors. Many papers report their analysis of those errors, so we focus on e-beam charging effect and compensation. Especially, their compensating methods are too complex to apply to production. So, it is need a simple way to compensate to image placement errors effectively.

Using AIMS^TM to qualify repairs of defects on photomasks is the industry standard. AIMS^TM provides a reasonable matching of lithographic imaging performances without the need of wafer prints. The need of utilisation of this capability by photomask manufacturers has risen due to the increased complexity of layouts incorporating aggressive RET and phase shift technologies as well as tighter specifications have pushed aerial image metrology to consider CD performance results in addition to the traditional intensity verification. The content of the paper describes the utilisation of the AIMS^TM Repair Verification (RV) software for the verification of aerial images in a mask shop production environment. The software is used to analyze images from various AIMS^TM tool generations and the two main routines, Multi Slice Analysis (MSA) and Image Compare (IC), are used to compare defective and non-defective areas of aerial images. It is detailed how the RV software cleans "non real" errors potentially induced by operator misjudgements, thus providing accurate and repeatable analyses all proven against the results achieved manually. A user friendly GUI drives the user through few simple, fast and safe operations and automatically provides summary tables containing all the relevant results of the analysis that can be easily exported in a proper format and sent out to the customer as a technical documentation. This results in a sensible improvement of the throughput of the printability evaluation process in a mask manufacturing environment, providing reliable analyses at a higher productivity.

We report on the development of a new mask inspection technology that makes total inspection faster and less costly. The new technology adopts a method of selecting a defect detection sensitivity level for every local area, defined by factors such as defect judgment algorithm and defect judgment threshold. This approach results in a reduction of pseudodefect count leading to shorter inspection and review time. Selected defect detection sensitivity levels for every local area are extracted from a database of Mask Data Rank (MDR) that is based on the design intent from the design stage, and/or on a pre-analysis of inspection pattern data. The proposed system also executes a printability verification function, not only for the mask defect regions but also for specific portions where high Mask Error Enhancement Factor (MEEF) is determined. It is necessary to ascertain suppression of pseudo-defect detection for extremely complicated masks such as masks with Source-Mask Optimization (SMO). This work reports on the new mask inspection system.

Patterns which are not aligned to standard orthogonal (x and y ordinate) directions have recently been developed for advanced lithography nodes. Efforts have been successful in developing single pass nanomachining repair processes to meet the printability requirements for these patterns. This development makes use of the latest improvements made to the COBRA repair process (the Enhanced COBRA process typically completed in less than 2 minutes of repair time) with symmetric NanoBits to repair opposing critical edges of bridging defects. It also required fundamental changes in the software tools to allow automated detection of the angle of the edges and the application of pre-programmed repair edge biases normal (90°) to the detected angled edges. Additionally, some other new improvements (hardware, software, and process) are reviewed in light of more traditional nanomachining repairs.

In this paper, we will report on the cleaning process durability and light shielding capability of FIB- and EB-CVD (Chemical Vapor Deposition) films which, are applied to repair clear defects on EUV mask. We evaluated tungsten containing, and silicon containing precursors in addition to carbon based precursor. For the conventional photomasks, the carbon based precursor is applied for repairing the clear defects because the reconstructed patterns by the carbon based precursor have excellent printability. However, under the condition of EUV lithography, the optical property of carbon deposited film is quite different. From the stand point of beam, FIB-CVD films showed better cleaning process durability and light shielding capability than EB-CVD film did. These differences are attributed to chemical components of the CVD films, especially with the tungsten based FIB-CVD film that contains 44 atomic % of tungsten and 24 atomic % of gallium. The tungsten based FIB-CVD film showed no loss of film thickness after dry cleaning, and the calculation showed that 56nmt was sufficient for repairing clear defects on EUV mask with 51nmt of absorber layer. On the other hand, carbon based FIB-CVD film suffered considerable loss in the film thickness and needed more than 180nm.

Currently, repair technology is one of the key factors in mask making process regarding TAT reduction and yield level enhancement. Since its commercial release EB repair tool has been commonly used for production line and contributed to high quality repair. But it is not guaranteed whether those conventional machines can keep up with future pattern reduction trend or not. In 2Xnm generation node some advanced exposure techniques seem to be adopted and that will inevitably require higher specification of repair machine. A simple lithography simulation predicts 5nm of indispensable repair accuracy for 2Xnm generation pattern. This number implies the necessity of upper class machine. Generally, the error budget of EB repair tool is composed of three to four components, stated another way mechanical stability, electrical (charging) uniformity, process stability, and graphical quality including software ability. If errors from those components are reduced, overall repair accuracy could be better. A suggestion which can improve those errors was issued last year from tool vender including new machine concept. We have conducted several kind of experiment in order to confirm the performance of new machine. In this paper, we will report the result of experiment and consider which part can effectively contribute to repair accuracy. And we have also evaluated its practical utility value for 2Xnm node by verifying actual application of some 3Xnm production masks.

In mask fabrication, e-beam exposure equipment malfunctioning could produce erroneous masks, several consecutive mask failures in the worst case. This type of error might unexpectedly increase mask turnaround time. Due to high cost of mask fabrication and its annual growth, it is critical detecting those errors as early as possible. Since mask SEM images at after-development inspection (ADI) phase have more visible noise, edges might be hard to detect clearly using classical edge detection algorithms. In this context, we present a novel pattern error detecting algorithm to capture pattern errors in mask monitoring patterns by inspecting mask SEM images at ADI phase. The originality of this paper lies in its use of simple but powerful techniques in a series used for automated error detection. More specifically, we inspect two specific types of errors in SEM images of monitoring patterns: bridging errors in a chessboard pattern, and CD uniformity errors in a line-and-space pattern. For a chessboard pattern, we utilize both horizontal and vertical projections of image intensity histogram to find areas for inspection automatically. From one dimensional projection of the image, we identify spatial coordinates of our interests, and define a small rectangular region, called D-region. For each D-region, we determine whether a pattern bridge is likely to occur, based on the ratio of brighter pixels in it. For a line-and-space pattern, we compute base lines for CD measurement, and detect CD uniformity errors or line shift errors by applying similar one dimensional histogram analysis and CD-computation algorithm to the image. Our experimental results using real pattern images and programmed defect images support that this technique is effective and robust in detecting errors without layout data or another SEM image for comparison.

The load of VSB-EB mask writers has significantly increased since particularly RET/OPC and CMP dummy pattern generation technologies were widely adopted into designs at advanced nodes, with the result that the volume of mask data patterns was increased exponentially. In order to reduce the load of VSB mask writer, we've focused on CMP dummy patterns and developed a method of reducing CMP dummy pattern, which can smartly write CMP dummy patterns without not only deteriorating the CMP effects by them and also increasing the total number of the mask writer's shot count. To that end, we are aiming to establish a VSB-mask-writer-friendly CMP dummy pattern generation flow with CMP simulator developers by providing a mask writer parameter for them. This paper shows the first experimental results of our mask writer's load reduction work.

The photomask cost is becoming one of the challenging issues in the semiconductor industry, as the cost of photomasks has been rising year by year. ASET started Mask D2I (Mask Design, Drawing and Inspection Technology) project with the sponsorship from the NEDO (New Energy and Industrial Technology Development Organization) in 2006 for the purpose of the mask cost reduction. In earlier papers[1-5], we introduced the idea of photomask data prioritization method which is referred to as Mask Data Rank (MDR). We have built our software system to convert Design Intent (DI) to MDR with cooperation of STARC. Then we showed the results of experiments with mask data provided by semiconductor companies. In this paper we show the additional report of mask inspection experiments using real photomasks. Then we show the evaluation results about mask drawing time reduction using MDR flow. Finally we introduce detailed algorithm to extract design intent from analog circuits.

OASIS (P39) specification imposes few restrictions on file structure and does not enforce the use of standard properties and features such as strict mode. As a natural consequence, P39 readers must be general enough to cover all possible types of input, and this leads to inefficiencies. In contrast, OASIS.MASK (P44) specification, which is a formal subset of P39, has restrictions on file structure and enforces the usage of properties, both standard and user mandatory ones. In addition to this, strict mode is mandatory and new features like Localization are added. Even though it is possible to read a P44 file using general P39 readers, such readers do not take advantage of the special P44 characteristics and therefore remain inefficient, especially for applications needing fast random access to arbitrary extents of data within the file. In this paper we explain the concepts that should be considered in the design of an efficient P44 reader and present Synopsys CATS^R implementation. Experimental results comparing CATS^R P44 specific reader against standard P39 readers show significant performance benefits.

As we prepare for 32nm-hp with 193nm immersion, complex and sometimes curvilinear shapes are going to be required on masks. Contacts and vias will be circular or oval in shape on the wafer, but are still drawn as over-sized squares or rectangles on masks and in CAD systems. Yet, for packing density of designs, particularly for DRAMs and SRAMs, in order to optimize for diagonal distances, a circular via shape on the mask is desirable. In addition, a circle has by definition the minimum perimeter for a given area, improving manufacturing tolerance. This paper demonstrates new techniques for writing circles of arbitrary diameters on masks efficiently and accurately using a production e-beam mask writer. Resist-exposed SEM images are shown, demonstrating the practicality of writing circles as mask shapes for production reticles.

Traditionally, Mask Data Preparation (MDP) flow for Variable Shape E-Beam (VSB) writers has been optimized in a generic fashion to minimize slivers and reduce shot count while maintaining data symmetry. To date, this approach has been sufficient and allowed the mask industry to meet requirements for CD uniformity, registration, and write time. However, ever tighter error budgets and increasing pattern complexity are driving a need for writer-specific optimization of MDP. This paper summarizes the joint development effort between Synopsys and JEOL to optimize MDP fractures for the JEOL platform. The advantages and challenges of platform specific optimization are discussed.

A requirement for CD control on wafer is increasing with shrinking design rule^[1]. This is especially true for dense contacts because of higher MEEF. It is considered that contact mask LER impact on lithographic performance is comparatively large. Nevertheless, a relationship between contact mask LER and wafer performance has not been evaluated in recent years. Therefore we studied contact mask roughness impact on wafer in order to determine specs for improvement of mask quality. We assumed the thin MoSi binary mask which was called Opaque MoSi On Glass (OMOG). The programmed roughness patterns data for 28 nm nodes was made. The frequency and depth of roughness was changed. In addition, we also drew bump patterns. A lithography simulator was used to investigate which kind of mask roughness impacted significantly on wafer. We compared the difference between wafer experiment and simulation. Finally a relationship between contact mask roughness and lithographic performance was obtained.

Inverse Lithography Technology (ILT) is becoming one of the strong candidates for 32nm and below. ILT masks provide significantly better litho performance than traditional OPC masks. To enable ILT for production as one of the leading candidates for low-k1 lithography, one major task to overcome is mask manufacturability including mask data fracturing, MRC constraints, writing time, and inspection. In prior publications^[4,5], it has been shown that the Inverse Synthesizer (IS^TM) product has the capability to adjust for mask complexity to make it more manufacturable while maintaining the significant litho gains of nearly ideal ILT mask. The production readiness of ILT has been demonstrated at full-chip level. To fully integrate ILT mask into production, a number of areas were investigated to further reduce ILT mask complexity without compromising too much of process window. These areas include flexible controls of SRAF placements with respect to local feature sizes, separate control of Manhattan mask segment length of main and SRAF features, topology based variable segmentation length, and jog alignment. The impact of these approaches on e-beam mask writing time and lithography performance is presented in the paper.

Optical proximity correction (OPC) is one of the most widely used Resolution Enhancement Techniques (RET) in mask designs. Conventional OPC is often designed for a set of nominal imaging parameters without giving sufficient attention to the process variations caused by aspherical wavefront leaving the exit pupil of the lithography system. As a result, the mask designed may deliver poor performance with process variations. In this paper, we first describe how a general point spread function (PSF) with wave aberration can degrade the output pattern quality, and then show how the wave aberration function can be incorporated into an inverse imaging framework for robust input mask pattern design against aberrations. A level-set-based time-dependent model can then be applied to solve it with appropriate finite difference schemes. The optimal mask gives more robust performance against either one specific type of aberration or a combination of different types of aberrations.

Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI) such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus (DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of assist features to be used. However in the case of random contact holes, rule-based SRAF placement is a nearly impossible task. To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described.

The most important factor in extreme ultra violet (EUV) mask process is thickness variations which caused by resist dark loss, absorber etching and capping layer durability of cleaning chemical at each layer. For example if multilayer (M/L) is damaged due to 2.5nm capping layer loss after cleaning, it means it is impossible to get sufficient reflectance to make proper EUV mask.

Reticle quality and the capability to qualify a reticle are key issues for EUV Lithography. We expect current and planned optical inspection systems will provide inspection capability adequate for development and production of 2X HP masks. We illustrate inspection technology extendibility through simulation of 193nm-based inspection of advanced EUV patterned masks. The influence of EUV absorber design for 193nm optical contrast and defect sensitivity will be identified for absorber designs of current interest.

Discrete Track Recording Media (DTR-Media) requires 50nm track pitch patterns and a mold as the start for 1 Tb/inch² areal density, which is a quality 15nm groove (trench) and beyond. Last year, 14nm groove was achieved with a newly designed solvent developer for ZEP520A, we reported in PMJ 2009. But, we still need to pursue extreme high resolution such as 10nm groove or 12.5nm dot array for bit patterns with ZEP520A since no alternative was found so far. To improve ZEP520 resolution, we just keep trying to find a new developer with a lower development speed for ZEP520 than the previous one. Then, a Fluoro-Carbon was selected from various candidates. It was proved that ZEP520 and the Fluoro-Carbon developer provided 11nm groove resolution at an exposure dose of 1800μC/cm². Furthermore, the mixture of the Fluoro-Carbon and Solvent B provided the same 11nm groove resolution at a higher sensitive, i.e. less exposure dose than the Fluoro-Carbon and even the Solvent B.

Since 2005, Canon, Nikon, and Entegris have been jointly developing an EUV mask carrier based on the "Dual Pod" concept in place of a pellicle. By using our MIRAI-Selete Mask Protection Engineering (MPE) tool, a few prototypes were tested for performance of particle protection in the case of both mask shipping and its handling in vacuum. As a result, the fundamental mechanical specifications of the Dual pod were registered as those of SEMI "E152" of an EUV Pod used in EUV mask. It is found that the latest pod named "cnPod", which is based on the SEMI E152, performs almost satisfactorily. Although superior protection performance with respect to external particles has been confirmed, the performance with respect to internal particles laid on the base plate of an inner pod is still under investigation. Therefore, we evaluate the influence of the internal particles laid on the base-plate surface for the first time. In order to confirm whether the particles on the base plate are transferred to the mask-patterned surface, well-characterized particles are dispersed on the base-plate surface. By using this contaminated base plate and the MPE tool, mask handling experiments are conducted. Under our experimental conditions, it is found that the number of test particles transferred to the mask surface is very low compared to the total number of particles on the base-plate surface.

Achieving the specifications of line width roughness (LWR), sensitivity and resolution of wafer resist is one of the top challenges of bringing extreme ultraviolet lithography (EUVL) into high volume manufacturing. At the same time, EUV mask LWR is set on very ambitious target value from ITRS ^[1] because mask LWR would contribute to wafer resist LWR more strongly than that of ArF lithography due to dramatic decrease of wavelength. Mutual relation between mask and wafer resist LWR has been discussed ^{[2] [3]} but not frequently, so standardization of mask LWR measurement is not fixed. SEM image analysis is common to measure mask LWR but the value depends on measurement parameters such as segment length of pattern edge. In this paper, optimum measurement conditions with SEM will be investigated and discussed using SEM images of actual mask and aerial simulation. And also we will report development status of actual mask LWR.

EUV lithography is regarded as the leading technology solution for the post-ArF era. Significant progress was made in recent years in closing the gaps related to scanner technology. This progress rendered EUV mask defectivity and related infrastructure as the primary risk for EUV lithography. The smallness of mask features, the novel defectivity mechanisms associated with the multilayer reflecting coating, and the stringent constraints on both multilayer and pattern imposed by the EUV wavelength - present a major challenge to current inspection technology, which constitutes a predominant gap to EUVL production-worthiness. Here we present results from an evaluation of a DUV mask inspection system and e-beam mask inspection technology on EUV masks. On this 193nm DUV system, we studied sensitivity and contrast enhancements by resolution enhancement techniques. We studied both pattern and blank inspection. Next, we studied image formation and performance of e-beam mask inspection technology for patterned mask defects. We discuss the advantages and roadmap of DUV and EBI mask inspection solutions for blank and patterned masks.

Electron backscattering from Extreme Ultraviolet (EUV) masks during Electron Beam (EB) exposure was studied by simulations and experiments. The film structure of EUV masks is quite different from that of photomasks. The Mo/Si multilayer on the EUV substrate is very thick (280 nm) and heavy metal material such as Ta is used for the absorber. Monte Carlo simulations suggest that the absorbed energy inside the resist caused by the backscattered electrons from these films is non-negligible, about 1/10 of the forward scattering electrons and 1/4 of the backscattered electrons from the substrate. Also the simulations show that the influence range is very short because the backscattering happens near the mask surface. These simulations were verified by conducting EB exposure experiments. Short-range proximity effect was clearly observed by measuring the resist Critical Dimentions (CDs) of short bars laid beside the large exposed area. The data were fitted by assuming a backscattering electron distribution which has an exponential form with 0.4 μm range. The range is very short compared with the conventional proximity range of 10 μm. We conclude that the conventional EB proximity effect correction method needs to be revisited for EUV masks.

EUV lithography is a promising candidate for 2x-nm-node device manufacturing. Management of effective dose is important to meet the stringent requirements for CD control. Test pattern for a lithography tool evaluation, the effective dose monitor (EDM), shows good performance in the dose monitoring for optical lithography, for example, KrF lithography. The EDM can measure an exposure dose with no influence on defocus, because the image of an EDM pattern is produced by the zero-th-order ray in diffraction only. When this technique is applied to EUV lithography, the mask shadowing effect should be taken into consideration. We calculated the shadowing effect as a function of field position and applied it to correction of the experimental dose variation. We estimated the dose variation in EUV exposure field to be 2.55 % when corrected by the shadowing effect. We showed that the EDM is useful for EUV lithography.

Optical proximity correction (OPC) is still an essential technology for critical dimension (CD) control in Extreme Ultra Violet (EUV) lithography. For quality assurance of EUV mask pattern, a metrology of complicated two-dimensional (2D) OPC patterns is important. Moreover, the side wall angle management of a mask pattern becomes important in EUV lithography because exposure light is diagonally incident on a mask pattern. The quality assurance of EUV mask pattern requires the pattern edge extraction including the side wall angle. We had developed an SEM which is one of the key factors of this three-dimensional (3D) quality assurance method. The high accuracy measurement of a side wall angle using Tilting and Moving Objective Lens (T-MOL) is most feature of this SEM. Employing this SEM, we will add the side wall angle information to the system for guaranteeing 2D OPC patterns before shipping the mask to a wafer factory. In this paper, we report the study about the management of the side wall angle of an EUV mask pattern. And then we report the evaluation results of the side wall angle measurement system with a tilted fine pixel SEM image that satisfies the requirement of the management.

We are focusing on the establishment of a flare correction technique for half pitch (HP) 22-nm generation in Extreme Ultra Violet Lithography (EUVL). However, there are some difficulties in the areas of flare calculation and edge biasing, associated with flare correction because of the tighter CD control requirements. In our previous work, we investigated the feasibility of an improved flare calculation and a new way of edge biasing. For the flare calculation, we adopted a short-range flare kernel method, which calculates short-range flare using a fine mesh only at the edges of patterns that require correction. From the simulation and experimental results of this method, we confirmed that it can calculate flare value accurately in a reasonable runtime. On the other hand, since the edge biasing has pattern dependency the work has to be customized accordingly, and that can lead to labor intensive task of pattern-dependent biasing. To address this problem, we began to explore the usefulness of model-based flare correction that has been improved where it can modulate the aerial image according to the flare effect during model-based OPC. For this work, we prepared a test mask containing line-and-space (L/S) patterns of several pitches with different flare levels. We then evaluated the accuracy of the model-based flare correction by simulating the corrected L/S patterns using a rigorous lithography simulation with 3-D mask stack structure. As a result, the CD error range was found to be from - 1.56 to 1.12 nm, which is within ±2 nm (±10 % of the minimum target CD). It is thus concluded that the model-based flare correction can deliver high accuracy results even where OPCs are also involved.

Advanced photomasks exploit complex patterns that show little resemblance to the target printed wafer pattern. The main mask pattern is modified by various OPC and SRAF features while further complexity is introduced as source-mask-optimization (SMO) technologies experience early adoption at leading manufacturers. The small size and irregularity of these features challenge the mask inspection process as well as the mask manufacturing process. The two major concerns for mask inspection and qualification efficacy of advanced masks are defect detection and photomask inspectability. Enhanced defect detection is critical for the overall mask manufacturing process qualification which entails characterization of the systematic deviations of the pattern. High resolution optical conditions are the optimal solution for manufacturing process qualification as well as a source of additional information for the mask qualification. Mask inspection using high resolution conditions operates on an optical image that differs from the aerial image. The high resolution image closely represents the mask plane pattern. Aerial imaging mode inspection conditions, where the optics of the inspection tool emulates the lithography manufacturing conditions in a scanner, are the most compatible imaging solution for photomask pattern development and hence mask inspectability. This is an optimal environment for performing mask printability characterization and qualification. In this paper we will compare the roles of aerial imaging and high resolution mask inspection in the mask house.

A new 193nm wavelength high resolution reticle defect inspection platform has been developed for both die-to-database and die-to-die inspection modes. In its initial configuration, this innovative platform has been designed to meet the reticle qualification requirements of the IC industry for the 22nm logic and 3xhp memory generations (and shrinks) with planned extensions to the next generation. The 22nm/3xhp IC generation includes advanced 193nm optical lithography using conventional RET, advanced computational lithography, and double patterning. Further, EUV pilot line lithography is beginning. This advanced 193nm inspection platform has world-class performance and the capability to meet these diverse needs in optical and EUV lithography. The architecture of the new 193nm inspection platform is described. Die-to-database inspection results are shown on a variety of reticles from industry sources; these reticles include standard programmed defect test reticles, as well as advanced optical and EUV product and product-like reticles. Results show high sensitivity and low false and nuisance detections on complex optical reticle designs and small feature size EUV reticles. A direct comparison with the existing industry standard 257nm wavelength inspection system shows measurable sensitivity improvement for small feature sizes