This PDF file contains the front matter associated with SPIE Proceedings Volume 8441, including the Title Page, Copyright information, Table of Contents, Introduction, and Conference Committee listing.

In this study, the relationship between the depth profile of features and critical dimension (CD) deviation on MoSi binary photomasks is comprehensively investigated using 3D atomic force microscopy (3D-AFM) and aerial image metrology system (AIMS). Detailed profile description based on various surface analysis techniques, was performed to reconstruct the profile at various stages of the mask fabrication process. It is found that profile change and sidewall byproduct formation are strongly correlated with the etching environment, wet cleaning, and post-treatment. These process-induced profile changes subsequently lead to wafer CD change which can be verified by deviation in AIMS and CDSEM measurements. Visualization of these 3D profile and morphology change clearly reveals that etching gas control forms an outer layer, to enhance etch selectivity, film strength, and immunity to the mask cleaning process. Our finding provides a direction for optimizing advanced photomask materials and processing.

Strict reticle critical dimension (CD) control is needed to supply ≤ 20nm wafer technology nodes. In front end lithographic processes for example, precise temperature control in resist baking steps is considered paramount to limiting reticle CD error sources. Additionally, current density during writing and focus are continuously tracked in 50kV e-beam pattern generators (PG) in order to provide stable CD performance. Despite these strict controls (and many others), feedback compensation strategies are increasingly utilized in mask manufacturing to reach < 2nm 3σ CD uniformity (CDU). Such compensations require stable reticle CD signatures which can be problematic when alternate or backup process tools are employed. The AMTC has applied principle component analysis (PCA) to resist CD measurements of 50kV test reticles fabricated with chemically amplified resists (CAR) in order to quantify the resist CDU capabilities of front and backup lithographic process tools. PCA results elucidate significant resist CDU differences between similar lithographic process tools that are considered well matched via CDU 3σ comparisons. The utility of PCA relies on the statistical analysis of large data sets however, reticle CD sampling is typically sparse, on the 10^-2 m or centimeter (cm) scale using conventional scanning electron microscopes (CD SEM). Higher CD spatial resolutions can be achieved using advanced inspection tools, which provide CD data on a substantially smaller length scale (10^-4 m), thus yielding a considerably larger CD snapshot for front/backup process tool comparisons. Combining PCA analysis with high spatial resolution CD data provides novel insights into the opportunities for tool and process CD capabilities.

Scanner expose condition is simulated to reproduce Chrome (Cr) migration on COG mask, known as a new type of mask degradation, with high energy fluency ArF acceleration tool. Contact hole size is decreased by forming rim inside sidewall of contact hole. CD change is observed as expose energy accumulates. Bridge defect is found on the unexposed line end feature adjacent to grounded pattern. Grounded mask showed much worse Cr migration than not grounded one. It may be analogized that the driving forces of Cr migration is relatively higher ArF energy (6.8eV) than self diffusion activation energy of Cr (3.5eV). Isolated exposed pattern will be positively charged by photovoltaic effect. Electric field potential with adjacent ground pattern formed by photovoltaic effect possibly boosts the Cr migration and material loss. New prevention treatment has been developed to mitigate Cr migration and it worked quite well. Cr migration by ArF expose wasn't found even grounded condition.

EUV lithography is one of the approaches to manufacture half-pitch 1x nm devices. It is required high CD mean control, high CD uniformity, and low defect density for EUV mask in common with DUV mask. In addition, backside defect density is drastically tightened to avoid overlay error in EUV scanner. PGSD (Proximity-Gap-Suction-Development), a novel development system we developed, has kept upgrading to satisfy the demand of most-advanced devices, and 3rd-generation PGSD (PGSD Gen. III) which developed for EUV mask will be contributed to achieve required accuracy of EUV mask. In this paper, we propose the concept of PGSD Gen. III and report its performance.

With the next technology nodes 193nm lithography is pushed to its utmost limits. The industry is forced to print at low k1 factor which goes along with a high MEEF. Additionally, new blank materials are being introduced for smaller nodes. From 4x node and beyond, global CD uniformity on wafer is getting more critical and becomes key factor to ensure a high yield in chip production. Advanced process control is required and correction strategies are applied to maintain tight wafer CD uniformity. Beside other parameters, like scanner and etch process, mask CD uniformity is one main contributor to the intra-field CD on wafer. To enable effective CDU correction strategies it is necessary to establish a mask CD uniformity metrology which shows a good correlation to wafer prints. Especially for logic pattern mask uniformity measurements to control intra-field CD uniformity becomes challenging. In this paper we will focus on mask CD uniformity measurement for logic application utilizing WLCD, which is based on aerial image technology. We will investigate 40nm node and 28nm node gate masks using 6% MoSi phase shifting mask and MoSi binary mask respectively. Furthermore, we will correlate the mask CD uniformity data to wafer data to evaluate the capability of WLCD to predict the intra-field wafer CD uniformity correctly in order to support feedforward correction strategies. We will show that WLCD shows an excellent correlation to wafer data. Additionally, we will provide an outlook on logic contact-hole masks showing first CD uniformity data and wafer correlation data.

Optical lithography stays at 193nm with a numerical aperture of 1.35 for several more years before moving to EUV lithography. Utilization of 193nm lithography for 45nm and beyond forces the mask shop to produce complex mask designs and tighter lithography specifications which in turn make process control more important than ever. High yield with regards to chip production requires accurate process control. Critical Dimension Uniformity (CDU) is one of the key parameters necessary to assure good performance and reliable functionality of any integrated circuit. There are different contributors which impact the total wafer CDU, mask CD uniformity, resist process, scanner and lens fingerprint, wafer topography, etc. In this paper, the wafer level CD metrology tool WLCD of Carl Zeiss SMS is utilized for CDU measurements in conjunction with the CDC tool from Carl Zeiss SMS which provides CD uniformity correction. The WLCD measures CD based on proven aerial imaging technology. The CDC utilizes an ultrafast femto-second laser to write intra-volume shading elements (Shade-In ElementsTM) inside the bulk material of the mask. By adjusting the density of the shading elements, the light transmission through the mask is locally changed in a manner that improves wafer CDU when the corrected mask is printed. The objective of this study is to evaluate the usage of these two tools in a closed loop process to optimize CDU of the mask before leaving the mask shop and to ensure improved intra-field CDU at wafer level. Mainly we present the method of operation and results for logic pattering by using these two tools.

The required measurement precision for multilayered EUV mask metrology is set below 0.4 nm three sigma. In addition to limited precision of CD-SEM, there are fundamental physical factors that deteriorate the accuracy of the measurements, the most important of which is charging. It is widely believed that EUV masks are conductive. However, experiments have revealed noticeable charging in CD-SEM measurements of EUV masks that cannot be ignored. In this work, the results of the experiments and simulations of the SEM signals are presented. It was shown that charging affects the metrology in a few ways. The SEM signal shifts at each frame, changes with beam current and also depends on the wall angle of the absorber. The results of the simulations are compared to experimental results.

As an alternative to EUV lithography, ArF immersion multiple patterning lithography has been heavily employed in semiconductor fabrication. This situation has led to increase use of bright-field photomasks with floating small patterns. Latest CDSEMs are equipped with various charge compensation features and applicable for devices with conductive and insulating material. However, there remain some difficulties when floating small patterns are to be measured. One of the specific examples is a floating dot on a via mask, dimension of which is around 200nm at the 45 nm process node, scaling down to 100nm at the 22nm process node. Since the dot has very small capacitance, it is easily charged by electron beam irradiation, and discharged in a short period. This kind of temporary voltage variation can affect the secondary electron yield, causes degradation of the SEM image contrast. We have analyzed that the "edge effect", which is the principle of SEM, has a primary role in small dot charging, and interchanging of scan line effectively suppresses the voltage variation. Based on this concept, we have developed a new scan technology for our "Multi Vision Metrology SEM" E3630, and improved the performance of image-based measurement. In this paper, the new scan technology and evaluation results are presented.

At sub 4X nm nodes in memory and sub 3X nodes in logic devices mask registration (Reg) is becoming a significant yield limiting factor. This is especially true for Double Patterning Technologies (DPT) where mask to mask overlay on the wafer is heavily influenced by mask registration error. Getting advanced mask registration into specification is a challenge for all mask shops as the tight registration specs are driven by tight wafer overlay specs. The first step in meeting the registration spec challenge in the mask shop is to be able to measure registration with the required specifications. With PROVE® Carl Zeiss SMS has recently introduced into the market a new registration and overlay metrology system which utilizes 193nm illumination for high resolution and a six axes controlled stage. The second step in meeting the registration spec challenge is to actively correct for intrinsic registration errors on the mask. For this Carl Zeiss SMS has developed the RegC® tool. The RegC® tool is based on writing strain zones with the help of an ultrashort pulse laser in the bulk of the mask. The strain zones induce deformations in the mask which practically push the misplaced features to a new location that after removing scale and orthogonality (S/O) correctable errors reflects a smaller residual registration error. By combining the RegC® tool with data generated by PROVE® it is possible to close the loop on the registration control process in the mask shop without wafer print or mask re-write. In this paper we report the demonstration results of a closed loop process between PROVE® and the RegC® tools.

First 50nm HP and 24nm iso line scanning stripe exposures with 1.4nm 1sigma stripe butting are shown of a proof-ofconcept electron multi-beam Mask Exposure Tool (eMET POC), operating the column with an Aperture Plate System (APS), providing 256k (k=1024) programmable beams of 20nm beam size and 50keV beam energy at substrate within 82μm × 82μm beam array fields. Multi-beam proximity effect correction (PEC) is shown with long range corrections by local dose adjustments. The capability of exposing OPC jog patterns down to 1nm jog height is demonstrated as well as the possibility to expose complex ILT (inverse lithography techniques) patterns at no loss of throughput. The possibility to use low sensitive pCAR resist material with 80μC/cm² exposure dose is shown. The novel electron-optical column is suitable for Alpha, Beta and multi-generational HVM tools.

One of the concerned phenomena that influencing to the performance of electron beam mask writer is contamination of deflector. Previous studies show that the relation between the deflector contamination and pattern placement error. In fact, the source of the contamination of deflector was not defined clearly yet. However, the fact that of deflector contamination clearly influences the pattern placement error on mask fabrication. We think that there is no detailed investigation about the effect of deflector contamination on the pattern placement error of production photomask. This paper will describe the effect of e-beam positioning error due to the contamination of deflector in electron optic system. To reduce the placement error by the deflector contamination circumstance the e-beam drift was evaluated in various conditions of deflection based on the theoretical assumption and our own modeling, and optimization of the deflection condition. Furthermore, we will present the requirements on position accuracy of deflector for the photomask of sub 20nm device node.

Recently, most of defects on high-end masks are repaired with electron beam (EB). The minimum repairable dimension of the current state-of-the-art repair systems is about 20-30 nm, but that dimension is not small enough to repair the next generation masks. Meanwhile, new molybdenum silicide (MoSi) films with high cleaning durability are going to be provided for an alternative technology, but the etching selectivity between new MoSi and quartz under EB repair process is not high enough to control etching depth. We developed the focused ion beam (FIB) technology that uses light ions emitted from a gas field ion source (GFIS). In this study, the performance of our developed GFIS mask repair system was investigated by using new MoSi (HOYA-A6L2). Specifically, the minimum repairable dimension, image resolution, imaging damage, etching material selectivity and through-focus behavior on AIMS were evaluated. The minimum repairable dimension was only 11 nm that is nearly half of that with EB. That result suggests that GFIS technology is a promising candidate for repairing the next generation masks. Meanwhile, the etching selectivity between A6L2 and quartz was 6:1. Additionally, the other evaluations on AIMS showed good results. Those results demonstrate that GFIS technology is a reliable solution of repairing new MoSi masks with high cleaning durability.

The technology to selectively remove nanoparticles from a photomask surface by adhering it to an AFM tip (BitClean) first introduced with the Merlin^® nanomachining mask repair platform has been successfully integrated in numerous mask house production centers across the globe over the last two years. One outstanding request for development from customers has been to develop the capability to not only selectively remove nanoparticles from a target surface, but to also redeposit in another target region. This paper reviews the preliminary work done to develop this capability with particular emphasis on its potential applications in creating realistic nanoparticle inspection sites for KLA systems at critical pattern print locations as well as the accumulation of trace amounts of contaminates for better compositional and print-impact analysis. There is also a feasibility study of new ultra-high aspect ratio (AR > 1.5) NanoBits for future BitClean process applications. The potential for these capabilities to be adapted for new applications will be examined for future work as well as a detailed parametric process analysis with the goal of showing how to make significant improvements in BitClean PRE.

The EUV-photomask is used as mirror and no longer as transmissive device. In order to yield defect-free reticles, repair capability is required for defects in the absorber and for defects in the mirror. Defects can propagate between the EUV mask layers, which makes the detection and the repair complex or impossible if conventional methods are used. In this paper we give an overview of the different defect types. We discuss the EUV repair requirements including SEMinvisible multilayer defects and blank defects, and demonstrate e-beam repair performance. The repairs are qualified by SEM, AFM and through-focus wafer prints. Furthermore a new repair strategy involving in-situ AFM is introduced. We will apply this new strategy on real defects and verify the repair quality using state of the art EUV wafer printing technology.

A perspective is given using student projects on how university research can be an important resource for the highly advanced and sophisticated photomask industry. The collaborative and cross-discipline nature of innovation in the IC industry naturally leads to win-win relationships. Specific examples are given of successful collaborative research projects from the University of California consortium "Integrated Modeling Process and Computation for Technology" (IMPACT). The examples include research on lithography and inspection, devices, statistical characterization, and Design-for-Manufacturing frameworks for multiple-patterning and EUV. The paper concludes with a perspective on future opportunities, challenges and plans. The technical details of the student projects were published but not presented in connection with Photomask Japan 2011 (SPIE Proc. 8081).

OPC models describe the entire patterning process, including photomask, optics, resist, and etch as a set of separately characterized modules. It is difficult, however, to definitively calibrate the optics model since the aerial image is not easily measurable. It is therefore common to calibrate relevant optical parameters using a constant threshold applied to the aerial image in order to best fit the experimentally measured photoresist CDs. With the optical model thus fixed, a subsequent tuning of resist model parameters is enabled. Alternatively, both optical and resist parameters can be tuned in a single lumped calibration to the measurement data. The parameters associated with the calibration of the photomask, optical, resist and etch processes can be sorted into three classes. There are parameters that are directly measurable or known as designed-in values, such as wavelength, numerical aperture (NA), illumination source profile, and film stack optical constants. A second class of parameters is associated with physical phenomena, where direct measurement is not done, but rather the model contains mathematical proxies for the parameters. A final class of calibration options includes software options for altering the approximations used in the model, such as number of optical kernels, optical diameter, and the functional form of the resist or etch model. The degree to which the model can faithfully decouple photomask from optical exposure from resist processing is related not only to the details of the resist model, but also to the nature of the approximations "upstream" in the representation of the mask and optical system. This paper will systematically explore the impact of all components in the photomask and optical models, and will provide a pathway to sub-nanometer accuracy required for 20 nm technology.

Novel Optical Proximity Correction (OPC) flow using the new compact lithography model which predicts wafer patterns formed by the trim-mask lithography has been developed. The trim-mask lithography has been indispensable to manufacture the random-logic devices using the leading-edge processes which require double patterning technology (DPT) and/or restricted/reduced design rule (RDR). It is the litho-etch-litho-etch (LELE) DPT in which a trim process, a litho-etch (LE) process, follows one or several LE processes. The trim process is used to remove redundant patterns in order to achieve the final patterns corresponding to design intent after forming periodic and lithography-friendly patterns by the preceding LE processes. In addition, it is used to form the narrow gaps between line ends¹. Since the influence of both the preceding processes and the trim process on the final wafer patterns should be considered through the OPC development, it is necessary to moderate the interference between the OPC developments for the masks and to reduce the increase of required computational resources. The concept of the compact lithography model has been proposed, the results applied to random-logic designs have been shown, and effectiveness of the OPC flow has been discussed.

The hybrid optical proximity correction (OPC) verification flow uses both compact and rigorous lithography models. This is the approach we are investigating to meet the challenges to improve the accuracy while keeping the turnaround time (TAT) in check for each new technology node. The compact lithography model is derived from the Hopkins method to calculate the image at the wafer. They consist of the pre-calculated optical kernel set that includes properties of projection, source optics, and the resist effects. The image at the wafer is formed by the convolution of optical kernel set with the mask transmission. The compact model is used for OPC and lithography rule checking (LRC) due to its excellent TAT in full chip applications. Leading edge technology nodes, however, are inherently more sensitive to process variation and typically contain more low contrast areas, sometimes resulting in marginal hotspots. In these localized areas, it is desirable to have access to more predictive first principle lithography simulation. The Abbe method for lithography simulation includes full 3D resist models which solve from the first principles (the reaction/diffusion equation of the post exposure bake) to provide the highest accuracy. These rigorous models have the ability to provide added insight into the 3D developed profile in resist at the wafer level to assist in the application of OPC, verification and disposition of hotspots found by LRC using compact models. The hybrid OPC verification takes the advantage of compact model for TAT and rigorous model for 3D profile accuracy ^{[1], [2]}. And since the rigorous lithography simulator already supports new technologies like double pattern technology (DPT), electron beam (E-beam) ^[3] and extreme ultraviolet lithography (EUV) ^[4] this approach is extendable to multiple technology nodes.

Sub-resolution Assist Features (SRAFs) are powerful tools to enhance the focus margin of drawn patterns. SRAFs are placed and sized so they do not print on the wafer, but the larger the SRAF, the more effective it becomes at enhancing through-focus stability. The size and location of an SRAF that will image on a wafer is highly dependent upon neighboring patterns and models of SRAF printability are, at present, unreliable. Model-based SRAF placement has been used to enhance resolution at 20nm node processes and below with stringent requirements that inserted SRAFs will not be imaged on wafer. However, despite widespread SRAF use and hard data as to SRAF effectiveness, it has been very difficult to develop a process model that accurately predicts under what process conditions an SRAF will image on a wafer. More accurate models of SRAF printing should allow model based SRAF placement to be relaxed, resulting in more effective SRAF placement and broader focus margins. One of the first problems with the concept of SRAF printability is the definition of an SRAF printing on a wafer. This is not obvious because two different states of printing exist. The first print state is when a residue is left on a wafer from the SRAF. The first state can be considered printing from the point of view that photoresist is on the wafer and the photoresist may even lift off and cause defects. However, the first state can be considered non-printing because the over etch from the etch process will generally remove the photoresist residual and the material underneath. The second state is when a pattern is formed and etched into the substrate, a state at which the pattern has clearly printed on the wafer. Of course, intermediate states may also be defined. In order to be applicable, an SRAF printability model must be able to predict both printing states. In addition, the model must be able to extrapolate to configurations beyond those used to develop the model in the first place. These model properties may then be used to optimize the printability vs. efficacy of an SRAF either prior to or during an Optical Proximity Correction (OPC) run. The process models that are used during OPC have never been able to reliably predict which SRAFs will print. This appears to be due to the fact that OPC process models are generally created using data that does not include printed subresolution patterns. An enhancement to compact modeling capability to predict Assist Features (AF) printability is developed and discussed. A hypsometric map representing 3-D resist profile was built by applying a first principle approximation to estimate the "energy loss" from the resist top to bottom. Such a 3-D resist profile is an extrapolation of a well calibrated traditional OPC model without any additional information. Assist features are detected at either top of resist (dark field) or bottom of resist (bright field). Such detection can be done by just extracting top or bottom resist models from our 3-D resist model. There is no measurement of assist features needed when we build AF but it can be included if interested but focusing on resist calibration to account for both exposure dosage and focus change sensitivities. This approach significantly increases resist model's capability for predicting printed SRAF accuracy. And we don't need to calibrate an SRAF model in addition to the OPC model. Without increase in computation time, this compact model can draw assist feature contour with real placement and size at any vertical plane. The result is compared and validated with 3-D rigorous modeling as well as SEM images. Since this method does not change any form of compact modeling, it can be integrated into current MBAF solutions without any additional work.

With the advent of the large-sized and high-precision flat panel display, enjoying Virtual reality is getting more familiar. SK-Electronics CO., LTD. is only the mask maker that can produce the Over-Generation 10- sized LCD photomasks in the world. We, SK-Electronics CO., LTD. believe that we can provide the pleasure of virtual reality with higher realistic sensation through the super large-sized and high-precision photomasks .

Flat panel display (fpd) design needs further improving of design quality and efficiency due to aggressive market needs like fast growing 3d panel, big screen for tv. In this paper, we explain the specialized verification technology for panel layout, reticle of fpd whcich enable to reduce the respin and design tat.

Since its breakthrough, the liquid crystal technology has continued to gain momentum and the LCD is today the dominating display type used in desktop monitors, television sets, mobile phones as well as other mobile devices. To improve production efficiency and enable larger screen sizes, the LCD industry has step by step increased the size of the mother glass used in the LCD manufacturing process. Initially the mother glass was only around 0.1 m² large, but with each generation the size has increased and with generation 10 the area reaches close to 10 m². The increase in mother glass size has in turn led to an increase in the size of the photomasks used - currently the largest masks are around 1.6 × 1.8 meters. A key mask performance criterion is the absence of "mura" - small systematic errors captured only by the very sensitive human eye. To eliminate such systematic errors, special techniques have been developed by Micronic Mydata. Some mura suppressing techniques are described in this paper. Today, the race towards larger glass sizes has come to a halt and a new race - towards higher resolution and better image quality - is ongoing. The display mask is therefore going through a change that resembles what the semiconductor mask went through some time ago: OPC features are introduced, CD requirements are increasing sharply and multi tone masks (MTMs) are widely used. Supporting this development, Micronic Mydata has introduced a number of compensation methods in the writer, such as Z-correction, CD map and distortion control. In addition, Micronic Mydata MMS15000, the world's most precise large area metrology tool, has played an important role in improving mask placement quality and is briefly described in this paper. Furthermore, proposed specifications and system architecture concept for a new generation mask writers - able to fulfill future image quality requirements - is presented in this paper. This new system would use an AOD/AOM writing engine and be capable of resolving 0.6 micron features.

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Un-repairable defects cause not only delivery delay but also un-negligible loss cost in Large Size Photo Mask (LSPM) Productions. In order to avoid such loss, Lasertec provides various types of inspection and repair systems. The Large Size Substrate inspection system LB79 works for qualifying substrates for LSPMs. In a LSPM maker, the resist coated blanks can be inspected with LIR79i, the In-process Inspection and Repair system. ADI (After Develop Inspection) also can be performed with the same LIR79i as well as Resist Pattern Repairs with the Laser shots and the ink dispensing.

As the feature size shrinks to sub-20nm, more advanced OPC technologies such as ILT and the new lithographic resolution by EUV become the key solutions for device fabrication. These technologies leads to the file size explosion of up to hundreds of gigabytes of GDSII and OASIS files mainly due to the addition of complicated scattering bars and flattening of the design to compensate for long range effects. Splitting and merging layout files have been done sequentially in typical distributed computing layout applications. This portion becomes the bottle neck, causing the scalability to become poor. According to the Amdahl's law, minimizing the portion of sequential part is the key to get the maximum speed up. In this paper, we present scalable layout dividing and merging methodologies: Skeleton file based querying and direct OASIS file merging. These methods not only use a very minimum memory footprint but also achieve remarkable speed improvement. The skeleton file concept is very novel for a distributed application requiring geometrical processing, as it allows almost pseudo-random access into the input GDSII or OASIS file. Client machines can make use of the random access and perform fast query operations. The skeleton concept also works very well for flat input layouts, which is often the case of post-OPC data. Also, our OASIS file merging scheme is a smart approach which is equivalent of a binary file concatenation scheme. The merging method for OASIS files concatenates shape information in binary format with basic interpretation of bits with very low memory usage. We have observed that the skeleton file concept achieved 13.5 times speed improvement and used only 3.78% of memory on the master, over the conventional concept of converting into an internal format. Also, the merging speed is very fast, 28MB/sec and it is 44.5 times faster than conventional method. On top of the fast merging speed, it is very scalable since the merging time grows in linear fashion with respect to the file size. Our experiment setup includes hundreds of gigabytes of GDSII and OASIS files. We demonstrate in the paper, that the skeleton file based querying and direct OASIS file-merging schemes are very scalable for distributed computing applications for large volume layout. Additionally, we used embedded skeleton file scheme to improve file loading speed in layout viewer system and achieved 61 time speedup. We used Nirmaan, SoftJin's post-layout EDA toolkit for skeleton file based querying, OASIS file-merging and embedded skeleton file schemes.

GPGPU (General Purpose Graphic Processor Unit) has been attracting many engineers and scientists who develop their own software for massive numerical computation. With hundreds of core-processors and tens of thousands of threads operating concurrently, GPGPU programs can run significantly fast if their software architecture is well optimized. The basic program model used in GPGPU is SIMD (Single Instruction Multiple Data stream), and one must adapt his programming model to SIMD. However, conditional branching is fundamentally not allowed in SIMD and this limitation is quite challenging to apply GPGPU to photomask related software such as MDP or MRC. In this paper unique methods are proposed to utilize GPU for MRC operation. We explain novel algorithms of mask layout verification by GPGPU.

Semiconductors technology trend to reduce critical features dimension has dramatically increased design file size. Design-tape-out flows have seen the introduction of Optical Proximity Correction (OPC) step that led to new files introduction, with an increase in the amount of data to be processed downstream in the flow. Today in 28 nm technology node, design post-OPC data files sizes reach hundreds of gigabytes. 20 nm technology node and below development is demonstrating that correction techniques complexity is increasing. That predicts new challenges in mask data preparation flow for advanced technology nodes. We have developed a mask data preparation flow designed to tackle the challenge of maintaining a consistent delivery time to mask shops, while using efficiently hardware investment. Addressing post-OPC data file size increase toward mask data preparation required innovations in data processing for fractured data files creation, and also in data review techniques. The paper will discuss these innovations and conduct a demonstration with results in a 28 nm technology node production flow. Cost-benefit analysis will be illustrated with runtime comparisons of fractured data creation, and data review between traditional mask data preparation flows and this specific flow.

In semiconductor industry, many wafer fabs acquire masks from qualified suppliers because they do not have in-house maskshops. Under the circumstances, for these fabs, their main objectives of mask supplier management are to carry out gaining stable quality performance with punctual delivery and acceptable prices. At present, interests in mask supplier management are launching into mask data preparation (MDP) field when it's beginning to face raised challenges to output correct results all the time. These incoming tasks are mainly due to increasingly complicated MDP demand from wafer fabs for implementing various approaches on masks and tape-out to support wafer production and tight cycle-time control. In this paper, it shows major factors of MDP quality issues from analyzing past accidents in our suppliers and proposes possible approaches for achieving further improvement.

Source mask optimization (SMO) emerged as powerful resolution enhancement technique (RET) for advanced technology nodes. However, there is a plethora of flow and verification metrics in the field, confounding the end user of the technique. Systemic study of different flows and the possible unification thereof is missing. This contribution is intended to reveal the pros and cons of different SMO approaches and verification metrics, understand the commonality and difference, and provide a generic guideline for RET selection via SMO. The paper discusses 3 different type of variations commonly arise in SMO, namely pattern preparation and selection, availability of relevant OPC recipe for freeform source and finally the metrics used in source verification. Several pattern selection algorithms are compared and advantages of systematic pattern selection algorithms are discussed. In the absence of a full resist model for SMO, alternative SMO flow without full resist model is reviewed. Preferred verification flow with quality metrics of DOF and MEEF is examined.

Influence of the mask error becomes serious because of the shrinkage of device pitch. The impact of mask line width roughness (LWR) on wafer CD needs to be studied on advanced node, because the device performance of semiconductor will be impacted seriously by wafer LWR/LER (line edge roughness). The Gate line width variation is a critical issue on advanced nodes. In this paper, we evaluate the LWR relationship between mask and wafer. We start the mask and wafer LWR study by simulation (aerial image model, and resist model) to see whether simulation meets optical theory. Besides, we also confirm the wafer printing result to compare simulation and wafer performance. Based on our study, simulation and wafer data show that the mask LWR has no obvious impact on wafer LWR even if on EUV (13.5nm wavelength) process.

Optical Proximity Correction (OPC) is a crucial step in Semiconductor manufacturing for technology of dimensions below the exposure wavelength. Light from the exposure source is diffracted when passing through mask dimensions below the exposure wavelength causing patterns on wafer to differ from the intent patterns. During OPC the design intent layout patterns are modified to compensate for light diffractions so that the final wafer patterns match the design intent patterns. OPC achieves this by using OPC models that model the optical conditions, resist, and etch behavior; and an OPC recipe that controls the patterns modification process. The OPC models are calibrated from test mask structures that are developed, exposed and measured when starting to set up the manufacturing process. Structures chosen to be placed on the test mask have a great impact on the capability to predict future layout patterns that were not present in the original test mask, referred to as model coverage. Test masks are usually composed of patterns used in model calibration and others used for verifying the calibrated model. In advanced technology nodes, both the feature size and the error budget are being shrunk. Hence to reach the best model coverage with acceptable accuracy, we need to ensure that the test mask contains all the possible structures in the real designs, while maintaining that the number of patterns does not consume long metrology tools time, cause extra overhead cost to the process, or delay the development cycle. This paper presents a systematic approach to optimize the number of patterns to be included in the test mask and split test patterns into calibration and verification patterns. Results from using the proposed method are compared to other methods of splitting that are based either on geometrical or random methods. The approach provided a significant reduction in model calibration time, the number of needed patterns in the test mask, and the total development process turn-around time; while maintaining the same accuracy that can be achieved from the original test patterns set.

Spin cleaning tools have advantages in cross contamination compared to bath cleaning tools. Although spin speed is one of key parameters to increase the cleaning efficiency of the spin cleaning tools, its optimization has been limited due to the generation of ESD (Electrostatic discharge) damage to optical masks. EUV masks, however, consist of more "stable" materials in terms of ESD damage so that it is allowed to increase spin speed to improve cleaning performance for EUV mask. In this paper, we showed particle removal efficiencies dependent on mask spin speed for megasonic, nano-binary, or the combination module of those two cleaning mechanisms. We also demonstrated that different characteristics of particle removal efficiency as a function of spin speed for megasonic and nano-binary cleanings can be predicted from simulation of particle trajectory in liquid medium and liquid hitting rates on mask spinning at various spin speeds. This work clearly signifies that it is possible to improve cleaning performance through optimization of known parameters.

As extreme ultraviolet lithography (EUVL) moves toward high volume manufacturing and pushes to increasingly smaller critical dimensions, achieving the stringent requirements for line edge roughness (LER) is increasingly challenging. For the 22 nm half-pitch node and beyond, the International Roadmap for Semiconductors requires less than 1.6 nm of line width roughness (LWR) on the wafer. The major contributor of this tight LWR is wafer resist LER and mask LER. However, in current ITRS, there is no guideline for mask LER. While significant progress has been made to reduce the resist of the LER on the wafer, it is not yet clear how much the mask LER should be improved for a 22 nm half-pitch node application. Additionally, there are various approaches to obtaining a smaller LER on the mask. It could be improved either by reducing well-known statistical noise or manipulating some process condition or material. Both approaches are effective in improving the LER, however, they shows a different result in mask CD uniformity itself. In this paper, in addition to setting the criteria of the mask LER, we will discuss how tight the mask LER is required to be and what kind of approach is desirable with regards to the LER and CD uniformity. Finally, an analysis of the LER and CD variation provides some insights into the impact of the next generation mask infrastructure.

The amount of sulfate ion on mask surface will increase haze defect growing once exposed by an ArF laser. And then the storage conditions influence amount of sulfate ion was investigated. Therefore, our evaluations used extraction method and IC (Ion Chromatography) test to examine the amount of ions for current mask pods and storage cabinet. The pods included the different material of ABS (Amber and Violet Acrylonitrile Butadiene Styrene), PMMA (Polymethyl meth acrylate), PEEK (Polyether ether ketone), Metal case, LCP (Liquid Crystal Plastic), PC+CF (Polycarbonate with carbon fiber) and PC+CNT (Polycarbonate with Carbon nano-tubes). Moreover, PSM (Phase shift Mask) haze life time and dosage was strongly interrelated with the amount of chemical contaminant aggregation for storage pods. The other factor to impact haze generation of ArF PSM masks is the condition of storage environment; therefore, we're comparing the different structure of cabinet from different vendors to extend mask life time. They included 3 types of storage system: cabinet with XCDA, purge cabinet and purge stocker. According to this point of view, we used the impinger and Cr Blank IC test to verify the best storage system and remove some of the polluted parts for cabinet to ensure haze free. Resulting from our investigations, we setup storage BKM (Best Known Method) and monitor haze performance to record their results. Consequently, the optimization components of storages will contribute the enormously economical benefit.

The problem of haze and related defects become more serious as the dimension of lithography becomes smaller. It has been reported that the causes of haze defects are organic and inorganic molecular contamination deposited on mask surface. These haze problems influence the productivity of lithography process, but the formation mechanism of haze has not been clear. So it is important to understand chemical composition and formation mechanism of haze to prevent it. To analyze the chemical composition, several analytical techniques are useful, that is, ion chromatography (IC) or gas chromatography mass spectrometer (GC/MS) after liquid extraction of mask surface, surface analysis such as time-of-flight secondary ionization mass spectrometry (TOF-SIMS), X-ray photon spectrometry (XPS) and so on. However, these techniques are all destructive methods and are difficult to evaluate the airborne molecular contaminants (AMCs) with high sensitivity between mask and pellicle. We have successfully developed new and sensitive analysis tool consists of two parts and applied it for the evaluation of micro-environment between photomask and pellicle. One is the equipment to collect AMCs effectively, that provides diagonal two holes with needles on the pellicle to collect the gas while ventilating the high-purity nitrogen gas. The other is sampler which is named BremS™ to collect and measure exhausted AMCs in the space with high sensitivity. We applied this method to masks with different exposure dosage rate and introduce the usefulness of our method.

Availability of Defect-free blank is one of the most critical issues for high volume mask production in EUV lithography. Blank defects will disrupt the structure of multi-layers and will cause phase defects in EUV lithography. Phase defects caused by the disruption in the structure of multi-layers are difficult to repair after identified by the pattern inspection tools. Defect density in blanks are improving year by year, but the current progress is still insufficient ^[1][2]. All EUV blanks should be inspected for qualification before blank suppliers can establish manufacture processes for defect-free EUV blanks with higher productivity. There are also techniques in EUV blank alignment to relax the specification of defect density on a blank ^[3][4]. The origin of the alignment is the coordinate defined by the fiducial marks which are prepared on the glass of low thermal expansion material (LTEM) or on the multi-layer of EUV mask substrate. A limited number of defects can be covered by absorber film of a pattern in this technique. We developed an optional function for EBM-8000 ^[5] to precisely align a blank based on the fiducial marks by electron beam (EB) prior to pattern writing. Two possible structures of fiducial marks, advocated by SEMI standard 4580, can be considered to be used for fiducial marks in EUV blanks. In this paper, the alignment accuracy of blanks will be discussed through alignment experiments with actual EUV blanks.

Placement error due to charging in electron beam lithography has been identified as the most important factor limiting placement accuracy in EBL, which is especially important in the fabrication of masks for double patterning. Published results from a few major companies demonstrated that the placement errors due to charging are far larger than 10 nm. Here, we will describe the results of predicting the charging placement error based on a significantly improved physical model. Specially designed patterns were used to characterize the details of the charging placement error. Reference marks were exposed before the exposure of the test pattern, during the exposure, and after the exposure was completed. The experimental results were used to calibrate the parameters of the physical model. Furthermore, the DISPLACE software was used to predict the placement error maps for other experiments. The results of the measurements and simulations are presented in this paper. The results produced by the software were in good agreement with the experimental measurements. When the amplitude and the direction of the placement error due to charging is predicted, it can be easily corrected using readily available software for mask data preparation, or directly in EBL writers.

As feature sizes of semiconductor device structures have continuously decreased, needs for metrology tools with high precision and excellent linearity over actual pattern sizes have been growing. And it has become important to measure not only two-dimensional (2D) but also three-dimensional (3D) shapes of patterns at 22 nm node and beyond. To meet requirements for 3D metrology capabilities, various pattern metrology tools have been developed. Among those, we assume that CDSEM metrology is the most qualified candidate in the light of its non-destructive, high throughput measurement capabilities that are expected to be extended to the much-awaited 3D metrology technology. On the basis of this supposition, we have developed the 3D metrology system, in which side wall angles and heights of photomask patterns can be measured with high accuracy through analyzing CDSEM images generated by multi-channel detectors. In this paper, we will discuss our attempts to measure 3D shapes of defect patterns on a photomask by using Advantest's "Multi Vision Metrology SEM" E3630 (MVM-SEM™ E3630).

EUV defect detectability is evaluated both through simulation and by conventional mask inspection tools at various wavelengths (13.5, 193, 257, 365, 488 and 532 nm). The simulations reveal that longer wavelength light penetrates deeper into the multilayer than shorter wavelength light, however this additional penetration does not necessarily provide an advantage over shorter wavelengths for detecting defects. Interestingly, for both blank and patterned mask inspections, each wavelength detected unique defects not seen at other wavelengths. In addition, it was confirmed that some of the defects that are detected only by longer wavelengths are printable. This study suggests that a combination of wavelengths may be the most comprehensive approach to finding printable defects as long as actinic inspection is not available.

Because the realization of defect-free Extreme Ultra-violet Lithography (EUVL) mask blanks is uncertain, the defect mitigation techniques are becoming quite important. One mitigation technique, "Pattern shift", is a technique that places a device pattern to cover multilayer (ML) defects underneath the absorber pattern in such a way that the ML defects are not printed onto wafers. This mitigation method requires the defect coordinate accuracy of down to tens of nanometers. Consequently, there is a strong demand for a Blank Inspection tool that is capable of providing such defect coordinate accuracy. To meet such requirement, we have started to develop a high accuracy defect locating function as an optional feature to our EUV Actinic Blank Inspection (ABI) system which is currently being developed aiming at HVM hp16 nm-11 nm node. Since a 26x Schwarzschild optics is used in this inspection tool, it is quite difficult to pinpoint defect location with high accuracy. Therefore we have decided to realize a high magnification review optics of 600x or higher by adding two mirrors to the Schwarzschild optics. One of the additional two mirrors is retractable so that the magnification can be switched according to the purpose of inspections. The high magnification review mode locates defect coordinates accurately with respect to the fiducial position. We set the accuracy target at 20 nm so that the mitigation technique can be implemented successfully. The optical configuration proposed in this paper allows both a high speed inspection for HVM and a high accuracy defect locating function to be achieved on one inspection system.

In order to realize pattern defect inspection for 1Xnm EUV mask, we are developing a novel projection electron microscopy (PEM) system; which enables us to make the inspection in high resolution and high speed as compared with conventional DUV and EB inspection systems. In this paper, we have cleared how progress is needed to the decided specification target, e.g., sensitivity of 16nm size in pattern defect and inspection speed of 19 hours/100mm square, as compared to the current PEM optics performance. Then, to achieve the progress, we made a new design concept, i.e., a novel PEM optics employing high electron energy as compared to the current PEM optics, and verifying the concept by using numerical estimations. The results show that the novel PEM optics design concept is capable to meet the progress and the target for 1Xnm EUV mask.

Photo lithography potential expands for 32nm node to 2xnm device production by the development of immersion technology and the introduction of phase shift mask, and NPI-6000 using 199nm laser source was developed to correspond to 2xnm node photo mask pattern inspection. On the other hand, EUV lithography with 13.5nm exposure wavelength is dominant candidate for the next generation lithography because of its excellent resolution for 1x half pitch (hp) node device. But, applying 199nm optics to complicated lithography exposure tool option for hp2x nm node and beyond, further development such as image contrast enhancement will be needed. Therefore, a new mask inspection tool, NPI-7000, has been developed. This tool can implement not only photo mask pattern (hp1x) inspection, but also EUV mask pattern inspection (hp2x) and blanks inspection with high throughput. In this paper, features of NPI-7000 and new developed technologies were described and applied results to EUV mask inspections were introduced.

Extreme Ultraviolet Lithography (EUVL) is a promising technology for the fabrication of ULSI devices with 20nm half-pitch node. One of the key challenges before EUVL is to achieve defect-free masks. There are three main categories of mask defects: multilayer defects which cause phase defects, absorber pattern defects, and particles during blank/mask fabrication or mask handling after mask fabrication. It is important to manage multilayer defect because small multilayer defects are difficult to be identified by SEM/AFM after mask patterning and can impact wafer printing. In this paper, we assess blank defect position error detected by 3^rd generation blank inspection tool, using blank defect information from blank supplier and 199nm wavelength patterned mask inspection tool NPI-7000. And we rank blank defect in the order of projection defect size to multilayer in order to estimate blank defect printability. This method avoids overestimating the number of potential killer defects that hardly be identified by SEM/AFM under the condition that EUV-AIMS is not available.

This paper presents results of the optimization of an EUV mask cleaning process and compares the results to data obtained on COG and EPSM masks using processes specifically designed for such masks. The key parameter investigated was cleaning efficiency, as measured in terms of Particle Removal Efficiency (PRE), CD shift and actinic reflectivity change. The PRE of 100%, 84%, and 80% was obtained for COG, EUV and HT-PSM masks, respectively. The CD change per clean cycle was 0.07nm. The feature damage limit was 50nm. Actinic reflectivity change in the range <0.1% per clean cycle was obtained for the process.

EUV blank inspection is the key technology for EUV mask fabrication. To assess blank inspection tools, it is important to obtain appropriate test blanks with properly characterized defect types. In this study, new programmed defect blank was fabricated with conventional programmed defect fabrication and several new methods for natural-like programmed defects. And defect characterization work has been conducted to verify the difference of conventional programmed defects and natural-like programmed defects, and confirmed wide range of defect sizes from minimum below 1nm-height × 18nm-width to micron order defects were successfully fabricated. Furthermore, the blank was inspected by Actinic Blank Inspection (ABI) tool and evaluated the effectiveness of the new defect fabrication methods. And it was confirmed that the new programmed defect showed similar characteristics as natural defects.

Poor solvent developers are effective for resolution enhancement on a polymer-type EB resist such as ZEP520A. Another way is to utilize "cold-development" technique which was accomplished by a dip-development technique usually. We then designed and successfully built a single-wafer spin-development tool for the cold-development down to -10degC in order to dissolve difficulties of the dip-development. The cold-development certainly helped improve ZEP520A resolution and hole CD size uniformity, and achieved 35nm pitch BPM patterns with the standard developer ZED-N50, but not 25nm pitch yet. By employing a poor solvent mixture of iso-Propyl Alcohol (IPA) and Fluoro-Carbon (FC), 25nm pitch BPM patterns were accomplished. However, the cold-development showed almost no improvement on the IPA/FC mixture developer solvent. This paper describes cold-development technique and a tool, as well as its results, for ZEP520A resolution enhancement to fabricate 1Xnm bits (holes) for EB master-mold for Nano-Imprinting Lithography for 1Tbit/inch² and 25nm pitch Bit Patterned Media development.

Extreme Ultra Violet (EUV) lithography is a leading candidate technology to succeed ArF lithography for high-volume manufacturing (HVM) in the next generation. A serious obstacle to the realization of EUV lithography is that the evaluation tool for EUV masks is insufficient. In particular, although the evaluation of mask pattern quality by means of an aerial image is essential for the supply of defect-free masks, timely establishment of EUV AIMS operation is difficult. We are developing a system that evaluates the printability to wafer of a mask pattern by a combination of mask pattern measurement using three-dimensional (3D) SEM and wafer image prediction using lithography simulation. The measurement of the mask pattern is a key technique of the system. It is performed by 3D-SEM, which enables the highly accurate measurement of the mask pattern sidewall angle using a tilted SEM image. Because EUV lithography is off-axis illumination on a mask pattern, the sidewall angle management of a mask pattern is important. Besides, 3D-SEM acquires a mask pattern image with high resolution and wide area. The wafer image can be predicted with high accuracy on the basis of the 3D mask pattern data, which are highly accurate and cover a wide area. In this paper, we describe the method of 3D mask pattern data measurement. Additionally, we report the experimental results concerning the 3D mask pattern measurements and the wafer image predictions.

Since the layout patterns on photomasks have been getting more and more complicated by OPC/RET processes, the mask patterns need to go through the verification to check the mask manufacturability even though the layout is 'DRC clean'. This verification process is called MRC (mask rule check). The fundamental functions required for MRC is relatively simple, such as narrow gap detection between patterns. SII NanoTechnology has been developing an MRC software product, SmartMRC^TM, and it is widely used in mask shops as MRC standard software. Recently, in addition to typical usages of MRC software, various realistic applications have been reported in order to solve problems related to mask fabrication process. In this paper, we introduce three applications of MRC software for more efficient mask manufacturing.

Multiresolution writing refers to a technique used to simplify the data in one or more of the write passes performed by a vector-based e-beam writer while maintaining the detail in at least one of the remaining layers. This technique has been demonstrated to reduce the total shot count by as much as 30% with minimal predicted impact to the mask features formed, and no predicted impact to the wafer lithographic results. We investigate the impact of this technique on the mask manufacturing process. Specific mask parameters investigated include critical dimension uniformity, critical dimension proximity and linearity effects, line edge roughness, and mask inspectibility. Additional considerations include the applicability of this technique to existing mask designs as well as next generation RET solutions. This characterization identifies an operating regime where shot savings can be realized while still maintaining acceptable mask quality.

The new generations of photomasks are seen to bring more and more challenges to the mask manufacturer. Maskshops face two conflicting requirements, namely improving pattern fidelity and reducing or at least maintaining acceptable writing time. These requirements are getting more and more challenging since pattern size continuously shrinks and data volumes continuously grows. Although the classical dose modulation Proximity Effect Correction is able to provide sufficient process control to the mainstream products, an increased number of published and wafer data show that the mask process is becoming a nonnegligible contributor to the 28nm technology yield. We will show in this paper that a novel approach of mask proximity effect correction is able to meet the dual challenge of the new generation of masks. Unlike the classical approach, the technique presented in this paper is based on a concurrent optimization of the dose and geometry of the fractured shots. Adding one more parameter allows providing the best possible compromise between accuracy and writing time since energy latitude can be taken into account as well. This solution is implemented in the Inscale software package from Aselta Nanographics. We have assessed the capability of this technology on several levels of a 28nm technology. On this set, the writing time has been reduced up to 25% without sacrificing the accuracy which at the same time has been improved significantly compared to the existing process. The experiments presented in the paper confirm that a versatile proximity effect correction strategy, combining dose and geometry modulation helps the users to tradeoff between resolution/accuracy and e-beam write time.

EUV lithography with 13.5nm exposure wavelength is dominant candidate for the next generation lithography because of its excellent resolution for 16nm half pitch (hp) node device and beyond. High sensitivity EUV mask pattern defect detection is one of the major issues to realize the device fabrication by using the EUV lithography. In order to achieve the inspection sensitivity and the applicability for 1x node, a projection electron microscopy (PEM) system; which enables us to make the inspection in high resolution and high speed as compared with conventional DUV and EB inspection systems is employed. Applying the PEM system to 16nm hp node defect inspection, we designed the system with high electron energy, low aberration optics. To guarantee the quality of the 16nm node EUV mask, corresponding size programmed defect masks are designed, and PEM system defect detectability is evaluated by using the current system for 2X nm generation. Also, the defect printability is verified by simulation. In this paper, we described targeted defect detection size and show the specification of 16nm hp node PEM system and the verification.

We have developed actinic inspection systems to detect multilayer phase-defects with dark field imaging. Although a prototype system for full-field inspection is available for half-pitch (hp) 16 nm node from the viewpoint of inspection sensitivity, but the inspection time for such a full-field area of a mask requires 4.8 hours and hence the technique is not viable for a high-volume manufacturing (HVM) application. To reduce the inspection time of the prototype, its signal to noise ratio was analyzed. The result shows that an "n" times faster scanning speed would require an "n" times enhancement of the illumination intensity for the system. The intensity was enhanced by 1.7 times, by improving the optic efficiency of the system where full-field inspection time reduced from 4.8 hours to 3.25 hours, and where the detection probability was also improved. These results are applied towards the development of a HVM prototype, and for evaluating 11 nm node inspection techniques.

For extreme ultraviolet (EUV) mask evaluation, we have developed the coherent EUV scatterometry microscope (CSM), which is equipped with a laboratory coherent EUV source for high-harmonic generation (HHG) and acts as a standalone EUV tool. The CSM records the diffraction from mask patterns directly with a charge-coupled-device (CCD) camera, which was illuminated with the coherent EUV light. The pattern image and the critical dimension values are evaluated by using the diffraction image with iterative calculations based on coherent diffraction imaging. The 59th high-order harmonic generation at a wavelength of 13.5 nm was pumped by a tabletop 6 mJ, 32 fs, Ti:sapphire laser system. EUV output energy of 1 μW was successfully achieved. We observed the EUV mask using the HHG-CSM system. A very small 2 nm-wide line defect was successfully detected while located in an 88 nm line-and-space pattern.

Industry roadmaps indicate that the introduction of Extreme Ultraviolet Lithography (EUVL) is on track for high volume manufacturing. Although, there has been significant progress in each of the individual subsets of the EUVL infrastructure, the absolute management of the process outside of the scanner and up to the point-of-exposure has been highlighted as critical requirement for the adoption of EUVL. Significant changes in the EUV system environment and mask architecture are driving a zero process tolerance level. Any unforeseen contamination introduced to the scanner environment from the EUV mask could cause considerable downtime and yield loss. Absolute mask integrity at the point-of-exposure must be guaranteed. EUV mask cleaning processes-of-record have been developed and introduced to the industry [1]. The issue is not longer "how to clean the mask" but, "how to keep it clean". With the introduction of EUVL, mask cleanliness extends out beyond the traditional mask cleaning tool. Complete control of contamination and/or particles during transportation, handling and storage will require a holistic approach to mask management. A new environment specifically for EUV mask integrity must be developed and fully tested for the sub 16nm half-pitch node introduction. The SUSS MaskTrack® Pro (MTP) InSync was introduced as the solution for EUV mask integrity. SUSS demonstrated the fully automated handling of EUV masks into and out of a Dual Pod System [2]. Intrinsic cleanliness of each individual handling and storage step of the inner pod (EIP) and EUV mask inside the MTP InSync Tool was investigated and reported. A target specification of a PRP ≤ 0.08 as criterion for the cross contamination between EIP and the EUV reticle during handling within MTP InSync has been achieved and therefore proofing the applicability for the Dual Pod automation. Moreover an appropriate automated handling, other aspects like backside particle contamination and EIP cleanliness plays a significant role to ensure EUV mask integrity. With this concept in mind a system for particle detection has been integrated into MTP InSync. This allows verifying the POR performance for backside cleaning by measuring particles down to 150nm size. A dynamic capture rate of larger 97% at 200nm particle size based on PSLs was achieved; for EIP cleaning, a dry-cleaning technology is under investigation. During feasibility studies high particle removal efficiency (PRE) results larger 99% has been achieved for particles down to 100nm. In this paper, the full scope and roadmap of the MTP InSync will be discussed. Preliminary results of backside particle detection and challenges on EUV Inner Pod (EIP) cleaning will be presented.

EUV lithography is the most promising candidate for semiconductor device manufacturing of 1x nm half pitch and beyond. For the practical use, EUV mask with a thin absorber could be adopted because of less shadowing effect. EUV reflectivity from the thin absorber is about 1~3%. It would cause CD change on wafer especially at the exposure field edge due to the leakage of the EUV light from neighboring exposure shots.¹ To avoid this phenomenon, light shield black border is needed at the edge of pattern area on mask. Stacked absorber type and ML-etched type of light shield black border have been proposed in the past.² The most important things for these black borders are that there is no reflection of EUV light and no defect which affects pattern CD on wafer. ML-etched black border is considered to be applied for early practical use from a viewpoint of manufacturability. Because CD degradation and defect increase might happen due to 2^nd litho and etch process on its main pattern area in manufacturing process of stacked absorber type. In this paper, we will show several evaluation results regarding ML-etched black border we have developed. It has a good light shield performance for EUV and low DUV light reflection. Defect inspection in black border area can be performed successfully by three kinds of inspection tools. As a result, most of the defects seemed not to be printable to wafer. We also evaluated CD change, flatness change linked to mask IP shift and particle contamination on main pattern area. What it comes down to is that there is no show-stopper for ML-etched BB process for now.

A new method to evaluate the shadowing effect of 3-dimensional mask has been developed and implemented for extreme UV technology. The method is composed of several key ingredients. The illuminator(source) is divided into very small domains to account for the partial coherence nature of the illumination employed by the microchip industry. Each sub-domain acts as an incoherent source emitting a partial vector electromagnetic field. Since the design on the mask is described on a sub- nanometer(nm) grid and the features are 20-40nm, a non-uniformed grid is essential for a manageable computation. Consequently, the space describing the mask is a mixture of momenta(kx,ky) and physical space(z-direction). The corresponding Maxwell equations are translated to the mask space and the transmitted wave of each sub illuminator is propagated through the optical system. This construction eliminates the usual use of the Kirchhoff boundary conditions which are normally used in the formation of the aerial image. Instead the integration over the source(illuminator) takes place over the propagated field into the photoresist constructing the latent image directly. Employing a previously developed techniques the latent image is translated into photoacid concentration, enabling the determination of the developed photoresist structures. By using the described methodology, a shadowing effect is detected and by the usage of a newly developed optimization-scheme of the shape of the source the shadowing effect can be minimized or even eliminated.

The measurement and extraction method of phase-shift values for thin and thick absorber Extreme Ultra-Violet (EUV) masks has been studied by both of experiments and simulations. We fabricated 4 EUV masks with different absorber thicknesses. We first estimated the phase-shift values from the absorber thicknesses of each mask and the nandk values which were derived in advance by other experiments. This method is indirect and may contain plate-by-plate errors. In order to extract the phase-shift values directly, we developed a phase-shift measurement method based on scatterometry. We measured the reflectivity of the open and dark area of the 4 masks by using the EUV reflectometer at Lawrence Berkeley National Laboratory (LBNL). We also measured the diffracted light intensities of grating pattern. The phaseshift values were derived from these data assuming an interference of reflected and diffracted lights. We calibrated the method by including the shadowing effect of 6 degree incident angle, and adding the information on the measured mask patterns. The extraction results of phase-shift values by this method agreed well within the error bar. The absorber thickness having 180 degree phase-shift, which works as an embedded attenuated phase-shifting mask, could be somewhere between 66 nm and 76 nm. The measurement accuracy of this method depends on the phase-shift values. The error becomes the largest at 180 degree phase-shift, and the worst one in this experiment was much larger than the proposed phase-shift measurement accuracy of ± 2 degree ^[1]. Much effort will be required to achieve this target.

Bit Patterned Media (BPM) is essential of HDD media areal density increase, which will be combined with heatassisted magnetic recording (HAMR) eventually for thermal diffusion prevention. 1Tbit/inch² areal density is the first demonstration target, which is 25nm pitch hole array, for the BPM development. Nano-Imprinting Lithography (NIL) is indispensable too, so molds as well, for the BPM large-scale production for throughput. At the beginning, 52nm pitch and below was successfully made on quartz master-mold. However, by our comprehensive development and improvement in material and process, we successfully fabricate 25nm pitch master-mold by EB Lithography, 25nm pitch working-replica by Nano-Imprinting Lithography as well.