This PDF file contains the front matter associated with SPIE Proceedings Volume 8701, including the Title Page, Copyright Information, Table of Contents, and the Conference Committee listing.

In this paper, we report our modeling results of the resist surface charging effect on our newer e-beam mask writer EBM-8000. We show that our fundamental modeling scheme we have developed for EBM-6000 can be adapted on EBM-8000 platform without major modifications. We also discuss the significant differences in the charging effect between EBM-6000 and EBM-8000 in terms of its amplitude, its spatial distribution, and its dependency on the pattern density.

For multi-purpose applications such as advanced LSIs, photonics, MEMS, and other nano- fabrications, it is important for electron beam (EB) writers that handle the various substrates with their own single mechanical platform. We have been developing the adjusting pallet function both 200mm and 300mm bases to satisfy this requirement. By analyzing actual examples of adjusting pallets we proved their effectiveness to their applications. The combination of adjusting pallet function, 1Xnm resolution column and character projection technologies will enable the next generation EB writer “F7000” to fit from Fab to Lab applications.

Acoustic energy applied through the cleaning media results into two kinds of cavitation effects; namely stable and transient cavitation. A uniformly pulsating bubble transforms into stable cavitation behavior whereas a bubble implosion implies transient cavitation. Pattern damage of sensitive features on advanced masks as well as Ru pitting on EUVL reticles is mostly the result of transient cavitation. Stable cavitation on the other hand produces a very narrowly controlled energy distribution which allows cleaning without damage. Stable cavitation can be achieved by suitably tailoring physical, chemical and thermodynamic properties of the liquid and gas media. In this paper we investigate a new cleaning chemistry that has favorable physical and thermodynamic properties to produce stable MegaSonic cavitation. The cavitation created in this chemistry is characterized by measuring acoustic energy as well as by pattern damage and particle removal efficiency on mask level. The chemical properties (pH and zeta potential) of this chemistry are compared with conventional cleaning chemistries. Its effects on CD shift as well as phase and transmission loss are also studied.

Current and future lithography techniques require complex imaging improvement strategies. These imaging improvement strategies require printing of sub-resolution assist-features (SRAF) on photomasks. The size of SRAF’s has proven to be the main limiting factor in using high power Megasonic cleaning process on photomasks. These features, due to high aspect ratio are more prone to damage at low Megasonic frequencies and at high Megasonic powers. Additionally the non-uniformity of energy dissipated during Megasonic cleaning is a concern for exceeding the damage threshold of the SRAFs. If the cavitation events during Megasonic cleaning are controlled in way to dissipate uniform energy, better process control can be achieved to clean without damage. The amount and type of gas dissolved in the cleaning liquid defines the cavitation behavior. Some of the gases possess favourable solubility and adiabatic properties for stable and controlled cavitation behaviour. This paper particularly discusses the effects of dissolved Ar gas on Megasonic characteristics. The effect of Ar Gas is characterized by measuring acoustic energy and Sonoluminscense. The phenomenon is further verified with pattern damage studies.

We investigated methods to extend the damage-free process window for fragile Sub-Resolution Assist Features (SRAF) in mask cleaning using MegaSonic and binary spray techniques. Particle removal efficiency (PRE) was found to increase by 8% and damage reduced from 7 ppm to 0 ppm with the optimization of the spray droplet characteristics through liquid media control. MegaSonic damage was eliminated completely from 10 ppm to 0 ppm by varying physical and chemical properties of the cleaning media. Since particles in the deep trenches are very difficult to remove using droplet spray alone, a combination of MegaSonic and Binary Spray processes was tested. The acoustic effects generated through the MegaSonic combined with optimized droplet impact showed an improvement of 4% in PRE of hard-to-remove trench particles. Overall, the improved process points to a promising solution for overcoming the roadblock in mask cleaning for the advanced mask cleaning.

Most of defects generated in mask fabrication processes have been mainly created during each unit process. It becomes more important to detect and remove smaller defects on mask as pattern nodes keep shrinking. Each unit processes are getting not only more challenging to sustain mask quality and defect level but also more influencing on other processes for smaller pattern nodes. New type of defects based on such influences (crosstalk) between different processes is starting to emerge, which is requesting for a revision of defect reduction strategy because dealing with crosstalk defects is directly related with quality and TAT of mask manufacturing. It is relatively difficult to properly understand root-cause or working mechanism of defects generated by crosstalk between different processes. This is because interaction between different processes from defect generation perspectives has hardly been studied. In this paper, we introduce emerging progressive defects created while etched masks are undergoing cleaning process or subsequent events of moving to next process or temporary storage. We will investigate how etch gas residues on mask surface remaining after etching process interact with cleaning chemicals or moisture from subsequent process or environment to trigger defect generation and its growth. We will also examine effects of POD outgassing on generation of crosstalk progressive defect. Based on this understanding, appropriate solutions to mitigate defects caused by crosstalk between mask fabrication processes will be proposed. It is believed that new type of progressive defects caused by crosstalk between different mask fabrication processes will be more flourishing in the near future where mask blank materials, mask manufacturing processes, and chemicals need to diversify in order to meet much tighter specifications of mask quality. Therefore, it is very crucial to have right understandings on the interactions between various processes and eradicate possible root-causes of defect generations.

Computational techniques have been widely adapted in furthering resolution of optical lithography. Now such techniques are expanded into inspection and metrology with many new applications in mask houses and wafer Fabs enabling process advancement, improving process cycle time, and eliminating operator errors. One area of those applications is mask repair. Many times defects repaired do not pass the AIMS check therefore, the mask has to be reloaded back to repair tool to perform another round of repair and verification. Adding more loops of repair and AIMS check significant increases the mask cycle time and effectively reduces the potential throughput of the AIMS and repair tools. Ideally, the mask should not be removed from repair tool until all defects are repaired successfully. Simulation based In-situ Repair Qualifier (IRQ) was developed to meet this goal. IRQ takes SEM image of a repaired site and then simulates the aerial image using the exact scanner optical and illumination conditions (including free form sources). If the CD on the aerial image does not meet spec, the defect has to be repaired again until it does. By doing so, the chance of having repaired defects not meeting the AIMS spec is dramatically reduced or eliminated. In this paper, we will discuss the technical challenges in detail and present results demonstrating the accuracy and benefits of IRQ. Results on both programmed defects and real defects from product masks will be presented. The repair cycle time improvements and effective tool capacity gains before and after using IRQ are presented.

The ZEISS AIMS™ platform is well established as the industry standard for qualifying the printability of mask features based on the aerial image. Typically the critical dimension (CD) and intensity at a certain through-focus range are the parameters which are monitored in order to verify printability or to ensure a successful repair. This information is essential in determining if a feature will pass printability, but in the case that the feature does fail, other methods are often required in order to isolate the reason why the failure occurred, e.g., quartz level deviation from nominal. Atomic force microscopy (AFM) is typically used to determine physical dimensions such as the quartz etch depth and sidewall profile. In addition the AFM is a useful tool in monitoring and providing feedback to the repair engineer, as the depth of the repair is one of the many critical parameters which must be controlled in order to have a robust repair process. Carl Zeiss, in collaboration with Photronics-nanoFab, demonstrate the ability to use AIMS^TM to provide quantitative feedback on a given repair process; beyond simple pass/fail of the repair. Using the ZEISS MeRiT^® repair tool as the example, the AIMS^TM technique is used in lieu of an AFM to determine if repaired regions are over-etched or under-etched; and further to predict the amount of MeRiT^® recipe change required in order to bring subsequent repairs to a passing state.

The detection and management of mask defects which are transferred onto wafer becomes more important day by day. As the photomask patterns becomes smaller and more complicated, using Inverse Lithography Technology (ILT) and Source Mask Optimization (SMO) with Optical Proximity Correction (OPC). To evaluate photomask quality, the current method uses aerial imaging by optical inspection tools. This technique at 1Xnm node has a resolution limit because small defects will be difficult to detect. We already reported the MEEF influence of high-end photomask using wide FOV SEM contour data of "E3630 MVM-SEM_®" and lithography simulator "TrueMask_® DS" of D2S Inc. in the prior paper [1]. In this paper we evaluate the correlation between our evaluation method and optical inspection tools as ongoing assessment. Also in order to reduce the defect classification work, we can compose the 3 Dimensional (3D) information of defects and can judge whether repairs of defects would be required. Moreover, we confirm the possibility of wafer plane CD measurement based on the combination between E3630 MVM-SEM_® and 3D lithography simulation.

As design rule continues to shrink, microlithography is becoming more challenging and the photomasks need to comply with high scanner laser energy, low CDU, and ever more aggressive RETs. This give rise to numerous challenges in the semiconductor wafer fabrication plants. Some of these challenges being contamination (mainly haze and particles), mask pattern degradation (MoSi oxidation, chrome migration, etc.) and pellicle degradation. Fabs are constantly working to establish an efficient methodology to manage these challenges mainly using mask inspection, wafer inspection, SEM review and CD SEMs. Aerial technology offers a unique opportunity to address the above mask related challenges using one tool. The Applied Materials Aera3^TM system has the inherent ability to inspect for defects (haze, particles, etc.), and track mask degradation (e.g. CDU). This paper focuses on haze monitoring, which is still a significant challenge in semiconductor manufacturing, and mask degradation effects that are starting to emerge as the next challenge for high volume semiconductor manufacturers. The paper describes Aerial inspector (Aera3) early haze methodology and mask degradation tracking related to high volume manufacturing. These will be demonstrated on memory products. At the end of the paper we take a brief look on subsequent work currently conducted on the more general issue of photo mask degradation monitoring by means of an Aerial inspector.

Pattern matching seems to be promising technique to the mask industry. It can be used for many applications such as hot spot detection of post-OPC data, search of AIMS reference location or CDSEM measurement point extraction. In particular, fuzzy pattern matching is more needed for mask data processing because the mask layout has different derivatives generated by OPC and there are many similar "OPC brothers" that come from the same layout. However, application of fuzzy pattern matching to the mask layout is challenging due to the reasons related to the characteristics of photomask data. In this paper we introduce a novel method of fuzzy pattern matching to cope with the issues that comes from the characteristics of mask data. The rule specification is quite simple - we only need to specify a single tolerance value for each edge displacement. We will show the experimental results using the actual mask layout and prove that the calculation speed and quality of the proposed technique is satisfactory from the view point of realistic MDP processing.

Design complexity sometimes grows faster than EDA tools performances, and some innovation should be made on the design flow to guarantee the best possible validation in a reasonable time. This was the challenge we were facing for the final layout validation of a 3 billions transistors, multi cores chip designed for a 28nm process. The design backend validation requires multiple tools: the LVS to check connectivity, the DRC to check layout rules and the ERC to check any risk of power drop among the whole chip. While the 2 first tools are able to deal with huge designs by using hierarchical approaches, Electrical Rule Checking is much more complicated as the power routing is generally made flat at the top level of the chip. The classical ERC tools were not able to validate the power distribution at top level. The power distribution was made through a power grid using two metal layers and arrays of vias to connect each block at deeper metal layers. The chip is made of 256 processors and has a quite regular structure so that each module has it own power grid with the same pitch and every thing should be butting or properly connected at top level. It has then been decided to use a very efficient tool dedicated to geometrical verification of flat designs (typically a Mask Rule Checker) to check any interruption on power lines or missing vias in arrays. This paper will describe how this validation was performed as well as the performances obtained on a 28nm, 3 billions transistors design.

With the technology node progress, the requirements on mask data preparation become more and more stringent. Standard long range dose modulation starts showing difficulties to meet the specifications in terms of correction accuracy and the so called Model Based Data Preparation (MBDP) is gaining more and more interest in order to maintain the required pattern fidelity. This type of correction which often includes a geometry change on top of the dose modulation cannot be checked conventionally using standard Mask Rule Check software tools. A new methodology and software tool to perform verification after Model Based e-beam Proximity Correction is presented to overcome this issue. A basic functionality is to do verification at the shot level taking into account the possible movement of the edges as well as the dose assignment. A second brick allows going one step further: a Model-Based Verification is performed all over the edges of the design, checking by simulation the deviation of the printed pattern to the target after correction. The verification tool is capable to identify hot spots as well as deviations to the targeted design occurring with a very low frequency, making it almost impossible to spot without the systematic use of a verification tool. The verification can be inserted either in the maskshop flow or at the semiconductor manufacturer as a help for improving the OPC flow or as an complementary check to be run with the OPC check.

There are known VSB (Variable shape beam) mask writers in production today that require mask data with all angle edges to be approximated by staircases (stacked slits) in either a horizontal or vertical direction. The approximation uses 0, 45 or 90 degree edges, depending on the fracture setup and the angle of the edges in the original data. In order to gauge the effectiveness of the algorithm that fractures the original design to the VSB format, several methods can be employed to analyze the differences between the fractured data in the VSB format output and the original data before fracture. This is commonly referred to as skew error. This paper explores various methods and approaches that can be used, and examines each in detail. The goal is to highlight the differences and the effectiveness of each method in order to provide mask makers with the necessary information to make decisions best suited for their MDP-to-Lithography process flow. The first method explored is an XOR operation, followed by a double geometric biasing, aka Underover Sizing. The second method explored is an XOR operation, followed by a cut out of the differences starting from the unfractured polygon edges, aka Path Implode. The third method analyzed is an XOR operation, followed by measurement of the differences in the direction orthogonal to the unfractured edges, aka Difference Measurement. The fourth and last method analyzed is a mix of the last two, and employs an XOR operation, followed by measurement of the differences in the direction orthogonal to the unfractured edges, followed by a cut out of the measurement results, aka Measurement Implode.

There are two main technologies commercially available to write photomasks: Raster Scanning and Variable Shape Beam (VSB). For masks with features sizes that can be written on either kind of machine, it is advantageous to estimate the write time on both kinds of machines. The machine that is expected to have a faster Turn Around Time could be chosen. It is trivial to estimate how much time a design would take to be written by using a Raster Scanning machine. Since this kind of machine scans the whole design area, its TAT depends mainly on the size of the design and the size of the pixel. The write time is therefore mostly independent of the number of figures composing the design data. Estimating how long the same design would take to be written by a VSB machine is more involved, since its TAT depends greatly on how data is organized and fractured. In other words, there is a direct relation between number of elementary data figures (rectangles and trapezoids) and writing time. In VSB machines, data with curvilinear geometries can produce a huge increase in the amount of shots needed to write a design, which in turn directly affects TAT. This paper presents a novel technique used to provide the user with relevant information to aid with deciding which technology is to be used for writing the mask. The technique yields two vital pieces of information: a) An estimation of the amount of VSB Shots needed by a VSB Machine to write the design data into a photomask, and b) A map of where curvilinear geometries are located throughout the design.

For the mask making community, maintaining acceptable dose margin has been recognized as a critical factor in the mask-making process. This is expected to be more critical for 20nm logic node masks and beyond. To deal with this issue, model-based mask data preparation (MB-MDP) had been presented as a useful method to obtain sufficient dose margin for these complex masks, in addition to reducing shot count. When the MB-MDP approach is applied in the actual mask production, the prediction of the dose margin and the CD in the finished mask is essential. This paper describes an improved model of mask process which predicts dose margin and CD in finished masks better compared with the single Gaussian model presented in previous work. The better predictions of this simple numerical model are confirmed with simulation by D2S and actual mask written by HOYA using JEOL JBX-3200MV.

As the resolution of LCD panels adapted for Smartphone and Tablet PC rapidly becomes higher, the performance needed for lithography tools to produce them also becomes higher than ever. To respond to such needs, we have developed new lithography tools for mass production of high resolution LCD panels. We have executed various exposure tests to evaluate their performance. In this paper, we present the results of these tests. By employing higher NA projection optics, high resolution (2.0μm and under) has been achieved. We also present the effect of special illumination and the difference in profile between kinds of photoresist. Furthermore, we also refer what will be needed for masks and blanks in the next generation. To achieve even higher resolution, it is necessary for masks and blanks to have high flatness, low level of defects and small linewidth error.

Lasertec has developed CLIOS G821, a new inspection system designed to inspect finely-patterned large-size photomasks used for production of high-definition FPDs. CLIOS G821 is a highly advanced successor to 51MD, which has been acclaimed as a de facto industry standard of inspection tools for the 8th generation large-size photomasks. Photomasks are becoming more and more finely patterned due to the high demand for higher quality displays driven by strong sales in smartphones as well as the introduction of the latest 4K2K HDTV format. They are also becoming more complex and advanced by the use of half-toned masks and grey-toned masks. At the frontline of production, there is a strong need for a high-sensitivity inspection tool that is capable of detecting defects on the finely-patterned and highly-advanced photomasks. In order to meet such a need, Lasertec has redesigned optics, stage mechanism and detection circuit for CLIOS G821, offering high-sensitivity and high-throughput inspection for finely-patterned and highly-advanced photomasks. The presentation will describe the superior performance and functions of CLIOS G821 in comparison to our previous model, 51MD.

For those wafer fabs that have no their own maskshops, the main target of mask quality department is to gain stable mask quality performance through effective supplier management, and therefore achieves competitive business results. After dealing with lots of mask data preparation (MDP) quality problems with suppliers, we have found that incomplete change management procedures are one of major sources that induce incorrect mask data for writing. This article will share our experience in how to enhance change management flows with mask suppliers together and will also show the utility after a series of flow improvement actions.

For many maskshops, designed parallel mask data preparation (MDP) flows accompanying with a final data comparison are viewed as a reliable method that could reduce quality risks caused by mis-operation. However, in recent years, more and more mask data mistakes have shown that present parallel MDP flows could not capture all mask data errors yet. In this paper, we will show major failure models of parallel MDP flows from analyzing MDP quality accidents and share our approaches to achieve further improvement with mask suppliers together.

Designing a fully new 256 cores processor is a great challenge for a fabless startup. In addition to all architecture, functionalities and timing issues, the layout by itself is a bottleneck due to all the process constraints of a 28nm technology. As developers of advanced layout finishing solutions, we were involved in the design flow of this huge chip with its 3 billions transistors. We had to face the issue of dummy patterns instantiation with respect to design constraints. All the design rules to generate the “dummies” are clearly defined in the Design Rule Manual, and some automatic procedures are provided by the foundry itself, but these routines don’t take care of the designer requests. Such a chip, embeds both digital parts and analog modules for clock and power management. These two different type of designs have each their own set of constraints. In both cases, the insertion of dummies should not introduce unexpected variations leading to malfunctions. For example, on digital parts were signal race conditions are critical on long wires or bus, introduction of uncontrolled parasitic along these nets are highly critical. For analog devices such as high frequency and high sensitivity comparators, the exact symmetry of the two parts of a current mirror generator should be guaranteed. Thanks to the easily customizable features of our dummies insertion tool, we were able to configure it in order to meet all the designer requirements as well as the process constraints. This paper will present all these advanced key features as well as the layout tricks used to fulfill all requirements.

It is common knowledge that DFM guidelines require revisions to design data. These guidelines impose the need for corrections inserted into areas within the design data flow. At times, this requires rather drastic modifications to the data, both during the layer derivation or DRC phase, and especially within the RET phase. For example, OPC. During such data transformations, several polygon geometry changes are introduced, which can substantially increase shot count, geometry complexity, and eventually conversion to mask writer machine formats. In this resulting complex data, it may happen that notches are found that do not significantly contribute to the final manufacturing results, but do in fact contribute to the complexity of the surrounding geometry, and are therefore undesirable. Additionally, there are cases in which the overall figure count can be reduced with minimum impact in the quality of the corrected data, if notches are detected and corrected. Case in point, there are other cases where data quality could be improved if specific valley notches are filled in, or peak notches are cut out. Such cases generally satisfy specific geometrical restrictions in order to be valid candidates for notch correction. Traditional notch detection has been done for rectilinear data (Manhattan-style) and only in axis-parallel directions. The traditional approaches employ dimensional measurement algorithms that measure edge distances along the outside of polygons. These approaches are in general adaptations, and therefore ill-fitted for generalized detection of notches with strange shapes and in strange rotations. This paper covers a novel algorithm developed for the CATS MRCC tool that finds both valley and/or peak notches that are candidates for removal. The algorithm is generalized and invariant to data rotation, so that it can find notches in data rotated in any angle. It includes parameters to control the dimensions of detected notches, as well as algorithm tolerances and data reach.

In previous work, an approach was detailed using CATS-MRCC-RPM, where new pattern matching functionality is used to find locations on a jobdeck that are suitable for mark placements and ultimately, metrology tool measurement locations. These locations are found by first creating pattern definitions. The defined patterns are passed to the CATS MRCC-RPM match algorithm which in turn outputs all found locations that match the description. In that previous work, the pattern definitions, also known as mark templates, had several limitations. For example, each template could hold only one mark placed at its center, and had to be symmetrical. This was considered to be severely limiting in nature and not production worthy for advanced mask manufacturing. This paper builds on top of the previous one in various ways, extends the possibilities, and provides mask makers unlimited options for extending metrology automation. Mark templates are expanded upon to hold multiple marks at different offsets from its center, and even of different types. Each template can be symmetrical or asymmetrical, and yet all the marks on it can still be correctly placed by taking advantage of match orientation information during the Classification step. Placement of other mark types beyond basic ones is also explored, such as Arbitrary Area. Lastly, the classification step is an enhancement process that thoroughly manages the use of chip/mark information. The result makes use of the output of JD MRC (jobdeck MRC) which executes RPM on jobdecks by chip in order to reduce redundant chips processing, rather than search all chip placements by extension.

In semiconductor manufacturing, scribe frame data generally is generated for each LSI product according to its specific process design. Scribe frame data is designed based on definition tables of scanner alignment, wafer inspection and customers specified marks. We check that scribe frame design is conforming to specification of alignment and inspection marks at the end. Recently, in COT (customer owned tooling) business or new technology development, there is no effective verification method for the scribe frame data, and we take a lot of time to work on verification. Therefore, we tried to establish new verification method of scribe frame data by applying pattern matching and DRC (Design Rule Check) which is used in device verification. We would like to show scheme of the scribe frame data verification using DRC which we tried to apply. First, verification rules are created based on specifications of scanner, inspection and others, and a mark library is also created for pattern matching. Next, DRC verification is performed to scribe frame data. Then the DRC verification includes pattern matching using mark library. As a result, our experiments demonstrated that by use of pattern matching and DRC verification our new method can yield speed improvements of more than 12 percent compared to the conventional mark checks by visual inspection and the inspection time can be reduced to less than 5 percent if multi-CPU processing is used. Our method delivers both short processing time and excellent accuracy when checking many marks. It is easy to maintain and provides an easy way for COT customers to use original marks. We believe that our new DRC verification method for scribe frame data is indispensable and mutually beneficial.

EUV blank defect is one of the key issues the industry has to overcome to implement EUV lithography for HVM (high volume manufacturing). Several inspection techniques for EUV blank defect detection have been proposed, but the blank defect criteria for EUV mask is assumed to be very tight, thus, high sensitivity performance is required for blank inspection. However, it is important how the blank inspection tool to be assessed with appropriate test blanks with properly characterized defects. New programmed defect fabrication method has been introduced and verified that the method enables to fabricate natural-like programmed defects. In this study, it was attempted to fabricate more complex shape defects and investigated how multilayer defects are grown during multilayer deposition. Then, printability simulation was conducted for 3 different defect transition models, and critical multilayer defect shapes and sizes were discussed based on the simulation work.

Extreme Ultraviolet Lithography (EUVL) is a promising technology for the next generation lithography. It will be applied for half pitch 16nm node and beyond. The pattern resolution of recent EUV lithography is around hp20nm and next target is hp16nm. Although present requirement for EUV mask pattern resolution is hp64 nm, there is a special request to make under 40nm size pattern for EUV mask. One of examples is programmed phase defect mask (PDM). Phase defect of EUV blank affects large influence to wafer print result. Blank inspection is one of the key technology for EUV mask fabrication. To evaluate blank inspection tool, program defect mask is essential. Other examples are EUV mask for EUV diffraction exposure tool and EUV microscope evaluation. These masks need absorber pattern resolution of 30nm and smaller. In this paper, we will present process development results targeting 30nm size pattern. Programmed defect size achieved to 20nm width (FWHM: width at half maximum), 1.0nm height, both pit and bump defect. Absorber pattern resolution achieved 30nm half pitch. Not only simple dense line pattern, we fabricated radial pattern and any angle pattern.

In order to realize pattern defect inspection for 1Xnm EUV mask, we are developing a novel projection electron microscopy (PEM) system; which enables us to make the inspection in high resolution and high throughput as compared with conventional DUV and EB inspection systems. To achieve the specification target, e.g., sensitivity of 16nm size in pattern defect and inspection speed of 19 hours/100mm square, we have examined to clear the required progress as compared to the current optical system for PEM; In order to meet the required progress, we made a new design concept and developed a new optical system, which comprises an exposure and an imaging electron optics. In this paper, we describe the evaluation on the basic performance of the developed optical system as concerning to the required progress: 1) transmittances over 10 times on the developed exposure optics and over 2 times on the developed imaging optics; 2) electron imaging being higher energy over 5 times and MTF inclination in hp44～64nm L/S pattern. The results show the developed optical system on the novel PEM is capable to meet the progress for 1Xnm EUV mask inspection.

EUVL scanner throughputs are calculated considering a higher mask magnification. The calculation results show that the throughput of 8X mask system is 60-70% of that of 4X mask system. However the relative throughput compared to the 4X is higher if the duty cycle is considered as the input EUV power. The throughput is also estimated considering a 450mm wafer. Additionally the throughput for a twin reticle stage system using two 8X 6” masks is estimated for the case of stitching exposure.

Projection lithography using a liquid crystal display panel in place of a reticle is expected as a low-cost reticleless patterning method. Here, a simple but useful new exposure system using a projector with highly minute liquid crystal display panels is proposed. A projector with a light source and red, green and blue liquid crystal display panels was used as it was, and a set of two commercial macro-lenses was attached as reduction projection optics. The exposure system was evaluated by printing various patterns. Positive OFPR-800 (Tokyo Ohka Kogyo) was used as a resist. The diameter of the exposure field was approximately 6 mm. As a result, line patterns with a minimum width of 14 μm were clearly resolved. However, noticeable partial exposure unevenness was observed for patterns with a width of 40 μm or less. Because applications using large patterns with widths of 100-200 μm are aimed at hand, it is not a problem, and patterns with such large sizes are sharply and homogeneously printed even if they are considerably complicated.

Various technologies such as multiple patterning (MP) are being developed to extend the current DUV optical lithography to deal with the delay of next generation lithography such as EUV and NIL. Likewise, it is necessary to continue to develop technologies for mask inspection tools for masks fabricated for the DUV optical lithography so that they can be appropriately inspected, until the next generation EB or EUV actinic inspection tools is put into practical use. To fabricate 1x nm devices with the present lithography process, the industry will likely further extend double patterning (DP) to multiple patterning (MP). For MP, the requirements for the inspection sensitivity of traditional defects such as intrusions or extrusions do not change much, but those for CD control and overlay tolerances will become more critical. In this paper, we will discuss the main features of NPI-7000, a DUV based mask inspection tool for the 1x nm node devices, and our challenges in enhancing the CD error sensitivities to enable the inspection of masks.

The prevailing industry opinion is that EUV Lithography (EUVL) will enter High Volume Manufacturing (HVM) in the 2015 – 2017 timeframe at the 16nm HP node. Every year the industry assesses the key risk factors for introducing EUVL into HVM – blank and reticle defects are among the top items. To reduce EUV blank and reticle defect levels, high sensitivity inspection is needed. To address this EUV inspection need, KLA-Tencor first developed EUV blank inspection and EUV reticle inspection capability for their 193nm wavelength reticle inspection system – the Teron 610 Series (2010). This system has become the industry standard for 22nm / 3xhp optical reticle HVM along with 14nm / 2xhp optical pilot production; it is further widely used for EUV blank and reticle inspection in R and D. To prepare for the upcoming 10nm / 1xhp generation, KLA-Tencor has developed the Teron 630 Series reticle inspection system which includes many technical advances; these advances can be applied to both EUV and optical reticles. The advanced capabilities are described in this paper with application to EUV die-to-database and die-to-die inspection for currently available 14nm / 2xhp generation EUV reticles. As 10nm / 1xhp generation optical and EUV reticles become available later in 2013, the system will be tested to identify areas for further improvement with the goal to be ready for pilot lines in early 2015.

EUV lithography is the leading candidate for chip manufacturing at sub 10nm technology node. EUV specifications for mask were derived from those of optical masks and are currently adjusted according to knowledge collected with respect to specific behavior of EUV masks and exposure process. Difference in application of optical and EUV masks - transmission vs. reflection lead to addition of parameters characterizing surface roughness of both capping layer covered multilayer mirror as well as absorber, tight specification of line edge roughness (LER), actinic reflectivity of the mask as well as critical dimension (CD) mean to nominal. Absence of pellicle at EUV masks is expected to result in more frequent cleaning of the mask and hence more pronounced changes of the mask properties due to the mask cleaning process. These assumptions are reflected in tighter specifications for clean process influence. Investigation of the clean process influence on the EUV relevant parameter identifies differences in CD shift between optical and EUV masks. The chemical composition of EUV mask surfaces; absorber and capping layer; not used at optical masks is reason, why change of line width can be observed, and is possibly responsible for differences in CD stability of commercially available EUV absorbers too. Combined with narrowing specifications for CD shift due to cleaning, the material properties may result in the need of material specific clean processes. In our work we investigate the root cause of the differences and check if one process can be used which covers both EUV material stacks at given CD shift specifications.

For EUVL mask with thinner absorber, it is necessary to make black border area in order to suppress the leakage of the EUV light from the adjacent exposure shots Black border of etched multilayer is promising structure in terms of light-shield capability and mask process simplicity. However, EUVL masks with this structure do not have electrical conductivity between the inside and the outside of black border. Inspection area including device patterns belongs to the inside of the black border. In case that quality check for EUVL masks is performed with E-beam inspection, the area is floating. As a result, electrification to mask pattern occurs and causes degradation of E-beam inspection accuracy when the mask is inspected by E-beam inspection tool. In this paper, we refine EUVL mask structure with black border of etched multilayer in order to improve electrical conductivity. We will show evaluation results of E-beam inspection accuracy, and discuss specifications of electrically conductive black border area.

EUV lithography has been investigated as one of the next generation lithography technologies for sub-20 nm patterning because of its high resolution capability. However, outgassing from EUV resists should be improved in order to prevent optic contamination and to implement EUV lithography for high-volume manufacturing. Recently, in e-beam lithography for fabrication of photomask, the resist related outgassing has been also considered as one of the critical issues like that of EUV resists. E-beam exposure dose has been increased gradually in order to make fine patterns with better resolution and line edge roughness. As a result, the total resist outgassing in the application of lower sensitive resists could be increased due to longer exposure time in high vacuum and higher amount of organic compounds such as a photoacid generator and a quencher during e-beam irradiation. Therefore, the study of e-beam resist outgassing needs to understand correlations between outgassed chemical components from resists and e-beam optic contamination. The outgassing evaluations of current three kinds of positive e-beam resists were performed by using a EUV outgassing machine. The commercial e-beam resists show less contamination results compared to that of general EUV resists, relatively. However, the outgassing of e-beam resists was increased with decreasing resist sensitivity. In this view point, the outgassing should be considered as one of the important properties of the newly developed chemically amplified e-beam resists. Therefore, these e-beam resist outgassing results could be used as important data for development of next generation e-beam resists with lower sensitivity, to prevent the e-beam exposure equipment contamination.

We have studied MVM (Multi Vision Metrology) -SEM^® E3630 to measure 3D shape of defects. The four detectors (Detector A, B, C and D) are independently set up in symmetry for the primary electron beam axis. Signal processing of four direction images enables not only 2D (width) measurement but also 3D (height) measurement. At last PMJ, we have investigated the relation between the E3630’s signal of programmed defect on MoSi-HT and defect height measured by AFM (Atomic Force Microscope). It was confirmed that height of integral profile by this tool is correlated with AFM. It was tested that E3630 has capability of observing multilayer defect on EUV. We have investigated correlation with AFM of width and depth or height of multilayer defect. As the result of observing programmed defects, it was confirmed that measurement result by E3630 is well correlated with AFM. And the function of 3D view image enables to show nm order defect.

We describe SEMATECH’s recent defect printability work categorizing native phase defects by type and dimension using a NXE3100 EUV scanner and DPS (Defect Printability Simulator) software developed by Luminescent Technologies. Since the critical dimension (CD) error on a wafer simulated by the DPS is strongly affected by the multilayer (ML) geometry, it was very important to select the optimal multilayer (ML) growth model for each defect. By investigating the CD results obtained from 27 nm HP node imaging on NXE3100 and comparing those with simulation results, it was clear that reconstructed ML geometry generated by the AFM measurement showed much better simulation accuracy than conformal ML geometry. In order to find a typical ML growth model to predict the best ML geometry for a given dimension and height of defect, we calibrated a general ML growth model with AFM data and obtained ML growth model parameters. Using the fitted ML geometry generated from ML growth model parameters, CD error for 22 nm HP node was simulated and the result showed that conformal ML geometry is good for 24 nm defect simulation while not appropriate for 36 nm defect simulation.

Extreme Ultraviolet Lithography (EUVL) is the leading candidate for next generation lithography. EUVL has good resolution because of the shorter wavelength (13.5nm). EUVL also requires a new and complicating mask structure. The blank complexity and substrate polishing requirements result in defects that are difficult to eliminate or repair. Due to these challenges, shifting the pattern so that absorber covers the multilayer defects is one option for mitigating the multilayer defect problem. We investigated the capability and effectiveness of pattern shifting using authentic layouts. The rough indication of, “how many of what size defects are allowable”, is shown in this paper based on the margin for the 11nm HP pattern. Only the twenty 300nm-sized defects are allowable for current location accuracy of the blank inspection and writing tools. On the other hand, sixty70nm-sized defects are allowable for the improved location inaccuracy. Furthermore we exercised the full process for pattern shift using a leading-edge 50 keV e-beam writer to confirm feasibility and it was successfully performed.

Computer simulation can be very useful for developing a better understanding of the printability of buried defects in EUVL masks. At present, the most widely used rigorous methods for this purpose are the finite-difference time-domain (FDTD) and the rigorous coupled wave analysis (RCWA) methods. However, both of these methods require huge computation resources to simulate large 3D EUVL masks accurately. In this paper, a new rigorous EMF simulator based on the pseudo-spectral time-domain (PSTD) method is discussed. PSTD is free from the grid-snapping and numerical-dispersion errors that plague FDTD and has an accuracy equal to that of RCWA. Also, PSTD requires relatively little computer memory and, furthermore, is well suited to parallization on both multi-core CPU and multi-GPU platforms.

EUV wavelength inspection tools are several years away from product release. Until then, the EUV Lithography (EUVL) community faces the challenge of inspecting EUV masks at non-actinic wavelengths. It is critical to understand how to improve mask inspectability and defect sensitivity. The absorber stack is one contributor, since changing the film stack modifies image contrast. To study the effect, masks were fabricated from three different film stacks on which the thickness of the low reflective and absorber layers vary. These three absorbers are identified in this paper as Type A, Type B and Type C. All blanks had the same Ru-capped multi-layer substrate beneath the absorber stack. Inspection contrast, defect sensitivity and inspectability were measured on a 193nm wavelength inspection tool. The focus of this paper will be on inspection at the 193nm wavelength; however, simulated wafer results at the 13.5 nm EUV exposure wavelength will be included to anchor the relevance of the mask inspection results. A comparison of the different absorber stacks, the ability to detect defects on the various masks, and how defects on these substrates prints on wafer will be provided. This work addresses the gap between EUVL mask inspection and wafer defect printability and how the two views differ relative to various absorber stacks.

Advanced 193nm DUV optical inspection tools that can cover 2Xnm HP node become more important and they are being tested to estimate their extendibility. We report DUV based inspection results evaluated and compared to wafer prints, as well as mask CD-SEM images in order to determine the size of printable defects that must be detected in each device node. Applied Materials® advanced Aera™ optical mask inspection tool that adapted a new optical technology enhancement was utilized to evaluate its inspection capability. The illumination conditions and pixel size were optimized to increase inspection sensitivity and reach detection requirements for not only critical defects that print on the wafer but also non-printing defects that indicate to a mask issue. Simulation was used to study suitable optical illumination conditions analyzing results to achieve the best performance for high-end EUV mask inspection toward next generation lithography.

EUV lithography with 13.5 nm exposure wavelength, because of its excellent resolution, is a leading candidate for the next-generation lithography for 16 nm half pitch (hp) node devices, and beyond. High-sensitivity EUV mask pattern defect detection is one of the major issues to realize device fabrication with EUV lithography. In order to achieve inspection sensitivity and attainability for 1X node, a projection electron microscopy (PEM) system is employed that enables us to do high-speed/ high-resolution inspection that is not possible with the conventional DUV or EB inspection systems. By selecting a higher electron energy in imaging by using Electron Optics (EO) exposure, and by applying a newly designed model to a basic PEM optics model, we have minimized the aberration in imaging that occurs when working with EO; and we have improved the related transmittance of such a system. Experimental results by showing designs for the improved transmittance were obtained by making electron throughput measurement. To guarantee the quality of the 16 nm node EUV mask, corresponding sized programmed defects on masks were designed, and a PEM system for defect detection was evaluated by using the developed EO.

Background level (BGL) of an actinic inspection image was analyzed. Backgrounds are referred to the lights scattered by the surface roughness of a mask blank, and BGL variations are attributed to tool-factors and mask-factors. The BGL variation due to the mask-factors was reproduced by simulation using the surface information obtained by AFM measurement. As a result of comparison between the experimental and simulated BGL intensities, the stacking structure was estimated to be the surface model; and the AFM measurement reflected only the roughness of the capping layer. Using the estimated stacking structure, mask surface roughness of 85 pm and 0.2 nm at rms was required for 11 nm and 16 nm nodes in the case of the surface model.

One of the most challenging tasks to make EUVL (Extreme Ultra Violet Lithography) a reality is to achieve zero defects for mask blanks. However, since it is uncertain whether mask blanks can be made completely defect-free, defect mitigation schemes are considered crucial for realization of EUVL. One of the mitigation schemes, pattern shift, covers ML defects under absorber patterns by device pattern adjustment and prevents the defects from being printed onto wafers. This scheme, however, requires accurate defect locations, and blank inspection tools must be able to provide the locations within a margin of the error of tens of nanometers. In this paper we describe a high accuracy defect locating function of the EUV Actinic Blank Inspection (ABI) tool being developed for HVM hp16 nm and 11 nm nodes.

In extreme ultraviolet (EUV) lithography, controlling the reflection phase of the mask pattern is important for enlarging the process window and for compensating for phase defects. And, there are shadowing effect owing to the oblique illumination which modifies reflection phase of absorber patterns. A phase imaging microscope is required to determine this actinic phase distribution. To this end, we have developed a coherent EUV scatterometry microscope (CSM) based on coherent diffraction imaging (CDI). The CSM consists of a coherent EUV source and a charge-coupled device (CCD) camera, which records the diffraction images from the mask pattern directly. The system is lensless and makes use of the inverse computations based on the intensity of the scattered radiation, instead of the image-forming optics, to retrieve the frequency-space phase data. This allows the aerial-image phase data to also be reconstructed. Using the CSM system, one can obtain the intensity and phase images of the sample pattern. In this study, we also reconstructed the phase images of line-and-space patterns that were free of the shadowing effect as well as of patterns in which shadowing occurred. In the case of the latter, shadowing could be observed clearly in the phase image. Finally, the phase image of a programmed phase defect was also reconstructed and its phase value evaluated quantitatively. Thus, the CSM system is powerful tool for developing phase-controlled masks.