This PDF file contains the front matter associated with SPIE Proceedings Volume PMJ, including the Title Page, Copyright information, Table of Contents, and Conference Committee listing.

In this paper we will describe the development of a new 12% high transmission phase shift mask technology for use with the 10 nm logic node. The primary motivation for this work was to improve the lithographic process window for 10 nm node via hole patterning by reducing the MEEF and improving the depth of focus (DOF). First, the simulated MEEF and DOF data will be compared between the 6% and high T PSM masks with the transmission of high T mask blank varying from 12% to 20%. This resulted in selection of a 12% transmission phase shift mask. As part of this work a new 12% attenuated phase shift mask blank was developed. A detailed description and results of the key performance metrics of the new mask blank including radiation durability, dry etch properties, film thickness, defect repair, and defect inspection will be shared. In addition, typical mask critical dimension uniformity and mask minimum feature size performance for 10 nm logic node via level mask patterns will be shown. Furthermore, the results of work to optimize the chrome hard mask film properties to meet the final mask minimum feature size requirements will be shared. Lastly, the key results of detailed lithographic performance comparisons of the process of record 6% and new 12% phase shift masks on wafer will be described. The 12% High T blank shows significantly better MEEF and larger DOF than those of 6% PSM mask blank, which is consistent with our simulation data.

The long-term development of electronics obliges increasingly tighter specifications for photomasks to meet the requirements of continuing miniaturization. We report on the influence of two different linear drive nozzle types A and B used for conducting the develop process on important mask properties, which comprise CD uniformity (CDU), loading behaviour, mean to target (MTT), iso-dense bias, line width roughness (LWR), linearity, resolution and defectivity. The results are presented for different resists, resist thicknesses and blank materials. First, the most important recipe parameters to ensure the best develop performance are defined and experimentally determined. Those critical factors are the nozzle scan speed over the mask, the develop time, the distance between nozzle and mask surface and the flow rate of the medium. It is demonstrated how these parameters can significantly affect the develop process performance. Dark loss experiments reveal that a more uniform resist removal takes place with the B kind of nozzle compared to that achieved with nozzle A. Based on the mask properties, the performances of two different nozzle types are compared. It is found that improvements with the B like nozzle can be achieved for CDU and loading. The presented nozzle type shows a promising approach to meet the requirements of future electronics.

We have been researching new mask blank materials for the next generation lithography (NGL) and developed a new mask blank with low-k phase shifter [1] [2]. The low-k phase shifter consists of only Si and N. In our previous work, we reported the advantages of developed SiN phase shift mask (PSM) [2]. It showed high lithographic performance and high durability against ArF excimer laser as well as against cleaning. In this report, we further verified its high lithographic performance on several types of device pattern. The SiN PSM had high lithographic performance compared with conventional 6% MoSi PSM. Exposure latitude (EL) and mask enhancement factor (MEEF) were especially improved on originally designed Gate, Metal and Via patterns.

NuFlare has started development of multi-beam mask writer MBM-1000 aiming to apply to N5 and to release in Q4 2017. MBM-1000 is based on large area projection optics with shaping aperture array plate, blanking aperture array (BAA) plate, single cathode and inline/realtime data path for vector data rasterization and bitmap dose correction. It is designed to accomplish higher throughput than EBM series (variable shaped beam (VSB) writers) with massive beam array, higher resolution by using 10-nm beam size and 10-bit dose control, and better writing accuracy with more write passes. Configuration of MBM-1000 and flow of data path processing are described. Write time estimation suggests MBM-1000 has advantage over VSB writer with shot count > 200 Gshot/pass and resist sensitivity >75 μC/cm². Printing test of 20 nm hp 1:1 line and space pattern with ZEP-520 resist showed better beam resolution of MBM-1000 alpha tool than EBM series.

In maskmaking, the main source of error contributing to placement error is charging. DISPLACE software corrects the placement error for any layout, based on a physical model. The charge of a photomask and multiple discharge mechanisms are simulated to find the charge distribution over the mask. The beam deflection is calculated for each location on the mask, creating data for the placement correction. The software considers the mask layout, EBL system setup, resist, and writing order, as well as other factors such as fogging and proximity effects correction. The output of the software is the data for placement correction. One important step is the calibration of physical model. A test layout on a single calibration mask was used for calibration. The extracted model parameters were used to verify the correction. As an ultimate test for the correction, a sophisticated layout was used for the verification that was very different from the calibration mask. The placement correction results were predicted by DISPLACE. A good correlation of the measured and predicted values of the correction confirmed the high accuracy of the charging placement error correction.

As the design rule becomes continuously smaller, the Hard OPC is being applied to pattern design in semiconductor production. Controllability of hard OPCed pattern’s quality directly affects to the performance of the device and yields of production. Critical Dimension Scanning Electron Microscopy (CD-SEM) is used to accurately confirm the Critical Dimension (CD) quality of the photomask. CD-SEM makes the pattern’s shape image by using secondary electrons information directly from the Mask surface and can measure CD values. Classically the purpose of CD-SEM measurement was to get one dimensional CD values. However it is difficult to guarantee complex hard OPCed pattern’s quality by using only one dimensional CD values because complexity of pattern design has been increased. To confirm and control the quality of hard OPCed pattern, the quality of pattern fidelity must be measured quantitatively. In order to overcome this difficulty we developed a new method to quantitatively evaluate the quality of pattern fidelity using EPE (Edge Placement Error) distance from the overlay between Target Design GDS and SEM GDS contour which is extracted from CD-SEM image. This paper represents how to define and analyze quantitatively the quality of complex hard OPCed pattern.

Mask profile of chromeless phase-shifting lithography (CPL) defined by OCD has been investigated. In CPL masks, unbalanced bombardments caused by different ion accelerations lead to the formation of micro-notch structures. A better understanding of micro-notch structures is essential for quality gating of mask processes to improve of CPL mask profiles. By measuring 12 of 16 elements of Mueller matrix, we are able to set up a model to simulate the depth of micro-notch structure profile which shows good correlation with TEM images. Moreover, values of CD, quartz etching depth and side wall angle acquired by OCD are presented and compared with those obtained by SEM, TEM and AFM, respectively.

The standard method for defect disposition and verification of repair success in the mask shop is through the utilization of the aerial imaging platform, AIMS^TM. The CD (Critical Dimension) deviation of the defective or repaired region as well as the pattern shift can be calculated by comparing the measured aerial images of this region to that of a reference. Through this analysis it can be determined if the defect or repaired region will be printed on the wafer under the illumination conditions of the scanner. The analysis of the measured aerial images from the AIMS^TM are commonly performed manually using the analysis software available on the system or with the help of an analysis software called RV (Repair Verification). Because the process is manual, it is not standardized and is subject to operator variations. This method of manual aerial image analysis is time consuming, dependent on the skill level of the operator and significantly contributes to the overall mask manufacturing process flow. AutoAnalysis (AA), the first application available for the FAVOR® platform, provides fully automated analysis of AIMS^TM aerial images [1] and runs in parallel to the measurement of the aerial images. In this paper, we investigate the initial AutoAnalysis performance compared to the conventional method using RV and its application to a production environment. The evaluation is based on the defect CD of three pattern types: contact holes, dense line and spaces and peripheral structure. The defect analysis results for different patterns and illumination conditions will be correlated and challenges in transitioning to the new approach will be discussed.

Design For Manufacturing (DFM) where the state-of-the-art nano-devices of the sub-20nm node to a subject, for each of the technology has been intricately sophisticated, comprehensive optimization to predict the performance of the device came become very important. [1] To get effective solutions on these subjects, one of the lithographic key is a nano Optical Proximity Correction (OPC) control with SMO technology, and another is TCAD approach using the most advanced computer simulations. And, it is very important to obtain DFM solutions by integrating both. On the other hand, to meet the needs of low-voltage drive and the characteristic variability reduction, in order to obtain a state-of-the-art device performance, the Fin-type transistors are introduced globally as the mainstream because of wider process control margin. This paper, from the point of view of the sub-20nm node DFM, the simulation are conducted on ArF-imm. technology with SMO in SPT, DPT and QPT on TachyonTM [2], and the guideline of design rules are obtained. Furthermore, the simulated transistor pattern shape are directly migrated into TCAD process flow on HyENEXSSTM [3]. Then calculated I-V characteristics on 6 transistors under the various parameters on TCAD, and finally summarized Static Noise Margin (SNM) of SRAMs. Here, various parameters that determine the performance of SRAMs (Fin width, height, angle, dopant concentrations, electric field strength, work function, drive voltage, and operation speed) are intentionally varied and calculated on the TCAD. This computational method is highly sophisticated DFM technology to predict for the leading-edge nano-devices toward for the sub-20nm nodes era [4] [5] [6] [7] .

As has been the case for many years and for the near future down to the 7-nm logic node, electron-beam (eBeam) mask writing is pushing the limits of acceptable write times and quality. The eBeam community has responded to these challenges through innovation, engineering and collaboration. In 2009, the eBeam Initiative was launched to provide a stronger voice and educational platform for eBeam technology within the photomask and semiconductor design and manufacturing ecosystem. For the fourth consecutive year, as the photomask community heads to the annual SPIE/BACUS Photomask Symposium in Monterey, the eBeam Initiative has conducted a survey on photomask-related trends and perceptions. This annual perceptions survey has been instrumental in confirming key areas to align the Initiative’s efforts on to guide the industry ecosystem forward in supporting the introduction of new eBeam technologies. At the request of the community, an additional mask survey was conducted this year by the eBeam Initiative to include trends on key mask metrics that help serve as a barometer for mask makers. The complete results of both surveys are available for download at www.ebeam.org. Below is a summary and analysis of the key findings.

At advanced technology nodes mask complexity has been increased because of large-scale use of resolution enhancement technologies (RET) which includes Optical Proximity Correction (OPC), Inverse Lithography Technology (ILT) and Source Mask Optimization (SMO). The number of defects detected during inspection of such mask increased drastically and differentiation of critical and non-critical defects are more challenging, complex and time consuming. Because of significant defectivity of EUVL masks and non-availability of actinic inspection, it is important and also challenging to predict the criticality of defects for printability on wafer. This is one of the significant barriers for the adoption of EUVL for semiconductor manufacturing. Techniques to decide criticality of defects from images captured using non actinic inspection images is desired till actinic inspection is not available. High resolution inspection of photomask images detects many defects which are used for process and mask qualification. Repairing all defects is not practical and probably not required, however it’s imperative to know which defects are severe enough to impact wafer before repair. Additionally, wafer printability check is always desired after repairing a defect. AIMS^TM review is the industry standard for this, however doing AIMSTM review for all defects is expensive and very time consuming. Fast, accurate and an economical mechanism is desired which can predict defect printability on wafer accurately and quickly from images captured using high resolution inspection machine. Predicting defect printability from such images is challenging due to the fact that the high resolution images do not correlate with actual mask contours. The challenge is increased due to use of different optical condition during inspection other than actual scanner condition, and defects found in such images do not have correlation with actual impact on wafer. Our automated defect simulation tool predicts printability of defects at wafer level and automates the process of defect dispositioning from images captured using high resolution inspection machine. It first eliminates false defects due to registration, focus errors, image capture errors and random noise caused during inspection. For the remaining real defects, actual mask-like contours are generated using the Calibre® ILT solution [1][2], which is enhanced to predict the actual mask contours from high resolution defect images. It enables accurate prediction of defect contours, which is not possible from images captured using inspection machine because some information is already lost due to optical effects. Calibre’s simulation engine is used to generate images at wafer level using scanner optical conditions and mask-like contours as input. The tool then analyses simulated images and predicts defect printability. It automatically calculates maximum CD variation and decides which defects are severe to affect patterns on wafer. In this paper, we assess the printability of defects for the mask of advanced technology nodes. In particular, we will compare the recovered mask contours with contours extracted from SEM image of the mask and compare simulation results with AIMS^TM for a variety of defects and patterns. The results of printability assessment and the accuracy of comparison are presented in this paper. We also suggest how this method can be extended to predict printability of defects identified on EUV photomasks.

The mask composition checking flow is an evolution of the traditional mask rule check (MRC). In order to differentiate the flow from MRC, we call it Mask Data Correctness Check (MDCC). The mask house does MRC only to identify process limitations including writing, etching, metrology, etc. There still exist many potential errors that could occur when the frame, main circuit and dummies all together form a whole reticle. The MDCC flow combines the design rule check (DRC) and MRC concepts to adapt to the complex patterns in today’s wafer production technologies. Although photomask data has unique characteristics, the MRC tool in Calibre® MDP can easily achieve mask composition by using the Extended MEBES job deck (EJB) format. In EJB format, we can customize the combination of any input layers in an IC design layout format, such as OASIS. Calibre MDP provides section-based processing for many standard verification rule format (SVRF) commands that support DRC-like checks on mask data. Integrating DRC-like checking with EJB for layer composition, we actually perform reticle-level DRC, which is the essence of MDCC. The flow also provides an early review environment before the photomask pattern files are available. Furthermore, to incorporate the MDCC in our production flow, runtime is one of the most important indexes we consider. When the MDCC is included in the tape-out flow, the runtime impact is very limited. Calibre, with its multi-threaded processes and good scalability, is the key to achieving acceptable runtime. In this paper, we present real case runtime data for 28nm and 14nm technology nodes, and prove the practicability of placing MDCC into mass production.

With shrinking pattern size, mask 3D effects are estimated to become stronger, such as horizontal/vertical shadowing, best focus shifts through pitch and pattern shift through focus. To reduce these mask 3D effects, we have proposed etched multilayer EUV mask structure and have also reported on the fabrication process of etched multilayer EUV mask, in which line and space mask patterning has been demonstrated. And by using etched multilayer EUV mask, the reduction of mask 3D effects is experimentally demonstrated. In our previous study, we have shown etched multilayer EUV mask has enough durability against chemical erosion in suitable cleaning process. In this work, to meet the demands of different variation on pattern in etched multilayer mask, especially fabrication process for sub-60nm pattern based on effective mirror width in dark-field exposure is studied. 60 nm pillar pattern on mask is obtained using negative tone resist with keeping resolution of line and space pattern. We also examined CD characteristics 60 nm line and space pattern in consideration of effective mirror width. This work represents that etched multilayer EUV mask is ready for dark-field exposure of 15 nm pattern in wafer.

High resolution patterning on the chip could be achieved by extreme ultraviolet lithography (EUVL). However, the defect on the mask becomes more important issue with very short wavelength (13.5 nm). Using the pellicle which could protect the mask from the defects can support high volume manufacturing (HVM). Most of the materials considered for pellicle have relatively high extinction coefficient in EUV region. Therefore, the thickness of the pellicle should be ~ nm thin. The stress of the pellicle is dependent not only on the temperature but also on the mechanical properties of the pellicle. The stress induced by the gravity was small compared to the thermal stress. However, the residual stress should be also considered since it is dependent on the pellicle manufacturing environment and this stress is comparable with the thermal stress. Our result shows the importance of the lowering the pellicle fabrication temperature in terms of the extending the lifetime during the scanning process.

Lithographic patterning at the 7 and 5 nm nodes will likely require EUV (λ=13.5 nm) lithography for many of the critical levels. All optical elements in an EUV scanner are reflective which requires the EUV photomask to be illuminated at an angle to its normal. Current scanners have an incidence of 6 degree, but future designs will be <6 degrees for high-NA systems. Non-telecentricity has been shown to cause H-V bias due to shadowing, pattern shift through focus, and image contrast lost due to apodization by the reflective mask coating. A thinner EUV absorber can dramatically reduce these issues. Ni offers better EUV absorption than Ta-based materials, which hold promise as a thinner absorber candidate. Unfortunately, the challenge of etching Ni has prevented its adoption into manufacturing. We propose a new absorber material that infuses Ni nanoparticles into the TaN host medium, allowing for the use of established Ta etching chemistry. A thinner is absorber is created due to the enhanced absorption properties of the Ni-Ta nano-composite material. Finite integral method and effective medium theory-based transfer matrix method have been independently developed to analyze the performance of the nano-composite absorption layer. We show that inserting 15% volume fraction Ni nanoparticles into 40-nm of TaN absorber material can reduce the reflection below 2% over the EUV range. Numerical simulations confirm that the reduced reflectivity is due to the increased absorption of Ni, while scattering only contributes to approximately 0.2% of the reduction in reflectivity.

Lithography has been generally used for printing two-dimensional patterns on flat wafers. Recently, however, it is also applied to a three-dimensional patterning for fabricating various MEMS (Micro Electro Mechanical Systems) components. The purpose of this research is to develop a new method for fabricating micro-lens arrays. At first, resist (Tokyo Ohka Kogyo, PMER LA-900PM) mold patterns with densely arrayed square or hexagonal concaves were replicated by intentionally shifting the focal position of projection exposure. The size of resist-mold was 2 mm square, and the initial thickness of the resist was 10 μm. Next, the wafer with the concave resist patterns was cut into small chips, and each wafer chip was fixed at the bottom of a paper cup using an adhesive tape. Then the epoxy resin (Nissin resin, Crystal resin Neo) was poured on the concave resist-mold patterns, and the resin was coagulated. Afterward, the hardened resin was grooved along the wafer chip using a cutter knife, and the wafer chip with the resist-mold patterns was forcibly removed using a pair of tweezers. Finally, both sides of the resin block were polished, and the thickness was reduced. Although the transparency and roughness of the resin block surfaces should be improved, epoxy micro-lens arrays were certainly fabricated. The mean values of curvature radius and lens height were 28.3μm and 4.9 μm, respectively.

Lithographical patterning on the surface of a thin pipe is required for fabricating three-dimensional micro-parts. For this reason, a new exposure system for printing patterns on a cylindrical pipe by synchronous scan-projection exposure was developed. Using the exposure system, resist patterns with a width of 100 μm were printed on a surface of stainless-steel pipe with a diameter of 2 mm. The exposure time was 30 s. Printed resist pattern widths were measured in the axial and circumferential directions. As a result, pattern widths were almost uniform in both axial and circumferential directions. Judging from the experimental results, it was clarified that the patterning technology had a potential to be applied to fabrications of bio-medical devices and micro-parts.

It is required to develop a simple but effective method for fabricating micro components with cylindrical shapes such as spring parts used for contact-probe springs of electrical testing systems. Here, laser-scan lithography was researched for printing fine resist patterns used for etching masks on ultra-fine stainless-steel pipes with a diameter of 100 μm. At first, a pipe was coated with 3-μm thick positive resist. Second, the resist is exposed to laser light. As the laser light source, a violet laser with a wavelength of 408 nm was used. The laser beam was reshaped in a circle, and irradiated on the pipe by reducing it in 1/20 using a reduction projection optics composed of a 10X objective lens and a 2X imaging lens. The pipe was supported by the chuck of rotation stage, and exposured by moving it up and down and rotating it. The pipe position was adjusted as the laser spot came on the pipe center using the XY stage. Linearly arrayed 22 slit patterns with a length of 180 μm and a separation of 70μm were printed at each 90° rotation angle. That is, 88 slits in total were delineated at an exposure speed of 110 μm/s.

In order to minimize the defects formation when using nano-imprinting process we investigated the efforts applied on the resist during the release of the template. Lift-off release has already been characterized accurately but for peeling studies are still lacking. However from experimental results it has been observed that peeling offers better performances when it comes to limit the defects. Using finite element method we simulated imprinting on PMMA resist by a silicon template and extracted the maximal release force and the induced stress in the resist in regard to the template stiffness and the number of patterns imprinted. Compared to lift-off method we found that maximal release force was much lower and decided to investigate the induced stress behaviour. We observed that using peeling the maximal release force doesn’t increase linearly in function of the template size as in lift-off but instead saturates beyond a certain template size, that saturating point depending on the template stiffness, a low stiffness meaning a lower maximal release force. However we found an opposite trend when we extracted the induced stress in the resist which decreases as the template stiffness increases, theoretically resulting in fewer defects. This seems to be due to the smaller bending of the more rigid template that put less constraint on the imprinted features during the releasing and thus avoid breaking them in the process. Therefore according to these results, to minimize defects when peeling release method is employed we should use a highly rigid template.

The sensitivity and the resolution are affected by not only the nature of the resist such as a chemical structure and a molecular weight but also the developing process such as a developer molecular size. Exposure characteristics of positive-tone polymer resists having various molecular weights (Mw’s) ranging from 60 k to 500 k are investigated using different ester solvents as a developer. The line-and-space (L/S) patterns are exposed by the electron beam writing system with an acceleration voltage of 50 kV and the samples are developed by amyl acetate, hexyl acetate and heptyl acetate. The pattern shape becomes better and the surface of the resist also becomes smoother with increasing developer molecular size, though the exposure dose required for the formation of the L/S pattern increases. The dose margin of pattern formation is also wider in all the resists having the different molecular weights. The dissolution in the unexposed portions of the 60k-Mw resist for heptyl acetate is reduced significantly compared with those for amyl acetate and hexyl acetate. The improvement of the pattern shape and the increasing of dose margin are remarkable in the low molecular weight resist. The 3σ of line width roughness tends to be smaller in the higher molecular weight resist and with the larger molecular size developer. Exposure experiment of the 35 nm pitch pattern using the 500k-Mw resist developed at the room temperature is presented.

Extreme ultraviolet lithography (EUVL) is a promising technique for 1X nm half-pitch (hp) generation lithography. The inspection of patterned EUVL masks is one of the main issues that must be addressed during mask fabrication for manufacture of devices with 11 nm hp feature sizes. We have already designed projection electron microscope (PEM) optics that have been integrated into a new inspection system called Model EBEYE-V30 (where “Model EBEYE” is an EBARA’s model code) and this system seems quite promising for 16 nm hp generation EUVL patterned mask inspection. The defect inspection sensitivity of this system was evaluated via capture of an electron image that was generated at the mask by focusing the image through the projection optics onto a time-delay integration (TDI) image sensor. For increased throughput and higher defect detection sensitivity, a new electron-sensitive area image sensor with a high-speed data processing unit, a bright and stable electron source, and a simultaneous deflector for the image capture area that follows the mask scanning motion have been developed. Using a combination of synchronous deflection and mask scanning, the image can be integrated into both the fixed area image sensor and the TDI image sensor. We describe our experimental results for EUV patterned mask inspection using the above system. Elements have been developed for inspection tool integration and the designed specification has been verified. The system performance demonstrates the defect detectability required for 11 nm hp generation EUVL masks.

EUV developed in the last decade to the most promising <7nm technology candidate. Defects are considered to be one of the most critical issues of the EUV mask. There are several contributors which make the EUV mask so different from the optical one. First one is the significantly more complicated mask stack consisting currently of 40 Mo/Si double layers, covered by Ru capping layer and TaN/TaO absorber/anti-reflective coating on top of the front face of the mask. Backside is in contrary to optical mask covered as well by conductive layer consisting of Cr or CrN. Second contributor is the fact that EUV mask is currently in contrary to optical mask not yet equipped with sealed pellicle, leading to much higher risk of mask contamination. Third reason is use of EUV mask in vacuum, possibly leading to deposition of vacuum contaminants on the EUV mask surface. Latter reason in combination with tight requirements on backside cleanliness lead to the request of frequent recleaning of the EUV mask, in order to sustain mask lifetime similar to that of optical mask. Mask cleaning process alters slightly the surface of any mask - binary COG mask, as well as phase shift mask of any type and naturally also of the EUV mask as well. In case of optical masks the changes are almost negligible, as the mask is exposed to max. 10-20 re-cleans within its life time. These modifications can be expressed in terms of different specified parameters, e.g. CD shift, phase/trans shift, change of the surface roughness etc. The CD shift, expressed as thinning (or exceptionally thickening) of the dark features on the mask is typically in order of magnitude 0.1nm per process run, which is completely acceptable for optical mask. Projected on the lifetime of EUV mask, assuming 100 clean process cycles, this will lead to CD change of about 10nm. For this reason the requirements for EUV mask cleaning are significantly tighter, << 0.1 nm per process run. This task will look even more challenging, when considering, that the tools for CD measurement at the EUV mask are identical as for optical mask. There is one aspect influencing the CD shift, which demands attention. The mask composition of the EUV mask is significantly different from the optical mask. More precisely there are 2 materials influencing the estimated CD in case of EUV mask, whereas there is one material only in case of optical masks, in first approximation. For optical masks, the CD changes can be attributed to modification of the absorber/ARC layer, as the quartz substrate can be hardly modified by the wet process. For EUV Masks chemical modification of the Ru capping layer - thinning, oxidization etc. are rather more probable and we need to take into account, how this effects can influence the CD measurement process. CD changes measured can be interpreted as either change in the feature size, or modification of the chemical nature of both absorber/ARC layer stack and the Ru capping layer. In our work we try to separate the effect of absorber and Ru/capping layer on the CD shift observed and propose independent way of estimation both parameters.

EUV lithography is the most promising technology for semiconductor device manufacturing of the 10nm node and beyond. The image border is a pattern free dark area around the die on the photomask serving as transition area between the parts of the mask that is shielded from the exposure light by the Reticle Masking (REMA) blades and the die. When printing a die at dense spacing on an EUV scanner, the reflection from the image border overlaps edges of neighboring dies, affecting CD and contrast in this area. This is related to the fact that EUV absorber stack reflects 1-3% of actinic EUV light. To reduce this effect several types of image border with reduced EUV reflectance (<0.05%) have been proposed; such an image border is referred to as a black border. In particular, an etched multilayer type black border was developed; it was demonstrated that CD impact at the edge of a die is strongly reduced with this type of the black border (BB). However, wafer printing result still showed some CD change in the die influenced by the black border reflection. It was proven that the CD shift was caused by DUV Out of Band (OOB) light from the EUV light source. New types of a multilayer etched BB were evaluated and showed a good potential for DUV light suppression. In this study, a novel BB called ‘Hybrid Black Border’ (HBB) has been developed to eliminate EUV and DUV OOB light reflection by applying optical design technique and special micro-fabrication technique. A new test mask with HBB is fabricated without any degradation of mask quality according to the result of CD performance in the main pattern, defectivity and cleaning durability. The imaging performance for N10 imaging structures is demonstrated on NXE:3300B in collaboration with ASML. This result is compared to the imaging results obtained for a mask with the earlier developed BB, and HBB has achieved ~3x improvement; less than 0.2 nm CD changes are observed in the corners of the die. A CD uniformity budget including impact of OOB light in the die edge area is evaluated which shows that the OOB impact from HBB becomes comparable with other CDU contributors in this area. Finally, we state that HBB is a promising technology allowing for CD control at die edges.

Contact-hole layer patterning is expected to be one of the first applications for EUV lithography. Conventional darkfield absorber masks, however, are extremely inefficient for these layers, placing even more burden on the already challenging source power demands. To address this concern, a checkerboard phase shift mask configuration has been proposed yielding theoretical throughput gains of 5x assuming a thin-mask modeling. In this manuscript we describe the fabrication of such a mask and demonstrate its imaging performance using the SHARP EUV microscope and MET exposure tool at Lawrence Berkeley National Laboratory. For 25-nm dense features, the phase shift mask was shown to provide a throughput gain of 8x based on SHARP and 7x based on the Berkeley MET. The higher then predicted gain is expected to be due to the fact that the thin mask modeling used in the initial prediction misses shadowing effects.

Several challenges hinder extreme ultraviolet lithography (EUVL) photomask fabrication and its readiness for high volume manufacturing (HVM). The lack in availability of pristine defect-free blanks as well as the absence of a robust mask repair technique mandates defect mitigation through pattern shift for the production of defect-free photomasks. The work presented here provides a comprehensive look at pattern shift implementation to intersect EUV HVM for the 7 nm technology node. An empirical error budget to compensate for measurement variability and errors, based on the latest HVM inspection and write tool capabilities, is first established and then experimentally verified. The validated error budget is applied to 20 representative EUV blanks and pattern shift is performed on fully functional 7 nm node chip designs. The probability of defect-free masks is explored for various layers, including metal, contact, and gate cut layers. From these results, an assessment is made on the current viability of defect-free EUV masks and what is required to construct a complete defect-free EUV mask set.

TNO is building EBL2 as a publicly accessible test facility for EUV lithography related development of photomasks, pellicles, optics, and other components. EBL2 will consist of a Beam Line, an XPS system, and sample handling infrastructure. EBL2 will accept a wide range of sample sizes, including EUV masks with or without pellicles. All types of samples will be loaded using a standard dual pod interface. EUV masks returned from EBL2 will retain their NXE compatibility. The Beam Line provides high intensity EUV irradiation from a Sn-fueled EUV source. EUV intensity, pupil, spectrum, and repetition rate are all adjustable. In-situ measurements by ellipsometry will enable real time monitoring of the sample condition. The XPS will be capable of analyzing the full surface area of EUV masks and pellicles, as well as performing angle resolved analysis on smaller samples. Sample transfer between the XPS and the Beam Line will be possible without breaking vacuum.

Due to the impact on image placement and overlay errors inherent in all reflective lithography systems, EUV reticles will need to adhere to flatness specifications below 10nm for 2018 production. These single value metrics are near impossible to meet using current tooling infrastructure (current state of the art reticles report P-V flatness ~60nm). In order to focus innovation on areas which lack capability for flatness compensation or correction, this paper redefines flatness metrics as being “correctable” vs. “non-correctable” based on the surface topography’s contributions to the final IP budget at wafer, as well as whether data driven corrections (write compensation or at scanner) are available for the reticle’s specific shape. To better understand and define the limitations of write compensation and scanner corrections, an error budget for processes contributing to these two methods is presented. Photomask flatness measurement tools are now targeting 6σ reproducibility <1nm (previous 3σ reproducibility ~3nm) in order to drive down error contributions and provide more accurate data for correction techniques. Taking advantage of the high order measurement capabilities of improved metrology tooling, as well as computational capabilities which enable fast measurements and analysis of sophisticated shapes, we propose a methodology for the industry to create functional tolerances focused on the flatness errors that are not correctable with compensation.

Nano imprint lithography (NIL) is one to one lithography and contact transfer technique using template. Therefore, the lithography performance depends greatly on the quality of the template pattern. In this study, we investigated the resolution and the defect level for hole patterning using chemical amplified resists (CAR) and VSB type EB writer, EBM9000. To form smaller pattern with high quality, high resolution resist process and high sensitivity etching process are needed. After these elements were optimized, we succeeded to form 24 nm dense hole pattern on template. In general, it is difficult to suppress the defect density in a large area because of fogging effect and process loading and so forth. However, from the view point of defect quality, 26 nm hole pattern is achieved to form with practical level in a large area. Therefore, we indicate the capability of forming 26 nm hole master template which will be required in 2019 from ITRS2013. These results show that this process is possible to obtain less than 30 nm hole pattern without enormous writing time. As future work, we will imprint master to replica template and check the printability.

Nano Imprint Lithography (NIL) is valued as a cost effective alternative to other Next Generation Lithography (NGL) choices, especially for memory device applications. In order to achieve an attractive Cost of Ownership (CoO), replicas are made from a master and those replicas are then used in the actual pattern transfer onto the device wafer. During the pattern transfer process from a template to a device wafer, droplets of imaging material are applied to the surface of the substrate, in the area where the imaging is to take place. The image to be transferred is then brought into direct contact with the imaging material, at which time it will spread between the two surfaces by means of capillary force, and the imaging material is then solidified through UV irradiation. As the template is pulled away, it leaves its image imprinted into the imaging material. Any resist adhering to the template will cause defects in subsequent imprints, hence such template contamination, so called resist plugs, must either be avoided or removed. This work focuses on the resist removal techniques employing ambient pressure plasma, and their benefit to improve throughput, i.e. CoO. In our studies, we found that resist removal efficiency is highly depending on the process gas mixture and the process temperature. This dry cleaning process has a good potential as an efficient in-line imprint mask cleaning system.

Nanoimprint lithography (NIL) is one of the most potential candidates for the next generation lithography for semiconductor. It will achieve the lithography with high resolution and low cost. High resolution of NIL will be determined by a high definition template. Nanoimprint lithography will faithfully transfer the pattern of NIL template to the wafer. Cross-sectional profile of the template pattern will greatly affect the resist profile on the wafer. Therefore, the management of the cross-sectional profile is essential. Grazing incidence small angle x-ray scattering (GI-SAXS) technique has been proposed as one of the method for measuring cross-sectional profile of periodic nanostructure pattern. Incident x-rays are irradiated to the sample surface with very low glancing angle. It is close to the critical angle of the total reflection of the x-ray. The scattered x-rays from the surface structure are detected on a two-dimensional detector. The observed intensity is discrete in the horizontal (2θ) direction. It is due to the periodicity of the structure, and diffraction is observed only when the diffraction condition is satisfied. In the vertical (β) direction, the diffraction intensity pattern shows interference fringes reflected to height and shape of the structure. Features of the measurement using x-ray are that the optical constant for the materials are well known, and it is possible to calculate a specific diffraction intensity pattern based on a certain model of the cross-sectional profile. The surface structure is estimated by to collate the calculated diffraction intensity pattern that sequentially while changing the model parameters with the measured diffraction intensity pattern. Furthermore, GI-SAXS technique can be measured an object in a non-destructive. It suggests the potential to be an effective tool for product quality assurance. We have developed a cross-sectional profile measurement of quartz template pattern using GI-SAXS technique. In this report, we will report the measurement capabilities of GI-SAXS technique as a cross-sectional profile measurement tool of NIL quartz template pattern.

We have observed a new type haze of which formation deviates from the generally accepted models with respect to the size, shape, and removability by chemicals. It has very small size of 50~100nm and are crowded around the cell boundary, while the typical haze doesn’t prefer a special region on mask in the majority of cases. It is hard to remove by general cleaning, while the typical haze is easily removed by general cleaning process and even de-ionized water. It is confirmed that the source of the haze is blank material related ions which are formed by chemical etching of blanks during mask cleaning process or the photomask blanks itself.