Sustainable practices, no matter the context, demand a quantitative assessment of environmental impacts. To provide that information, imec has developed a cradle-to-gate life cycle analysis of logic technology nodes based on bottom-up modeling of a generic high-volume semiconductor fabrication fab. Tool data, process recipes, and integrated wafer process flows are extracted from imec’s fab and partner data. The resultant virtual fab is used to identify major process contributors to emissions, to provide sensitivity analysis, and to enable future patterning decisions with a quantification of their environmental ramifications. Overall technology data will be shown, but as a more targeted example, the introduction of low and high NA EUV lithography will be studied. Key patterning parameters like mask design choices, wafer dose and patterning approaches are varied to quantify sensitivity to these choices. In the end, sustainability is driven by understanding the impact of these decisions throughout the supply chain. You will learn among other things, whether high NA is a sustainable choice or not.
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