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29 January 1985 Optical Threshold Logic Architectures For Hybrid Binary/Residue Processors
R. Arrathoon, T. Klepaczyk
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Proceedings Volume 0517, Integrated Optical Circuit Engineering I; (1985) https://doi.org/10.1117/12.945142
Event: 1984 Cambridge Symposium, 1984, Cambridge, United States
Abstract
A new hybrid binary/residue arithmetic processor is proposed which significantly reduces the number of components and lines with respect to ordinary residue processors. Programmable optical threshold logic elements are combined with the hybrid structure to produce an optical architecture which offers substantial advantages over all-electronic approaches.
© (1985) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
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R. Arrathoon and T. Klepaczyk "Optical Threshold Logic Architectures For Hybrid Binary/Residue Processors", Proc. SPIE 0517, Integrated Optical Circuit Engineering I, (29 January 1985); https://doi.org/10.1117/12.945142
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KEYWORDS
Binary data
Logic devices
Integrated optics
Logic
Integrated optical circuits
Optical engineering
Photonic integrated circuits
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