Effect Of Plastic Deformation Of Silicon Wafers On Overlay

R. E. Gegenwarth; F. P. Laming

doi:10.1117/12.955355

8 August 1977 Effect Of Plastic Deformation Of Silicon Wafers On Overlay

R. E. Gegenwarth, F. P. Laming

Proceedings Volume 0100, Developments in Semiconductor Microlithography II; (1977) https://doi.org/10.1117/12.955355
Event: Developments in Semiconductor Microlithography II, 1977, San Jose, United States

Abstract

Direct measurement of lateral distortion in (100) silicon wafers reveals random shifts as large as 0.5 μm resulting from high-temperature processes commonly used during the manufacture of integrated circuits. Such shifts are commensurate in size with the dimensional tolerances required for high-performance integrated circuits, and therefore pose a serious problem in the manufacture of devices requiring submicrometer lines or overlay accuracy of less than 1 μm. The effect has been studied after processing in various conditions; the lateral or in-plane distortions appear to increase as wafers undergo multiple-processing steps.

Citation Download Citation

R. E. Gegenwarth and F. P. Laming "Effect Of Plastic Deformation Of Silicon Wafers On Overlay", Proc. SPIE 0100, Developments in Semiconductor Microlithography II, (8 August 1977); https://doi.org/10.1117/12.955355

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