This PDF file contains the front matter associated with SPIE Proceedings Volume 10032, including the Title Page, Copyright information, Table of Contents, Foreword, List of Sponsors, and Conference Committee listing.

The patterning of the contact layer is modulated by strong etch effects that are highly dependent on the geometry of the contacts. Such litho-etch biases need to be corrected to ensure a good pattern fidelity. But aggressive designs contain complex shapes that can hardly be compensated with etch bias table and are difficult to characterize with standard CD metrology. In this work we propose to implement a model based etch compensation method able to deal with any contact configuration. With the help of SEM contours, it was possible to get reliable 2D measurements particularly helpful to calibrate the etch model. The selections of calibration structures was optimized in combination with model form to achieve an overall errRMS of 3nm allowing the implementation of the model in production.

In recent years, increased demand for high aspect ratio MEMS structures has driven the need for thick photoresist fabrication processes. In this work, the optimization of a thick photoresist process using a negative tone resist (THB-151N) is described. A thickness of 85 μm is obtained with an aspect ratio of 17:1 in a single coating process, with a 5 μm pitch. Conventional UV lithography is used and its parameters are optimized in order to achieve straight and near vertical sidewall profiles. The developed patterns are used as a mold to electroplate high aspect ratio copper windings of micro-inductors and micro-transformers. A high aspect ratio yields a copper track with a large cross sectional area resulting in a lower DC resistance. This enables a further reduction in the footprint area allowing for a more efficient manufacturing process and smaller device size. Unlike other high aspect ratio resist such as SU-8, this resist does not need a post exposure bake and can be readily removed after metal electroplating.

Photomasks contain geometric information that will be transferred to substrates or pre-structured surfaces. Conventional mask aligner lithography in the sense of shadow printing of the photomask suffers from limited achievable resolution. Photomask and substrate are typically separated by an air gap causing diffraction effects and hence affecting the minimum structure size. Even though contact lithography offers a resolution in the wavelengthscale, yield problems and contamination of the photomask are its drawbacks. Using proximity lithography, these problems can be avoided since it profits from a contact-free exposure process. To overcome the resolution limitation of the shadow printing mode more advanced diffraction based photo masks need to be used.

As optical lithography is extended into 10nm and below nodes, advanced designs are becoming a key challenge for mask manufacturers. Techniques including advanced Optical Proximity Correction (OPC) and Inverse Lithography Technology (ILT) result in structures that pose a range of issues across the mask manufacturing process. Among the new challenges are continued shrinking Sub-Resolution Assist Features (SRAFs), curvilinear SRAFs, and other complex mask geometries that are counter-intuitive relative to the desired wafer pattern. Considerable capability improvements over current mask making methods are necessary to meet the new requirements particularly regarding minimum feature resolution and pattern fidelity. Advanced processes using the IMS Multi-beam Mask Writer (MBMW) are feasible solutions to these coming challenges. In this paper, we study one such process, characterizing mask manufacturing capability of 10nm and below structures with particular focus on minimum resolution and pattern fidelity.

The pattern requirements for mask writers have steadily been growing, and there is considerable interest in multibeam mask writers to handle the throughput and resolution challenges associated with the needs of sub- 10nm technology nodes. The mask writer of the future will process terabits of information per second and deal with petabytes of data. In this paper, we investigate lossless data compression and system parallelism together to address part of the data transfer problem. We explore simple compression algorithms and the effect of parallelism on the total compressed data in a multibeam system architecture motivated by the IMS Nanofabrication multibeam mask writer series eMET. We model the shot assignment problem and beam shot overlap by means of two-dimensional linear spatial filtering on an image. We describe a fast scanning strategy and investigate data volumes for a family of beam arrays with 2^N ×(2^N −1) beams, where N is an odd integer.

Megasonic cleaning remains the industry’s workhorse technology for particle removal on advanced 193i and extreme ultraviolet (EUV) photomasks. Several megasonic cleaning technologies and chemistries have been proposed and implemented over the years in diverse production environments. The operational range of these process technologies, over a wide array of applications, is ultimately defined by measurable capability limits. As geometries continue to scale-down and new materials are introduced, existing cleaning technologies will naturally fade out of range and new capability is ultimately required. This paper presents a novel fundamental approach for expanding cleaning capability by use of high-frequency megasonics and tenside-based additives (BASF SELECTIPUR C-series). To this end, a sonoluminescence-based experimental test bench was configured to characterize and study the effects of various process parameters on cleaning performance, with a particular emphasis on cavitation-induced damage and enhancement of particle removal capabilities. The results from the fundamental studies provide a path forward towards delivering new cleaning capability by enabling high-frequency megasonic systems and tenside-based additives.

The race to 800 PPI and higher in mobile devices and the transition to OLED displays are driving a dramatic development of mask quality: resolution, CDU, registration, and complexity. 2D metrology for large area masks is necessary and must follow the roadmap. Driving forces in the market place point to continued development of even more dense displays. State-of-the-art metrology has proven itself capable of overlay below 40 nm and registration below 65 nm for G6 masks.

Future developments include incoming and recurrent measurements of pellicalized masks at the panel maker’s factory site. Standardization of coordinate systems across supplier networks is feasible. This will enable better yield and production economy for both mask and panel maker. Better distortion correction methods will give better registration on the panels and relax the flatness requirements of the mask blanks. If panels are measured together with masks and the results are used to characterize the aligners, further quality and yield improvements are possible.

Possible future developments include in-cell metrology and integration with other instruments in the same platform.

Photonic technology is increasingly used in applications in medicine, life and environmental science. Whereas currently many of these applications are implemented using some form of discrete (free-space) optics, much can be gained from a transition to Photonics Integrated Circuits. This follows the trends in the electronics industry where highly integrated electronic circuits have allowed the combination of many different functions in a small form factor. Just as it has done for the electronics industry, integrated optics will lead to smaller, cheaper, more reliable and more user friendly devices.

We will shed light on the optimization of lithographic metrics for the semi-isolated dark field two-bar logic building block. Under standard D90Y illumination this building block suffers from large mask 3D induced relative focus dependent CD asymmetries. Such behavior limits its overlapping process window and gives rise to untenable full wafer CDU and intra-field pattern shifts.

We have found that besides a Ta absorber thickness reduction an illumination pupil optimization is necessary to fully remove these CD asymmetries. The pupil optimization is achieved by relating the aerial image decomposition (here: symmetrization and balancing of intensities across the diffracted orders) with lithographic metrics per pupil plane location. The resulting pupil allows us (i) to lift the focus-dependent CD asymmetries and (ii) to co-optimize a number of lithographic metrics such as overlapping process window, contrast, non-telecentricity and pattern shift. The importance of subsidiary conditions (e.g. symmetry of the pupil, required DOF) will be discussed.

This paper presents some of the main imaging properties introduced with the design of a possible new EUV High-NA (NA > 0.5) exposure system with anamorphic projection lens, a concept not new in optics but applied for the first time in semiconductor lithography. The system is projected to use a demagnification of 4 in the X-direction and of 8 in the Y-direction.

We show that a new definition of the Mask Error Factor needs to be used in order to describe correctly the property introduced by the anamorphic optics. Moreover, for both 1-Dimensional (1D) and 2-Dimensional (2D) features the reticle writing error in the low demagnification direction X is more critical than the error in high demagnification direction Y.

The effects of the change in demagnification on imaging are described on an elementary case, and are ultimately linked to the basic physical phenomenon of diffraction.

The fabrication of high performance gratings for distributed feedback (DFB) lasers by direct-write (DW) electron-beam lithography (EBL) is presented. This paper starts with a short introduction of the grating theory and various types of gratings commonly used in DFB lasers, laying out resolution requirements and other fabrication challenges. The development and optimization process of the adopted EBL technology is then disclosed to address these challenges. In the end, the state-of-the-art laser performance is demonstrated, validating the technology and also paving ways for more advanced applications in the modern optical networks. We concentrate on grating fabrication technology of DFB lasers for telecommunication applications as the technology has been continuously developed at Fraunhofer Heinrich Hertz Institute (HHI) for more than two decades.

In this work routes towards the fabrication of photonic integrated circuits (PICs) and the challenges their fabrication poses on lithography, such as large differences in feature dimension of adjacent device features, non-Manhattan-type features, high aspect ratios and significant topographic steps as well as tight lithographic requirements with respect to critical dimension control, line edge roughness and other key figures of merit not only for very small but also for relatively large features, are highlighted. Several ways those challenges are faced in today’s low-volume fabrication of PICs, including the concept multi project wafer runs and mix and match approaches, are presented and possible paths towards a real market uptake of PICs are discussed.

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography* (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. For imprint lithography, recent attention has been given to the areas of overlay, throughput, defectivity, and mask replication. This paper reviews progress in these critical areas. Recent demonstrations have proven that mix and match overlay of less than 5nm can achieved. Further reductions require a higher order correction system. Modeling and experimental data are presented which provide a path towards reducing the overlay errors to less than 3nm. Throughput is mainly impacted by the fill time of the relief images on the mask. Improvement in resist materials provides a solution that allows 15 wafers per hour per station, or a tool throughput of 60 wafers per hour. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. Hard particles on a wafer or mask create the possibility of inducing a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, the lifetime of both the master mask and the replica mask can be extended. In this work, we report results that demonstrate a path towards achieving mask lifetimes of better than 1000 wafers. Finally, on the mask side, a new replication tool, the FPA-1100NR2 is introduced. Mask replication is required for nanoimprint lithography (NIL), and criteria that are crucial to the success of a replication platform include both particle control and IP accuracy. In particular, by improving the specifications on the mask chuck, residual errors of only 1nm can be realized.

Nano-patterning materials and surfaces can add unique functionalities and properties which cannot be obtained in bulk or micro-structured materials. Examples range from hetro-epitaxy of semiconductor nano-wires to guiding cell expression and growth on medical implants. [1] Due to the cost and throughput requirements conventional nano-patterning techniques such as deep UV lithography (cost and flat substrate demands) and electron-beam lithography (cost, throughput) are not an option. Self-assembly techniques are being considered for IC manufacturing, but require nano-sized guiding patterns, which have to be fabricated in any case.[2] Additionally, the self-assembly process is highly sensitive to the environment and layer thickness, which is difficult to control on non-flat surfaces such as PV silicon wafers or III/V substrates. Laser interference lithography can achieve wafer scale periodic patterns, but is limited by the throughput due to intensity of the laser at the pinhole and only regular patterns are possible where the pattern fill fraction cannot be chosen freely due to the interference condition.[3] Nanoimprint lithography (NIL) is a promising technology for the cost effective fabrication of sub-micron and nano-patterns on large areas. The challenges for NIL are related to the technique being a contact method where a stamp which holds the patterns is required to be brought into intimate contact with the surface of the product. In NIL a strong distinction is made between the type of stamp used, either rigid or soft. Rigid stamps are made from patterned silicon, silica or plastic foils and are capable of sub-10nm resolution and wafer scale patterning. All these materials behave similar at the micro- to nm scale and require high pressures (5 – 50 Bar) to enable conformal contact to be made on wafer scales. Real world conditions such as substrate bow and particle contaminants complicate the use of rigid stamps for wafer scale areas, reducing stamp lifetime and yield. Soft stamps, usually based on silicone rubber, behave fundamentally different compared to rigid stamps on the macro-, micro- and nanometer level. The main limitation of traditional silicones is that they are too soft to support sub-micron features against surface tension based stamp deformation and collapse [4] and handling a soft stamp to achieve accurate feature placement on wafer scales to allow overlay alignment with sub-100nm overlay accuracy.

EUV Defect avoidance techniques will play a vital role in extreme ultraviolet lithography (EUVL) photomask fabrication with the anticipation that defect free mask blanks won’t be available and that cost effective techniques will not be available for defect repairing. In addition, mask shops may not have a large inventory of expensive EUV mask blanks. Given these facts, defect avoidance can be used as cost effective technique to optimize the mask blank and design data (mask data) pair selection across mask blank manufacturers and mask shops so that overall mask blank utilization can be enhanced.

In previous work, it was determined that the pattern shift based solution increases the chance that a defective mask blank can be used that would otherwise be discarded [1]. In pattern shift, design data is shifted such that defects are either moved to isolated regions or hidden under the patterns that are written. However pattern shifts techniques don’t perform well with masks with higher defect counts. Pattern shift techniques in this form assume all defects to be equally critical. In addition, a defect is critical or important only if it lands on the main pattern. A defect landing on fill, sub-resolution assist feature (SRAF) or fiducial areas may not be critical. In this paper we assess the performance of pattern shift techniques assuming defects that are not critical based upon size or type, as well as defects landing in non-critical areas (smart shift) can be ignored.

In a production mask manufacturing environment it is necessary to co-optimize and prioritize blank-design pairing for multiple mask layouts in the queue with the available blanks. A blank-design pairing tool maximizes the utilization of blanks by finding the best pairing between blanks and design data so that the maximum number of mask blanks can be used. In this paper we also propose a novel process which would optimize the usage of costly EUV mask blanks across mask blank manufacturers and mask shops which write masks.

In the early phases of technology development, designers and process engineers have to converge toward efficient design rules. Their calculations are based on process assumptions and result in a design rule based on known process variability capabilities while taking into account enough margin to be safe not only for yield but especially for reliability. Unfortunately, even if designs tend to be regular, efficient design densities are still requiring aggressive configurations from which it is difficult to estimate dimension variabilities. Indeed, for a process engineer it is rather straightforward to estimate or even measure simple one-dimensional features (arrays of Lines & Spaces at various CD and pitches), but it starts to be less obvious for complex multidimensional features. After a context description related to the process assumptions, we will outline the work flow which is under evaluation to enable robust metrology of 2 dimensional complex features. Enabling new metrology possibilities reveals that process hotspots are showing complex behavior from lithography to etch pattern transfer. In this work we studied the interaction of lithography variability and etching for a mature 28 nm CMOS process. To study this interaction we used a test feature that has been found very sensitive to lithography process variations. This so-called “golden” hotspot shows edge-to-edge geometries from 88nm to 150nm, thus comprising all the through pitch physics in the lithography pattern transfer [1, 2]. It consists of three trenches. From previous work it was known that through trench there is a systematic variation in best focus due to the Mask 3D effects. At a given chosen focus, there is a distinct difference in profiles for the three trenches that will lead to pattern displacement effects during the etch transfer.

In the process of semicondutcor fabrication the translation of the final product requirements into specific targets for each component of the manufacturing process is one of the most demanding tasks. This involves the careful assessment of the error budgets of each component as well as the sensible balancing of the costs implied by the requirements. Photolithographic masks play a pivotal role in the semiconductor fabrication. This attributes a crucial role to mask error budgeting within the overall wafer production process. Masks with borderline performance with respect to the wafer fabrication requirements have a detrimental effect on the wafer process window thus inducing delays and costs. However, prohibitively strict mask specifications will induce large costs and delays in the mask manufacturing process. Thus setting smart control mechanisms for mask quality assessment is highly relevant for an efficient production flow. To this end GLOBALFOUNDRIES and the AMTC have set up a new mask specification check to enable a smart ship to control process for mask manufacturing. Within this process the mask CD distribution is checked as to whether it is commensurable with the advanced dose control capabilities of the stepper in the wafer factory. If this is the case, masks with borderline CD performance will be usable within the manufacturing process as the signatures can be compensated. In this paper we give a detailed explanation of the smart ship control approach with its implications for mask quality.

Derivatives technologies based on core CMOS processes are significantly aggressive in term of design rules and process control requirements. Process control plan is a derived from Process Assumption (PA) calculations which result in a design rule based on known process variability capabilities, taking into account enough margin to be safe not only for yield but especially for reliability. Even though process assumptions are calculated with a 4 sigma known process capability margin, efficient and competitive designs are challenging the process especially for derivatives technologies in 40 and 28nm nodes. For wafer fab process control, PA are declined in monovariate (layer1 CD, layer2 CD, layer2 to layer1 overlay, layer3 CD etc….) control charts with appropriated specifications and control limits which all together are securing the silicon. This is so far working fine but such system is not really sensitive to weak signals coming from interactions of multiple key parameters (high layer2 CD combined with high layer3 CD as an example). CHAM is a software using an advanced statistical algorithm specifically designed to detect small signals, especially when there are many parameters to control and when the parameters can interact to create yield issues. In this presentation we will first present the CHAM algorithm, then the case-study on critical dimensions, with the results, and we will conclude on future work. This partnership between Ippon and STM is part of E450LMDAP, European project dedicated to metrology and lithography development for future technology nodes, especially 10nm.

A novel Sub-Resolution Assist Feature (SRAF) insertion approach is discussed. The method of linearly added SRAFs (laSRAF) is based on the superposition, linear addition in the simplest case, of pre-calculated SRAF usefulness templates. The usefulness templates describe net effect of an elementary SRAF insertion in the proximity of an isolated arbitrary target shape. The method includes two major steps: (i) SRAF usefulness map generation for arbitrary layout comprised of OPC target shapes and (ii) derivation of Mask Rule Check (MRC) compliant SRAF shapes from those usefulness maps. The performance of the laSRAF method measured by the run-time and process window enhancement effect is compared to production quality model-based SRAF insertion implementations and one rule-based realization. The comparison reveals up to 8 times faster SRAF insertion at the same or better SRAF quality with the laSRAF method compared to model-based solutions. LaSRAF has been found to be significantly superior in terms of SRAF quality at the penalty of 2-4x longer run-time compared to rule-based SRAF.

In order to deploy EUV lithography as a high volume manufacturing technology an extreme control of reticle defectivity is required. Systematic defect printing is unaffordable. A potential solution being investigated for meeting the EUV reticle contamination control requirements is to utilize a suspended thin membrane (pellicle) mounted at a fixed distance in front of the reticle as a physical barrier against particles. Pellicles of the aspect ratios relevant for the scanner (~11x14 cm², ~50 nm) that are based on polycrystalline silicon were produced and successful imaging runs were carried out. Investigations of pellicles using different materials continue to ensure having membranes capable of withstanding future high EUV source powers and to ensure larger EUV transmission values. The ideal requirements of the pellicle are: (i) maximum EUV transmission ideally above 90% single pass, (ii) chemical stability and (iii) thermo-mechanical resistance under EUV/H₂. Since fulfilling all the requirements in one single layer is a challenge, different layer film architectures are proposed. This paper discusses such architectures, both silicon- and carbon-based. The base materials are complemented by nanometre thin coatings that increase IR absorption and thus enhance emissivity and that prevents oxidation of the base material occurring in high power EUV systems.

In this paper a first Critical Dimension (CD) uniformity assessment onto 200 mm wafers printed with the SmartNIL^TM technology available in the HERCULES® NIL equipment platform is proposed. The work brings focus on sub micrometer resolution features with a depth between 220 and 433 nm. The silicon masters were manufactured with 193 optical lithography and dry etching. A complete Scanning Electron Microscopy (SEM) characterizations were performed over the full masters surface prior to the imprint process. Repeatability tests were performed over 25 wafers first and then on 100 wafers to collect statistics and the CD distribution within a wafer and also wafer to wafer. The data revealed that the CD is evolving imprint after imprint and an explanation based on polymer shrinkage is proposed.

The use of optical proximity correction (OPC) demands increasingly accurate models of the photolithographic process. Model building and analysis techniques in the data science community have seen great strides in the past two decades which make better use of available information. This paper expands upon Bayesian analysis methods for parameter selection in lithographic models by increasing the parameter set and employing posterior predictive checks. Work continues with a Markov chain Monte Carlo (MCMC) search algorithm to generate posterior distributions of parameters. Models now include wafer film stack refractive indices, n and k, as parameters, recognizing the uncertainties associated with these values. Posterior predictive checks are employed as a method to validate parameter vectors discovered by the analysis, akin to cross validation.

Epoxy-based resist SU-8 is widely used in the development and fabrication of high-aspect-ratio (HAR) MEMS structures. It has proven to be a suitable photoresist combining thick layer coating and good adhesion on silicon substrates as well as possessing good mechanical and chemical stability. However, the trend towards minia- turization and increasing packaging density has pushed the demand for challenging micro-machining processes. As an example, a novel design of a MEMS microinductor requires a dielectric permanent layer coated in deep silicon trenches in order to insulate copper windings from the magnetic material deposited in these trenches. This requires the development of a photolithography process which enables the coating of a void-free layer filling the trenches. In this paper, the use of thick SU-8 photoresist for filling deep silicon trenches is investigated. Different SU-8 formulations are analyzed, processed and results are compared. As a result, an optimized process is developed to achieve void-free filled trenches and a uniform planar layer above them, with near vertical sidewall patterns.

Advanced technology nodes require more and more information to get the wafer process well setup. The critical dimension of components decreases following Moore’s law. At the same time, the intra-wafer dispersion linked to the spatial non-uniformity of tool’s processes is not capable to decrease in the same proportions. APC systems (Advanced Process Control) are being developed in waferfab to automatically adjust and tune wafer processing, based on a lot of process context information. It can generate and monitor complex intrawafer process profile corrections between different process steps. It leads us to put under control the spatial variability, in real time by our SPC system (Statistical Process Control). This paper will outline the architecture of an integrated process control system for shape monitoring in 3D, implemented in waferfab.

This work presents a novel approach for combined micro- and nanofabrication based on the local laser exposure of an UV-curing material through a structured mold. The proposed process makes use of the high freedom of design of direct laser writing (DLW) and the high resolution of soft lithography molds (made e.g. from PDMS). By optimizing the exposure process it was possible to fabricate locally defined hierarchical structures with a height of around 16 μm, that are fully covered with nanometer-sized holes using OrmoComp®. Manual test imprints showed that the fabricated structures can be used for “step and repeat” nanoimprint processes. Furthermore, the local transfer of nanostructures into two different soft lithography resists (Katiobond 110707, mr-NIL210) was investigated. Diffusion of resist components into the PDMS mold was observed and could be prohibited by the use of hybrid molds, which employ OrmoComp® as structure containing layer. First experiments revealed successful transfer of the mold’s nanostructures into mr-NIL210 but still leave room for improvement concerning the process parameters.

For the specific requirements of the 14nm and 20nm site applications a new CD map approach was developed at the AMTC. This approach relies on a well established machine learning technique called recursive partitioning. Recursive partitioning is a powerful technique which creates a decision tree by successively testing whether the quantity of interest can be explained by one of the supplied covariates. The test performed is generally a statistical test with a pre-supplied significance level. Once the test indicates significant association between the variable of interest and a covariate a split performed at a threshold value which minimizes the variation within the newly attained groups. This partitioning is recurred until either no significant association can be detected or the resulting sub group size falls below a pre-supplied level.