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21 March 2017 Study of nanoimprint lithography (NIL) for HVM of memory devices
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A low cost alternative lithographic technology is desired to meet the decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the candidates for alternative lithographic technologies.[1][2][3] NIL has such advantages as good resolution, critical dimension (CD) uniformity and low line edge roughness (LER). On the other hand, the critical issues of NIL are defectivity, overlay, and throughput. In order to introduce NIL into the HVM, it is necessary to overcome these three challenges simultaneously.[4]-[12] In our previous study, we have reported a dramatic improvement in NIL process defectivity on a pilot line tool, FPA-1100 NZ2. We have described that the NIL process for 2x nm half pitch is getting closer to the target of HVM.[12] In this study, we report the recent evaluation of the NIL process performance to judge the applicability of NIL to memory device fabrications. In detail, the CD uniformity and LER are found to be less than 2nm. The overlay accuracy of the test device is less than 7nm. A defectivity level of below 1pcs./cm2 has been achieved at a throughput of 15 wafers per hour.
Conference Presentation
© (2017) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Takuya Kono, Masayuki Hatano, Hiroshi Tokue, Kei Kobayashi, Masato Suzuki, Kazuya Fukuhara, Masafumi Asano, Tetsuro Nakasugi, Eun Hyuk Choi, and Wooyung Jung "Study of nanoimprint lithography (NIL) for HVM of memory devices", Proc. SPIE 10144, Emerging Patterning Technologies, 1014406 (21 March 2017);

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