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30 March 2017 Pattern-based analytics to estimate and track yield risk of designs down to 7nm
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Topological pattern-based methods for analyzing IC physical design complexity and scoring resulting patterns to identify risky patterns have emerged as powerful tools for identifying important trends and comparing different designs. In this paper, previous work is extended to include analysis of layouts designed for the 7nm technology generation. A comparison of pattern complexity trends with respect to previous generations is made. In addition to identifying topological patterns that are unique to a particular design, novel techniques are proposed for scoring those patterns based on potential yield risk factors to find patterns that pose the highest risk.
© (2017) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jason P. Cain, Moutaz Fakhry, Piyush Pathak, Jason Sweis, Frank E. Gennari, and Ya-Chieh Lai "Pattern-based analytics to estimate and track yield risk of designs down to 7nm", Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 1014805 (30 March 2017);

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