Electrical failure debug using interlayer profiling method

Thomas Yang; Yang Shen; Yifan Zhang; Jason Sweis; Ya-Chieh Lai

doi:10.1117/12.2259944

30 March 2017 Electrical failure debug using interlayer profiling method

Thomas Yang, Yang Shen, Yifan Zhang, Jason Sweis, Ya-Chieh Lai

Proceedings Volume 10148, Design-Process-Technology Co-optimization for Manufacturability XI; 101481D (2017) https://doi.org/10.1117/12.2259944
Event: SPIE Advanced Lithography, 2017, San Jose, California, United States

Abstract

It is very well known that as technology nodes move to smaller sizes, the number of design rules increases while design structures become more regular and the process manufacturing steps have increased as well. Normal inspection tools can only monitor hard failures on a single layer. For electrical failures that happen due to inter layers misalignments, we can only detect them through testing.

This paper will present a working flow for using pattern analysis interlayer profiling techniques to turn multiple layer physical info into group linked parameter values. Using this data analysis flow combined with an electrical model allows us to find critical regions on a layout for yield learning.

Citation Download Citation

Thomas Yang, Yang Shen, Yifan Zhang, Jason Sweis, and Ya-Chieh Lai "Electrical failure debug using interlayer profiling method", Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101481D (30 March 2017); https://doi.org/10.1117/12.2259944

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