Self-aligned blocking integration demonstration for critical sub-40nm pitch Mx level patterning

Angélique Raley; Nihar Mohanty; Xinghua Sun; Richard A. Farrell; Jeffrey T. Smith; Akiteru Ko; Andrew W. Metz; Peter Biolsi; Anton Devilliers

doi:10.1117/12.2257769

7 April 2017 Self-aligned blocking integration demonstration for critical sub-40nm pitch Mx level patterning

Angélique Raley, Nihar Mohanty, Xinghua Sun, Richard A. Farrell, Jeffrey T. Smith, Akiteru Ko, Andrew W. Metz, Peter Biolsi, Anton Devilliers

Author Affiliations +

Proceedings Volume 10149, Advanced Etch Technology for Nanopatterning VI; 101490O (2017) https://doi.org/10.1117/12.2257769
Event: SPIE Advanced Lithography, 2017, San Jose, California, United States

Abstract

Multipatterning has enabled continued scaling of chip technology at the 28nm node and beyond. Selfaligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) as well as Litho- Etch/Litho-Etch (LELE) iterations are widely used in the semiconductor industry to enable patterning at sub 193 immersion lithography resolutions for layers such as FIN, Gate and critical Metal lines. Multipatterning requires the use of multiple masks which is costly and increases process complexity as well as edge placement error variation driven mostly by overlay. To mitigate the strict overlay requirements for advanced technology nodes (7nm and below), a self-aligned blocking integration is desirable. This integration trades off the overlay requirement for an etch selectivity requirement and enables the cut mask overlay tolerance to be relaxed from half pitch to three times half pitch. Selfalignement has become the latest trend to enable scaling and self-aligned integrations are being pursued and investigated for various critical layers such as contact, via, metal patterning.

In this paper we propose and demonstrate a low cost flexible self-aligned blocking strategy for critical metal layer patterning for 7nm and beyond from mask assembly to low –K dielectric etch. The integration is based on a 40nm pitch SADP flow with 2 cut masks compatible with either cut or block integration and employs dielectric films widely used in the back end of the line. As a consequence this approach is compatible with traditional etch, deposition and cleans tools that are optimized for dielectric etches. We will review the critical steps and selectivities required to enable this integration along with bench-marking of each integration option (cut vs. block).

Conference Presentation

Citation Download Citation

Angélique Raley, Nihar Mohanty, Xinghua Sun, Richard A. Farrell, Jeffrey T. Smith, Akiteru Ko, Andrew W. Metz, Peter Biolsi, and Anton Devilliers "Self-aligned blocking integration demonstration for critical sub-40nm pitch Mx level patterning", Proc. SPIE 10149, Advanced Etch Technology for Nanopatterning VI, 101490O (7 April 2017); https://doi.org/10.1117/12.2257769

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available