Silicon pixel detector prototyping in SOI CMOS technology

Roma Dasgupta; Szymon Bugiel; Marek Idzik; Piotr Kapusta; Wojciech Kucewicz; Michal Turala

doi:10.1117/12.2261485

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22 December 2016 Silicon pixel detector prototyping in SOI CMOS technology

Roma Dasgupta, Szymon Bugiel, Marek Idzik, Piotr Kapusta, Wojciech Kucewicz, Michal Turala

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Proceedings Volume 10175, Electron Technology Conference 2016; 1017505 (2016) https://doi.org/10.1117/12.2261485
Event: Electron Technology Conference ELTE 2016, 2016, Wisla, Poland

Abstract

The Silicon-On-Insulator (SOI) CMOS is one of the most advanced and promising technology for monolithic pixel detectors design. The insulator layer that is implemented inside the silicon crystal allows to integrate sensors matrix and readout electronic on a single wafer. Moreover, the separation of electronic and substrate increases also the SOI circuits performance. The parasitic capacitances to substrate are significantly reduced, so the electronic systems are faster and consume much less power. The authors of this presentation are the members of international SOIPIX collaboration, that is developing SOI pixel detectors in 200 nm Lapis Fully-Depleted, Low-Leakage SOI CMOS. This work shows a set of advantages of SOI technology and presents possibilities for pixel detector design SOI CMOS. In particular, the preliminary results of a Cracow chip are presented.

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Roma Dasgupta, Szymon Bugiel, Marek Idzik, Piotr Kapusta, Wojciech Kucewicz, and Michal Turala "Silicon pixel detector prototyping in SOI CMOS technology", Proc. SPIE 10175, Electron Technology Conference 2016, 1017505 (22 December 2016); https://doi.org/10.1117/12.2261485

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