A 10 Gs/s latched comparator with dynamic offset cancellation in 28nm FD-SOI process

Zbigniew Jaworski

doi:10.1117/12.2263521

22 December 2016 A 10 Gs/s latched comparator with dynamic offset cancellation in 28nm FD-SOI process

Zbigniew Jaworski

Proceedings Volume 10175, Electron Technology Conference 2016; 101750A (2016) https://doi.org/10.1117/12.2263521
Event: Electron Technology Conference ELTE 2016, 2016, Wisla, Poland

Abstract

This papers presents a high-speed, latched comparator implemented in industrial 28 nm FD-SOI technology. A novel approach to counter the mismatch is proposed. The solution employs trimming the threshold voltage by means of modulating of back-gate polarization of FD-SOI transistors. The comparator is a first step towards the design of a complete 4-bit FLASH analog-to-digital converter, with a sampling frequency of 10 GHz.

Citation Download Citation

Zbigniew Jaworski "A 10 Gs/s latched comparator with dynamic offset cancellation in 28nm FD-SOI process", Proc. SPIE 10175, Electron Technology Conference 2016, 101750A (22 December 2016); https://doi.org/10.1117/12.2263521

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