Semiconductor pattern overlay

Neal T. Sullivan

doi:10.1117/12.187454

1 July 1994 Semiconductor pattern overlay

Neal T. Sullivan

Proceedings Volume 10274, Handbook of Critical Dimension Metrology and Process Control: A Critical Review; 102740C (1994) https://doi.org/10.1117/12.187454
Event: Microelectronic Processing '93, 1993, Monterey, CA, United States

Abstract

Advanced semiconductor manufacturing processes require tight overlay registration tolerances. These strict overlay performance specifications dictate the wafer level overlay metrology performance required. Achieving a high level of performance from overlay metrology equipment requires attention to all aspects of the measurement process. A typical measurement system configuration is reviewed and elements of optical overlay measurement, as they relate to measurement uncertainty, are discussed in detail. Data analysis techniques, used to quantify tool induced measurement uncertainty, are demonstrated with supporting examples. Process and measurement target induced uncertainties are reviewed. Current developments in both target design and measurement algorithms are proposed to address these uncertainties. Measurement optimization and its role in process control applications and future developments in overlay processing are also discussed.

Citation Download Citation

Neal T. Sullivan "Semiconductor pattern overlay", Proc. SPIE 10274, Handbook of Critical Dimension Metrology and Process Control: A Critical Review, 102740C (1 July 1994); https://doi.org/10.1117/12.187454

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