Translator Disclaimer
Presentation + Paper
15 September 2017 Through-Silicon-Vias (TSVs) for 3D readout of ASIC for nearly gapless CdZnTe detector arrays
Author Affiliations +
Wirebonds, although proven for space application and perceived necessary for hybrid sensors like CdZnTe (CZT) detectors, introduce assembly complexity and undesirable gaps between detector units. Thus, they pose a serious challenge in building a low cost large area detector. We are developing Through-Silicon Vias (TSVs) to make all connections (both power and data) through ASICs, which will eliminate wirebonds and enable simple direct flip-chip bonding between the ASIC and a substrate electronics layer. TSVs also enable a more compact layout of the ASIC, which reduces the inactive area of the detector plane, and thus enables nearly gaplessly tilable detector arrays. We demonstrate the first successful TSV implementation on ASICs used for CZT detectors onboard the Nuclear Spectroscopic Telescope Array (NuSTAR) mission as part of our program to develop large area CZT imagers for wide field coded aperture imaging.
Conference Presentation
© (2017) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
J. Hong, B. Allen, J. Grindlay, Hiromasa Miyasaka, Jill Burnham, Sangki Hong, Wesker Lei, Scott Barthelmy, Robert Patti, and Fiona Harrison "Through-Silicon-Vias (TSVs) for 3D readout of ASIC for nearly gapless CdZnTe detector arrays", Proc. SPIE 10392, Hard X-Ray, Gamma-Ray, and Neutron Detector Physics XIX, 103920U (15 September 2017);

Back to Top