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14 March 2018 Impacts of SiO2 sidewall roughness on light-coupling efficiency for silicon photonics ICs (Conference Presentation)
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Proceedings Volume 10537, Silicon Photonics XIII; 1053715 (2018)
Event: SPIE OPTO, 2018, San Francisco, California, United States
Silicon photonics IC’s are fabricated in CMOS/MEMS lines, and need wafer-level testing and inspection for optical performances. Although optical characteristics evaluations of waveguide and grating coupler have been reported, there is no reports for optical characteristics of a light introduction window from a flip-chip mounted laser diode to a waveguide in a silicon photonics IC. In this paper, we’ll discuss a 5 µm-deep SiO2 clad etching process to fabricate this light introduction window by using a wafer-level optical probing system [1]. Several deep-etched trenches were introduced in the SiO2 clad optical path to measure the optical loss at the windows consisting of well-aligned two waveguides. Three different SiO2 etch conditions to vary the trench sidewall roughness were applied. The gap distance between two waveguides was 2 µm, and the trench width was 1 µm. The measured optical loss at the etched SiO2 surface was about -0.5 dB for the smoother sidewall surface, and increased to -0.6 dB for the rougher surface. This indicates our new method can evaluate the loss difference of the SiO2 surface roughness to 0.1 dB precision. Surface loss distributions over the wafer were about the same for every etch conditions which reflected uniform etching conditions over the wafer. It was confirmed the optical probing system is useful for in-line process monitoring. Impact of the sidewall angle will be discussed at the presentation. This research was supported by New Energy and Industrial Technology Development Organization, Japan. [1] T. Horikawa, et al., Microelectron. Eng., 156, 46 (2016).
Conference Presentation
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Keizo Kinoshita, Tsuyoshi Horikawa, Masataka NOGUCHI, Takahiro Nakamura, and Tohru Mogami "Impacts of SiO2 sidewall roughness on light-coupling efficiency for silicon photonics ICs (Conference Presentation)", Proc. SPIE 10537, Silicon Photonics XIII, 1053715 (14 March 2018);

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