1.1

ESA objectives

Compilation of optical instruments inputs from a large range of ESA missions for science & earth observation program results in ESA objective to develop on the same die and based on a commercial technology (hardened by design):

In order to integrate in Space Market, an European IP Design House Leader, MIPS/CHIPIDEA(Portugal) has been selected by ESA for the VASP (Video Acquisition Signal Processor) ASIC development, in the frame of the HIVAC project.

1.2

HIVAC project organisation and objectives

HIVAC project organisation is presented hereafter:

Prime:

THALES ALENIA SPACE for AIV and System Test

Sub-contractors:

MIPS/CHIPIDEA for VASP development

THALES ALENIA SPACE for HIVAC Breadboard development

Main Technical objectives of HIVAC project are:

In order to improve integration and miniaturisation of video units and to design functional bricks allowing smart flight unit development for future missions.

1.3

HIVAC project workplan

HIVAC project is split in 2 phases (i.e. Phase 1 & Phase 2):

Table 1

HIVAC project work plan

Phase 1 of HIVAC project has been closed successfully. HIVAC project phase 2 is actually on going and detailed design of VASP and HIVAC breadboard finalisation is pending.

3.1

VASP architecture

VASP design is based on high performance analog block functions for signal conditioning and digital block functions for SpaceWire RMAP signal interfacing.

Table 2 details main VASP specifications.

Table 2:

VASP main specifications

VASP integrates a complete analog front-end with Analog to Digital conversion, including video input multiplexer (3 pseudo-diff or diff video inputs), correlated double sampler (CDS), programmable gain amplifier (PGA), 16-bit 3MSps analog to Digital Converter (ADC) and a full optical black on board correction/regulation algorithm.

The VASP ADC is based on a fully differential high speed low power pipeline core including on board calibration algorithm for Integral Non Linearity (INL) and Differential Non Linearity (DNL) correction.

ADC have been designed to have optimal performances at 3MSps. Moreover, for applications having Pixel frequency lower than 1MHz, multisampling per pixel sequencing is possible to optimize SNR by averaging.

Fig. 2:

VASP synoptic

VASP Video chain uses built-in analog reference digitally programmable through SpaceWire to adjust thermal coefficient of the video chain gain.

VASP includes a Phase Locked Loop (PLL) to generate SpaceWire high frequency clock, from an external low frequency clock.

From the SpaceWire high frequency clock, it is possible to generate inside VASP two clocks for operating HIVAC core sequencer: A high frequency master clock (HIVAC system clock) and a pixel frequency. Clock characteristics are fully user programmable through SpaceWire.

VASP has four slow chain inputs for telemetries coming from HIVAC module and/or focal plan (bias voltages, current, temperature, etc).

SpaceWire RMAP (Random Memory Access Protocol) block allows video and auxiliary data packets transmission to user and allows VASP configuration. Moreover, it is possible to transmit to HIVAC core sequencer two kinds of messages directly from SpaceWire interface for HIVAC configuration through a specific 8bits parallel bus managed by VASP.

A local on board time block enables to date all events inside VASP in particular video data packets, errors, SpaceWire tick reception for user and VASP date synchronisation. It allows also to trigger configuration parameters loaded through SpaceWire accordingly to a loaded trigger date.

SpaceWire interface management inside VASP is requiring a wide part of the total power consumption (50% for digital and 50% for analog). Since applications would require stringent power dissipation specification (in particular scientific applications with very low pixel frequency), it is possible to adjust SpaceWire speeds during packet transmission and out of packet transmissions. Both speeds are adjustable independently between Fmax (100Mbps), Fmax/2, Fmax/4 and Fmin (10Mbps).

VASP integrates an I²C interface link in a fully read/write access to VASP internal registers. This interface allows in particular to control fast VASP configuration changes (gain change at line rate, complex offset regulation loop at line rate for spectrometer application, etc).

Since digitised video flux (ADC outputs) is accessible through dedicated pins, it is possible to manage completely the VASP from the I²C interface without using SpaceWire.

4.1

Functional description

HIVAC core sequencer is implemented inside a Field Programmable Gate Array (FPGA) accordingly to the following functional diagram shown Fig. 3.

Fig. 3:

Core sequencer functional diagram

HIVAC core sequencer includes 8 main functional blocks:

For CCD 55-20 sequencing, CCD sequencer block generates 6 image clocks, 4 register clocks and 1 slow clock (Dump Gate).

4.2

Core sequencer selection

HIVAC core sequencer is implemented inside a FPGA. In the frame of the breadboard development Actel ProASIC PA3P1000 has been selected mainly for its on board programmability.

For Future FM units several candidate have been identified. The best candidate is the UT6325 from Aeroflex including RAM on Chip and compatible with a wide range of applications.

For applications requiring not so much programmability of detector sequencer blocks and no VASP I²C interface block, FPGA as Actel RT54SX32/72 can be used.

5.1

Time base selection

HIVAC breadboard embeds a 9MHz local oscillator. The HIVAC sequencing can be performed using this local oscillator or using an external master clock through a SMA connector.

5.2

Power distribution

All secondary supplies are post-regulated upstream HIVAC. Only regulators and op-amp for CCD and µbolometer interfaces are embedded on HIVAC breadboard.

All secondary supplies are filtered (Π filters) on HIVAC before being distributed to the HIVAC functions.

5.3

CCD and µbolometer Bias and clock levels setting

Adjustable regulators and/or op-amp + Ballast are used to supply CCD bias, µbolometer bias and clock drivers requiring current capability. The adjustment is performed using DACs programmed through the I²C link managed by HIVAC core sequencer.

The Architecture of CCD and µbolometer Bias and clock level setting blocks and associated devices have been selected to reach stringent low noise specifications required by most detectors. Moreover specific filtering have been implemented to reduce noise at high frequencies.

5.4

Detector clock driving

Dedicated monolithic phase drivers are used for CCD interface. For APS/CMOS clock driving, standard CMOS logic buffer are used.

6.1

HIVAC operating modes

The HIVAC module is able to operate in following working modes.

▪ OFF: HIVAC module is not supplied. This mode is obtained when all HIVAC input power supplies are OFF.

▪ ON: HIVAC module is supplied. This mode is obtained when HIVAC power supplies are ON. The biases at detector interface are fully operational and the detector is not sequenced. The HIVAC-VASP interface is fully operational. The HIVAC module is able to communicate with the VASP ASIC. The core sequencer is able to receive all the commands coming from the VASP. The VASP is able to be configured using SpaceWire interface.

From this ON HIVAC mode, VASP will be in NO VIDEO DATA mode for which VASP is able to be programmed through the SpaceWire interface, to communicate with the core sequencer for its configuration.

In this case, VASP is able to switch to RAMP mode and VASP CALIBRATION mode. VASP is not able to access to the OPERATIONAL mode because detector and video chain are not sequenced by HIVAC sequencer.

▪ SEQUENCED: This HIVAC mode enables detector sequencing. Analog video signals coming from detector (CCD or CMOS) are available on HIVAC interface.

From this mode, the accessible VASP modes are the same than in the previous HIVAC mode but in this case the video signal coming from detector is available at VASP input.

The VASP ASIC is able to operate in the following working modes:

The links between HIVAC and VASP modes are illustrated by Fig. 4.

Fig. 4:

HIVAC and VASP modes

24 RMAP messages have been defined for VASP communication (cf. Table 3) with User through SpaceWire network. Since HIVAC SpaceWire interface is integrated inside VASP, message definition are frozen except for SEQ_PARAM and SEQ_IMG messages whose final user is HIVAC core sequencer. For both messages, the content is application dependant and can be defined for future units during HIVAC core sequencer development (VASP has been defined to be independent and transparent regarding the content and the length of SEQ_PARAM and SEQ_IMG messages).

Table 3:

HIVAC SpaceWire messages

7.1

Detector management

7.2

Acquisition characteristics

7.3

Video Chain

7.4

Optical black correction

7.5

Specificity of HIVAC breadboard

Of course, HIVAC breadboard integrates specific programmability associated to the management of the selected detectors, in particular:

8.1

Connectors

Table 4 shows HIVAC breadboard connector list.

Table 4:

HIVAC breadboard connector list

8.2

Power supplies

Table 5 shows HIVAC breadboard power supply list

Table 5:

HIVAC breadboard power supply list

Future flight models based on HIVAC design and driving only one detector should need less than 7 secondary supplies.

8.3

Power consumption

Table 6 shows typical HIVAC breadboard Power budget.

Table 6:

HIVAC breadboard power budget

8.4

HIVAC performances

Table 6 gives an extraction of main HIVAC performances with typical power supplies and a 3MSps conversion rate. Typical values are given at 25°C.

Table 6:

Main HIVAC electrical characteristics