EPE fundamentals and impact of EUV: Will traditional design-rule calculations work in the era of EUV?

Allen H. Gabor; Andrew C. Brendler; Timothy A. Brunner; Xuemei Chen; James A. Culp; Harry J. Levinson

doi:10.1117/12.2297459

Translator Disclaimer

30 March 2018 EPE fundamentals and impact of EUV: Will traditional design-rule calculations work in the era of EUV?

Allen H. Gabor, Andrew C. Brendler, Timothy A. Brunner, Xuemei Chen, James A. Culp, Harry J. Levinson

Author Affiliations +

Proceedings Volume 10583, Extreme Ultraviolet (EUV) Lithography IX; 105830C (2018) https://doi.org/10.1117/12.2297459
Event: SPIE Advanced Lithography, 2018, San Jose, California, United States

Abstract

The relationship between edge placement error, semiconductor design-rule determination and predicted yield in the era of EUV lithography is examined. This paper starts with the basics of edge placement error and then builds up to design-rule calculations. We show that edge placement error (EPE) definitions can be used as the building blocks for design-rule equations but that in the last several years the term “EPE” has been used in the literature to refer to many patterning errors that are not EPE. We then explore the concept of “Good Fields”¹ and use it predict the n-sigma value needed for design-rule determination. Specifically, fundamental yield calculations based on the failure opportunities per chip are used to determine at what n-sigma “value” design-rules need to be tested to ensure high yield. The “value” can be a space between two features, an intersect area between two features, a minimum area of a feature, etc. It is shown that across chip variation of design-rule important values needs to be tested at sigma values between seven and eight which is much higher than the four-sigma values traditionally used for design-rule determination. After recommending new statistics be used for design-rule calculations the paper examines the impact of EUV lithography on sources of variation important for design-rule calculations. We show that stochastics can be treated as an effective dose variation that is fully sampled across every chip. Combining the increased within chip variation from EUV with the understanding that across chip variation of design-rule important values needs to not cause a yield loss at significantly higher sigma values than have traditionally been looked at, the conclusion is reached that across-wafer, wafer-to-wafer and lot-to-lot variation will have to overscale for any technology introducing EUV lithography where stochastic noise is a significant fraction of the effective dose variation. We will emphasize stochastic effects on edge placement error distributions and appropriate design-rule setting. While CD distributions with long tails coming from stochastic effects do bring increased risk of failure (especially on chips that may have over a billion failure opportunities per layer) there are other sources of variation that have sharp cutoffs, i.e. have no tails. We will review these sources and show how distributions with different skew and kurtosis values combine.

Conference Presentation

Citation Download Citation

Allen H. Gabor, Andrew C. Brendler, Timothy A. Brunner, Xuemei Chen, James A. Culp, and Harry J. Levinson "EPE fundamentals and impact of EUV: Will traditional design-rule calculations work in the era of EUV?", Proc. SPIE 10583, Extreme Ultraviolet (EUV) Lithography IX, 105830C (30 March 2018); https://doi.org/10.1117/12.2297459

ACCESS THE FULL ARTICLE