EUVL Gen 2.0: key requirements for constraining semiconductor cost in advanced technology node manufacturing

Arindam Mallik; Peter Debacker; Greg McIntyre; Ryoung-Han Kim; Kurt Ronse

doi:10.1117/12.2297447

23 April 2018 EUVL Gen 2.0: key requirements for constraining semiconductor cost in advanced technology node manufacturing

Arindam Mallik, Peter Debacker, Greg McIntyre, Ryoung-Han Kim, Kurt Ronse

Author Affiliations +

Proceedings Volume 10583, Extreme Ultraviolet (EUV) Lithography IX; 1058326 (2018) https://doi.org/10.1117/12.2297447
Event: SPIE Advanced Lithography, 2018, San Jose, California, United States

Abstract

The constant improvement of critical pitch reduction to enable the next generation semiconductor technology node is the primary driver for innovation in semiconductor industry. Previous researches [1] have shown the benefits of EUVL to bring down the wafer manufacturing cost for imec 7nm technology node. Beyond the technology node (N node) that will use EUV single patterning to enable the critical layers, the critical pitch enablement would require the second generation of EUVL lithography (high NA EUV) or double patterning EUVL(EUVL-DP). In this paper, we have provided a comparison between the two alternatives in terms of cost. We explored patterning options that would enable a costfriendly 5nm logic (N+1 node). The goal is to analyze the alternatives beyond the current 0.33 NA EUVL single patterning limit.

Citation Download Citation

Arindam Mallik, Peter Debacker, Greg McIntyre, Ryoung-Han Kim, and Kurt Ronse "EUVL Gen 2.0: key requirements for constraining semiconductor cost in advanced technology node manufacturing", Proc. SPIE 10583, Extreme Ultraviolet (EUV) Lithography IX, 1058326 (23 April 2018); https://doi.org/10.1117/12.2297447

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