2.1

Quantum Processing Units

In this section, we summarize the requirements and behaviors expected for large-scale general-purpose QPUs. The basic requirements expected for a quantum computer were first articulated by DiVincenzo,¹⁰ and we further define the general principles of operation for these abstract devices. These requirements follow from the expected basic usage for quantum computing hardware, which may in general be very broad. These criteria represent the minimal behaviors needed to perform general-purpose quantum computing in the presence of likely architectural constraints. Only a subset of these criteria may be required by specializing a QPU to singular function, e.g., a special-purpose device, or by engineering the quantum physical interactions to implement prescribed behaviors. We do not consider that case here.

First among the criteria is the ability to address elements within a scalable register of quantum physical systems. These register elements perform the role of storing information and scalability implies a manufacturing capability to fabricate and layout as many register elements as needed for a specific computational method. Second, these register elements must be capable of being initialized with high fidelity, as the starting quantum state of the computation needs to be well known to ensure accurate results. As described by Eq. (1), this amounts to preparing the quantum physical system(s) in a specific starting state. As a matter of convenience, the leading choice for register element design corresponds with a two-level system, in which orthonormal levels labeled 0 and 1 corresponding to binary values of information. The principles of quantum mechanics, however, permits two-level quantum mechanical system to also encode superpositions of these two levels, namely, |Ψ〉 = c₀ |0〉 + c₁ |1〉, where we have used |0〉 and |1〉 to denote the normalized basis for this two-dimensional system. The complex-valued coefficients c₀ and c₁ represent the probability amplitude to reside in the 0 and 1 state, respectively, and the general term for such a state is a qubit. According to the quantum theory, the modulus squared characterizes the probability to observe the physical system in the corresponding basis state, e.g., the probability to observe the 0 state is p₀ = |c₀|², and similarly for 1. The second criterion implies that the levels 0 and 1 must be well-defined within the register element and that the ability to initialize the register element to a specific value of c₀ and c₁ is available. The third basic criterion for a quantum computer is the ability to measure register elements in this well-specified basis. As measurement corresponds to a sample drawn from the statistical distribution encoded by the quantum state according to the probabilities p_i over a given basis set, each measurement must accurately reflect the underlying distribution. Therefore, measurement is sampling and represents readout from the register of the quantum computer, which produces a classical binary value that may be subsequently processed.

The fourth criterion states the control over the register must include the ability to apply sequences of gates drawn from a universal set. Universality of the gate set characterizes the potential to perform an arbitrary unitary operation on the quantum state using a sufficiently long series of gates from that set. In particular, it is known that a finite set of gates is sufficient to approximate universality and, moreover, that a finite set of addressable one- and two-qubit gates are sufficient for universality.¹¹ The latter result, known as the Solovay-Kitaev theorem, provides a constructive method for composing arbitrary gates from a finite, universal gate set. Selection of a universal gate set raises the question of the optimal instruction set architecture for an intended application within a specific device technology¹². The fifth criterion is that the gate operation times must be much shorter than the characteristic interaction times on which the register couples to other unintended quantum physical systems. These interactions induce decoherence of the stored quantum superposition states, which leads to the loss of information.^{13, 14} In order to maintain the stored quantum state with sufficient accuracy, the duration of the gate sequence must be much shorter than the characteristic decoherence time. Fault-tolerant protocols for gate operations are designed to counter the losses from decoherence and other errors by redundantly encoding information with quantum error correction codes.¹⁵

Two additional functional criteria are necessary for operating a quantum computer with geometrical constraints on the layout of the quantum register elements. In particular, layout constraints may impose restrictions on which register elements can be addressed by multi-qubit gates, e.g., nearest neighbors within a two-dimensional rectangular lattice design. Physical layout restrictions may be overcome by moving stored quantum states between register elements. This is accomplished using the SWAP gate, a unitary operation that exchanges the quantum state between two register elements. In addition, a MOVE operation can support long distance transport of a stored value, in which the register element itself is displaced. The latter proves useful for distributed quantum registers that may requires interconnects, aka communication buses, to SWAP register values. The necessity of these functions depends on the purpose of the quantum computer and especially the limitations of the technology. Presently, all technologies for quantum computing face some constraints on register layout.

2.2

Component Model for a QPU

There are several different realizations of the quantum computational model which vary according to how the unitary operators, or gates, are implemented. We summarize two of the most prominent examples. The circuit model represents the sequence of unitary operators as an ordered sequence of discrete gates applied individually to register elements or perhaps applied to some subset of elements. The single and multi-qubit gates may be applied in series or in parallel depending on constraints placed on their execution. By contrast, the adiabatic model of quantum computation uses a single continuous time unitary applied global to all qubits simultaneously. Moreover, the applied operator must be restricted to adiabatically evolve the register, in which adiabaticity is defined according to the rate of change of the Hamiltonian relative to the internal energy scale of the quantum register. Nevertheless, the principles of operation for all of these quantum computational model begins with initializing the quantum register into a well-defined fiducial state followed by series of unitary operators applied to the register in series or parallel, and concluding with the register measured to generate the readout from the computation. This readout may be used to generate feedback that determines the next sequence of gate operations.

In Fig. 1, we present a component model capable of satisfying the functional requirements expected of a quantum processing unit. As we shall show, this model for QPU structure not only aligns with established separation of concerns in computer programming but it also mirrors the current implementation of experimental quantum processors. In general, a QPU defines a computational system that can allocate, initialize, transform, and readout a quantum register. The register is composed from addressable elements that store the quantum computational value, i.e., the quantum state representing a computational outcome. An individual quantum register element is modeled as a two-level quantum physical system capable of storing a single qubit of information. An array of n such elements has the capacity to store n qubits of information and, more generally, a quantum state in an 2ⁿ-dimensional Hilbert space.

Figure 1:

(left) Components of a computing node may include a CPU, memory system (MEM), GPU, and network interface (NIC) alongside a quantum processing unit (QPU). (right) A QPU may be decomposed into a quantum control unit (QCU) that manages quantum execution units (QEUs) that apply gates onto a register.

As quantum algorithms may be composed using gates applied to the register, it becomes necessary to implement multi-qubit gates in the general case. As noted above, multi-qubit gates are, at minimum, well approximated by sequences of one and two-qubit gates. Yet constraints imposed by the layout of the quantum register may limit the connectivity of multiple register elements. As some physical gates require that multiple elements be simultaneously addressable and spatially proximate due to the underlying Hamiltonian interactions. We therefore define register connectivity as the addressability of multiple elements during physical gate operation and we represent it by a graphical model of the possible interactions at any given instance of operation. Examples of the register connectivity include a complete graph, a linear chain (path graph) and a two-dimensional lattice (lattice graph). The connectivity of the register may not support gate operation requirements and, for these instances, additional swap instructions may be issued to reassign data stored in the register elements. However, modifying the register to satisfy a pending gate operation must be synchronized with subsequent instructions in order to ensure program correctness.

Applying gates to the quantum register elements implements control of the Hamiltonian H(t) in Eq. (1). The leading approach to affect this control is the tailored application of analog fields, including optical, electrical, and magnetic, to the quantum physical system. Depending on the nature of the physics and the coupling interaction, the timing, amplitude, and phase of the field are designed to drive the encoded quantum state to a desired outcome. The efficacy of this design depends on the noise in the field generation and delivery as well as the extraneous coupling between other quantum physical systems. We model the components within the QPU that carry out the synthesis and delivery of the analog field to the quantum register as the quantum execution unit (QEU). Moreover, multiple QEUs may exist with each specialized by its gate execution or connectivity constraint. In practice, QEUs are implemented using arbitrary waveform generators (AWGs), which take as input specification for a waveform design and produce as output a desired analog electrical field. Less robust implementations may rely on function generators to perform the same task with limited variability. In either case, the output electrical field drives a signal generator of the necessary type, for example, modulated laser, microwave or radio frequency generator, etc., as required by the gate design.

The QEUs also serve to implement measurement, which is important for readout from the quantum register. Measurement of the register requires the detection of a field that characterizes the quantum physical state within a specified basis. This may include detection of the field to have a specific energy, time of arrival, current, voltage, etc. that characterizes the state in the defined basis. Often times, the QEU must apply a field in order to trigger a response from the register that may be detected. This requires synchronization between the application of the trigger field and the detection of the response field. This synchronization may come from either temporal scheduling of the fields, i.e., windowing, or it may results from spatial synchronization, e.g., dedicated channels. In either case, detection of the response field becomes a decision as to whether the field was present or not. This is a translation from the analog to digital domain and represents gate execution.

We have ascribed to QEUs the direct application of gates to register elements but the decision to apply a specific gate is made elsewhere. The component responsible for dictating the flow of gate execution is the quantum control unit (QCU). Given a sequence of instruction which must be carried out by the QPU, the role of the QCU is to decide how to carry out those instructions. This separation of concerns in the execution of a program is made to ensure that the tasking of multiple QEUs can be optimized with respect to the available resources and pending gate applications. In particular, the QCU must configure the flow of data to the relevant QEUs and this may necessitate decisions that decode the received instructions to achieve the desired logic. The resulting sequences of gates, or operands, that perform the equivalent logic as the original instruction may similarly generate a response that requires subsequent interpretation by the QCU. The implementation of the QCU may rely on fixed logic, for example, using application-specific integrated circuits (ASICs), or it may be implemented using conditional logic. In either, the translation of an instruction into a sequence of operands requires the QCU to have a fine grain understanding of register connectivity, QEU functionality, scheduling constraints, and timing of gate executions.

The QCU implements the instruction set architecture (ISA) that is native to the QPU. The ISA exposes the functionality of the QPU and provides the interface by which processing requests are submitted. The ISA for a QPU may be tailored to the underlying technology by accounting for the constraints of register layout and gate execution that arise from the type of physical system, the computational model, and the signal generators. Moreover, the choice of ISA enables the QPU developer to tailor the interface to specific application concerns and computational models. This includes future definitions for standardized ISAs that enable portability between processing requests. This description emphasizes that the ISA provides a specification of the operations that can be interpreted by the QCU and translated into QEU operands. However, the ISA may also include conventional logic that is interpreted by the QCU. This includes conditional statements for which different instruction branches are executed depending on the local state of the QPU. For example, measurement outcomes may be used to evaluate conditions as to whether additional instructions must be performed to ensure a register is prepared in the desired state.

A notable concern for future QPU implementations is the development of fault-tolerant protocols that enable resilient execution of instruction sequences. The theory of fault-tolerant quantum computing currently relies on redundant encoding of the stored quantum state through the use of quantum error correction codes. Monitoring the collective encoded state through syndrome measurements using ancillary elements provides feedback that can trigger a corrective action by the QPU. An important design choice for future fault-tolerant QPUs is where to allocate this functionality. In our description of components within a QPU, it is not possible for the QEU to trigger measurement-driven feedback due to a lack of conditional logic. In addition, the QEU may be specialized to a given gate operation or subset of register elements that inhibit the ability to carryout QEC. Therefore the QCU is the default component from which fault-tolerant protocols may be implemented. An alternative to this design choice is to allocate management of the fault-tolerant protocol to a component outside of our current QPU model. While this alternative is perhaps likely for near-term QPU experiments, the design choice faces the burden that the necessary knowledge about the register state, the translation of instructions into operand sequences, and the constraints placed on the QEU execution must be exposed to the external manager.

3.1

Simulation Method

We have presented a model for the components of a hybrid computing system, a hierarchy of languages to communicate between these components, and a model for how these components execute the communicated instructions. In order to simulate this model, we rely on a discrete-event simulator, in which events represents transactions between components in the form of transmitting and receiving messages. The message packets deliver information that dictates the behavior of the receiving component. For example the QCU receives a messages packet relaying a sequence of instructions within the specified ISA while the QEU receives a packet specifying the gate operation codes issued by the QCI. Each component processes the received message packets according to a behavioral model that defines how subsequence messages, i.e., events, are generated.

We model the entire system using the Structural Simulation Toolkit (SST), a discrete-event simulation framework that has been used previously for modeling GPU accelerator architectures. SST provides a core discrete-event simulator, including an event manager, as well as a framework of classes, methods, and data types to model development. In addition, SST offers a variety of existing components that can be reused in our quantum-accelerator model. In particular, models for the memory hierarchy that includes main memory, cache, and memory controllers are useful for interfacing conventional CPU models with new QPU models. We extend the framework by introducing new quantum components that model the QPU, QCU, QEU, and register. These extensions are then customized to a chosen implementation of the language hierarchy and the necessary message packets are defined according to the component interface language.

The purpose of the simulation is to gain insight into the behavior and performance of the hybrid computing system. Performance may be quantified in terms of metrics such as time and energy, while behavior may be quantified by correctness in program execution as well as performance robustness with respect to changes in program design. We use the SST model to quantify the time required for program execution as well as the energy consumed. These metrics can be estimated by sampling the simulation and accumulating statistics that represent the aggregate behavior.

An SST model is defined by first specifying and then programming the necessary components using C/C++. These component classes are then compiled into a shared library that provides a Python wrapper to each method. The SST model is then composed by declaring instances of the components within a Python script and linking those components together into a defined network. Executing the Python script within the SST run-time environment initiates the discrete-event simulator to start simulating each component. Events are generated when each components interfaces with the simulations messaging systems, and the event manager routes these messages to the destinations based on the established connectivity. A fundamental parameter within the simulation is the clock that describes the frequency with which the event manager monitors changes in components. In addition, there are clocks for each component that define the frequency with which the internal state is refreshed. These clocks can be tuned to vary the granularity of the simulation. In addition, the initial state of the components can be defined by passing parameters when the components are declared.