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20 July 2018 Design of two ASIC chips for scientific CCD detectors
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Abstract
In order to implement the driver and readout functions for several types of scientific CCD detector, meanwhile decreasing the size of electronics and reducing the total power dissipation for a large scale mosaic CCD detector system, two Application-specified Integrated Circuits (ASIC) were designed. One is for CCD driver and called BCDA (Bias Clock Driver ASIC), which is to provide multi-channel clocks and Bias voltage; the other is for CCD video processing and called CVRA (CCD Video Readout ASIC). In the BCDA chip, the bias drivers are generated by high voltage amplifiers. The clock drivers are made of a clock switch circuit and high voltage amplifier. Two 8-bit current-steering DACs are used to adjust the driver capability and high-level voltage of clocks. The CVRA chip processes the video signal of a CCD detector. The functions of CVRA chip consist of pre-amplifier, single-to-differential circuit, CDS circuit, and integrating circuit. The Global Foundry 180 nm BCDlite technology is used in this chip design. The first round of design has been finished and part of tests of two chips have been done.
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Dong-xu Yang, Jie Gao, Yi Feng, Wen-qing Qu, Jian-min Wang, Hong-fei Zhang, and Jian Wang "Design of two ASIC chips for scientific CCD detectors", Proc. SPIE 10709, High Energy, Optical, and Infrared Detectors for Astronomy VIII, 107091U (20 July 2018); https://doi.org/10.1117/12.2311419
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