Silicon photonics is gaining increasing adoption for mid- to long-reach communication links in datacenters at 100Gbps and beyond. Two significant challenges remain integrated on-chip WDMs, and fiber and laser packaging.
The adoption of wavelength division multiplexing (WDM) allows for multiple data signals to be carried on a single fiber, reducing the cost of fiber provisioning compared to parallel implementations and greatly increasing achievable data rates. Designing WDM structures can be challenging on a silicon platform, however, as silicon waveguides are highly sensitive to minute fabrication variations and temperature changes. To account for and compensate for these changes, it is necessary to have a robust testing methodology to characterize the WDM system, as well as an efficient and complete tuning mechanism to dial in the desired performance without sacrificing too much in power consumption, chip area for off-chip electrical connections, and insertion loss. We will present a monolithic silicon WDM design, the implementation of low power tuning elements, and the test and biasing algorithms to align all filters on the desired CWDM grid.
Another perennial challenge for silicon photonics has been coupling light on and off the chip, due to the significant mode size mismatch and exacting alignment requirements between silicon waveguides and optical fibers or III-V chips. We will present on packaging developments implementing fully passive alignment using existing CMOS production tools, improving scalability and cost efficiency and enabling the packaging techniques for silicon photonics chips to keep up with the massive volumes generated by silicon waferscale fabrication.