A low cost alternative lithographic technology is desired to cope with the challenges in decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the viable candidates.  NIL has been a promising solution to overcome the cost issue associated with expensive process and tool of multi patterning and EUVL. The challenges of NIL implementation for mass-production are overlay, defects, throughput, template life, and template patterning. The overlay and defects must satisfy the requirements of the products applied. The throughput needs to provide adequate cost of ownership (CoO). Since NIL is a contact process, its template damage by the particles on a wafer is inescapable and a longer template life is required for mass production.- In our previous study, we have reported that the hp2xnm NIL process performance is getting closer to the requirement for the high volume manufacturing. We focused on the process overlay accuracy and demonstrated dramatic reduction of process overlay error by using CVA(controlled viscosity alignment) and HODC(high order distortion control) function of FPA-1200 NZ2C.  Currently, we have further developed a nanoimprint lithography (NIL) technology including NIL system, template, and resist process for half pitch 14 nm direct pattering. The hp14 nm template was fabricated by a self-aligned double patterning (SADP) on a template. Using this template, we fabricated hp 14 nm dense Si lines with a depth of 50 nm on a 300 mm wafer. In this paper, we report on the latest lithography performance of NIL including hp14nm pattering with single mask exposure.