EUV computational lithography using accelerated topographic mask simulation

Vitaly Domnenko; Bernd Küchler; Wolfgang Hoppe; Jürgen Preuninger; Ulrich Klostermann; Wolfgang Demmerle; Martin Bohn; Dietmar Krüger; Ryoung Ryoung Han Kim; Ling Ee Tan

doi:10.1117/12.2515668

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4 April 2019 EUV computational lithography using accelerated topographic mask simulation

Vitaly Domnenko, Bernd Küchler, Wolfgang Hoppe, Jürgen Preuninger, Ulrich Klostermann, Wolfgang Demmerle, Martin Bohn, Dietmar Krüger, Ryoung Ryoung Han Kim, Ling Ee Tan

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Proceedings Volume 10962, Design-Process-Technology Co-optimization for Manufacturability XIII; 109620O (2019) https://doi.org/10.1117/12.2515668
Event: SPIE Advanced Lithography, 2019, San Jose, California, United States

Abstract

As EUV lithography is getting ready for deployment in high volume manufacturing, lithography engineering focus moves to efficient computational lithography tools (mask correction, verification, source-, mask- and processoptimization) providing optimal RET solutions for EUV early design exploration. Key to computational lithography success is the prediction ability of the underlying lithography process simulation model. Topographic mask effects prediction is one of the major challenges with significant impact on both simulation quality of results and turn around time. In this paper, we apply a fast modeling approach to EUV light diffraction on topographic masks, which is based on fully rigorous topographic mask simulations. It is demonstrating performance benefits of several orders of magnitude while maintaining the accuracy requirements for productive cases. We explore its applicability to medium sized computational lithography tasks. The accurate mask solver results will be complemented with imaging and 3D resist simulations using the rigorous lithography simulator S-Litho by Synopsys.

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Vitaly Domnenko, Bernd Küchler, Wolfgang Hoppe, Jürgen Preuninger, Ulrich Klostermann, Wolfgang Demmerle, Martin Bohn, Dietmar Krüger, Ryoung Ryoung Han Kim, and Ling Ee Tan "EUV computational lithography using accelerated topographic mask simulation", Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 109620O (4 April 2019); https://doi.org/10.1117/12.2515668

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