1.

INTRODUCTION

To date, the semiconductor industry has invested billions of dollars on the development of EUV lithography. For example, an early consortium dedicated to the development of EUV lithography, the EUV LLC, involved an investment of more than $270M.¹ Later, consortia such as INVENT² and imec invested additional hundreds of millions of dollars into EUV lithographic technology. Companies producing key elements of EUV infrastructure such as mask blanks, inspection tools, resists, and exposure systems have also made significant investments into EUV technology. For a single company that fabricates chips, it has been estimated that a minimum initial capital investment of one billion dollars is needed to start using EUV lithography in high-volume manufacturing (HVM).³ Whether or not companies realize a positive return on their investments in EUV technology is dependent on the semiconductor industry’s ability to extend the technology to future nodes and how much more investment will be required. No insurmountable problems for extensibility have been identified, but several issues need to be confronted, with solutions identified and implemented in order to extend EUV lithography beyond one or two nodes.

2.

EXTENDING EUV LITHOGRAPHY SINGLE PATTERNING AT 0.33 NA

3.

EUV MULTIPLE PATTERNING

Immersion ArF lithography at 1.35 NA has been used in manufacturing for almost a decade, having been extended to additional nodes by the use of multiple patterning. Consequently, it is natural to contemplate a similar extension of EUV lithography. The problems with EUV single patterning described in Section 2 have provided additional impetus for such considerations at larger values of k₁ than the entry point for immersion multiple patterning.

While developing immersion double patterning, technologists began to recognize significant increases in patterning costs due to the increase in the number of process operations, and steps were taken to compensate for these extra costs, including layout modifications and deeper shrinks than the traditional node-to-node 0.7× linear scaling. If we assume that EUV lithography is first used in HVM for processes with 40 nm metal pitches, this implies that the pitch for second generation EUV lithography needs to be < 28 nm if double patterning is required. At such tight pitches, the process control budget needs to be studied in detail.

A typical situation involving multiple patterning is depicted in Fig. 1. Proper processing requires that the block feature overlays the line it is intended to block, while not encroaching on a neighboring line. This process control requirement can be estimated from the following condition for the variation in G:

Figure 1.

Schematic of block masking for a line-space pattern generated using a spacer process.

where OL is the overlay variation (3σ), and ΔS and ΔB represent the variations in the dimensions S and B. In Eq. 1, it is assumed that the total variation is the root sum of squares of the variation of the components. For illustration, consider a situation involving a 20-nm pitch line/space pattern consisting of equal lines and spaces. If we further assume that critical dimensions are controlled to ±15%, and the overlay control is 3.0 nm (3σ), then 3σ_G = 3.4 nm. Even using 4σ_G = 4.6 nm as the target for process control in high-volume manufacturing (HVM), it would seem that the level of process control is adequate for using double patterning to fabricate 20 nm pitch line/space patterns. However, due to stochastics, this may not be the case.

The statistics of process control have been changing as stochastics have become more significant. Controlling processes to ±4σ has long been used in high-yield manufacturing. Since processes controlled to this level have 63 ppm failure rates (assuming normal variation), it might seem not possible to yield circuits with billions of transistors. However, it has been possible to yield such large circuits at this level of process control, because occurrences that are out-of-specifications for parameters such as critical dimensions and overlay do not occur randomly in optical lithography. This is shown schematically in Fig. 2. Over much of the wafer (area A), the relevant process parameters are within specification, while on a different part of the wafer (area B) they are not. In area B, where the out-of-specification conditions occur, there are often multiple locations in which the relevant parameter is out-of-specifications. Thus, devices with billions of transistors can yield even with processes controlled only to ±4σ, because the failures do not occur randomly: chips in area A can yield, while those in area B will likely not.

Figure 2.

Illustration of non-randomness. For process parameters, such as overlay, values may be within specifications throughout area A of a wafer, while being out of specifications at multiple locations in area B.

In EUV lithography, the situation is different, because of stochastic phenomenon. It has been argued that LER should be added to Eq. 1,³⁶ resulting in:

Moreover, LER should be included at the 6σ or 7σ level. If LER is only 1.5 nm (3σ), then the “4σ” level of control for G increases to 7.3 nm. This means that the smallest pitch for which double patterning is possible is ~28 nm. At tighter dimensions, self-aligned block masks would be required, leading to triple or quadruple patterning.³⁷ Since EUV lithography is expected to be on-par with the costs of immersion triple patterning, adding additional EUV exposures is a very expensive proposition.

It has been argued that the cost of EUV multiple patterning is mitigated because each exposure step can be done at low exposure dose. If the line-space pattern illustrated in Fig. 1 is created using EUV lithography and a spacer process, the linewidth roughness (LWR) will be low, but the line-edge roughness LER remains. Consequently, if low dose resists are used, the resulting LER will increase the minimum pitch which can be patterned using double lithography. Moreover, the throughput advantage of low dose does not scale directly with the dose. Consider the graph in Fig. 3. At 250 W source power (at intermediate focus), the throughput with a resist sensitivity of 20 mJ/cm² is slightly more than 50% greater than the throughput with a resist sensitivity of 40 mJ/cm². This means that the exposure tool capital cost of double patterning at 20 mJ/cm² is about 30% greater than single patterning at 40 mJ/cm². For actual double patterning, there are the additional costs of masks, consumables and non-lithographic operations, so double exposure at low dose is a costly solution. It is worth noting that EUV multiple patterning is being discussed for NA = 0.33 because of persistence in targeting EUV lithography at low exposure doses, which prevents single patterning at values of k₁ which are low but consistent with optical resolution. This contrasts with what occurred in optical lithography, where multiple patterning was widely used only after limits were reached for numerical aperture and wavelength reduction, and there were no optical lithographic alternatives to multiple patterning consistent with the laws of physics. Similarly, consideration of multiple patterning with EUV lithography is sensible once limits to numerical aperture and wavelength have been met. Higher numerical aperture for EUV lithography is the topic of the next section.

Figure 3.

Output per day of a single EUV cluster.³⁸ This graph was based on assumption of 88% system availability and 75% utilization.

4.

HIGH NA EUV LITHOGRAPHY

Prior lithographic technologies, such as i-line, KrF and ArF lithography, have been applied to multiple nodes, primarily through increases in numerical aperture over time. This occurred in ArF optical lithography until a physical limit to numerical aperture was effectively reached. In a similar manner, Zeiss and ASML are developing EUV optics and exposure tools at 0.55 NA. The challenges of fully enabling high-NA EUV lithography have been discussed previously,¹⁵ and a summary is provided in Table 1. The issue of resist stochastics, including photon shot noise, was discussed in Sec. 2.1. It has been argued that high-NA EUV lithography will help to address the problem of stochastics by providing an aerial image with greater acuity. However, this is an expensive solution to the problem of stochastics. It means that the full potential of EUV lithography at NA = 0.33 will be unrealized. To parallel what occurred in optical lithography, single patterning at NA = 0.33 down to k1 ≈ 0.3 (24 nm pitch) is needed, followed only then by the introduction of high numerical aperture. Finally, multiple patterning would be used after a practical limit to NA has already been reached.

Table 1:

Technical and cost challenges for enabling 0.55 NA EUV lithography

At NA = 0.55, the Rayleigh depth-of-focus will be only 45 nm. It will be very challenging to control focus to this level. To reduce the impact of mask 3D effects, these high-NA systems have anamorphic lenses with reduced field sizes.³⁹ This will have an impact on the productivity of high NA tools, particularly for fabricating dies too large to fit into a single reduced-size exposure field (necessitating stitching), thereby adding to the return-on-investment challenge. New generations of lithographic technology have often required construction of new fabs that can support the facilities requirements of new tool sets. While the technical issues are straightforward, this will require additional investments. Changes of numerical aperture also necessitate acquisition of new tools for mask making, such as AIMS tools. Finally, realization of the full theoretical resolution potential of 0.55 NA optics will require control of polarization. Coupled with the small depth-of-focus at NA = 0.55, there would be value in having variable numerical aperture for future EUV exposure tools. High NA EUV exposure tools are also expected to cost considerably more than current 0.33 NA tools, leading to additional return-on-investment challenges. All of these should be viewed as problems that soluble – there are no apparent show-stoppers currently recognized for high-NA EUV lithography.

5.

SUMMARY

There is good potential for the semiconductor industry to get a positive return-on-investment for EUV lithography by extending the technology to multiple nodes. Cost-effective extension will require that stochastic-induced resist process variations, including defects, be controlled to adequate levels. This may necessitate development of resists that are very different from the types of chemically amplified resists that have been used in leading-edge lithography for decades. Sufficiently powerful light sources will be needed to bring photon shot noise to acceptable levels without excessively reducing exposure tool throughput. Multiple patterning can be used to shrink pitches further, but this makes sense only after EUV lithography has been extended to a maximum NA. At that point, triple or quadruple patterning will be required for line/space patterns, because edge pattern placement errors necessitate self-aligned block masks. High numerical aperture EUV lithography is undergoing development and offers a useful path for extending EUV lithography, once basic technical issues associated with the new technology are addressed.