2.1

SERDES

Serializer and De-serializer (SERDES) have become popular gradually in past decades. FPGA first employed SERDES in Virtex II Pro family in 2002. It was only a few high-end family members with limited number of SERDES channels of only 3.125Gpbs. Today in 16nm Ultrascale-plus family, SERDES have been much proliferated with higher performance. For example the UV-29Plus has 48 channels of 58Gbps PAM4 and 32 channels of 32Gbps SERDES. The VU-13Plus has 120 channels of 32Gbps SERDES. Both are in a 3D-IC integration. These high speed and large number of SERDES channels become essential in communication industry.

Not only 58Gbps PAM4, Xilinx also demonstrated 112Gbps SERDES [3], and it will be a part of 7nm Versal family offering.

To incorporate SERDES design into FPGA, one key challenge is timing – one needs to be able to bring complicate RF design at early development stage of a technology, not just waiting for its matureness. This requires in-depth understanding the technology, analyzing existing data and forecasting its RF behavior in RF modeling. Xilinx has spent major effort to master this aspect.

Beyond 112Gbps, industry has not had clear conclusion the roadmap. Xilinx believes optical photonics integration could be one of the options, and has been studying accordingly.

Below Figure 3 lists publications showing the evolution of SERDES in past a decade and half.

Figure 3:

SERDES performance in various technology nodes (ISSCC, VLSI, CICC, ASSCC, etc.)

2.2

Embedded micro-processors, SOC and RFSOC

In the same Virtex-II Pro family in 2002, it was also the first time a micro-processor, PowerPC 405 (PPC405), embedded into certain high-end FPGA family members. A major effort was spent to ensure intimate connections between PPC405 to programmable logic fabric. The embedded micro-processor enabled many new high-end industrial and communication FPGA applications.

However the application usage of embedded micro-processor has still be relatively limited, until the 28nm 7-Series Zynq SOC family in 2012 time frame. The 7-Series Zynq had a much more popular, lower cost ARM A9 processor, with vast effort to build it not only a connected processor but far more capable SOC, which includes memories, IOs and large amount of system software to support applications. The 7-Series Zynq SOC attracted a lot more applications in all range (including very low cost ones).

In 2016 the 16nm Ultrascale-Plus FPGA products, this ARM based SOC has been further upgraded into MPSOC and RFSOC. The MPSOC was an order of magnitude more sophisticate and capable (multiple ARM A53 and AMR R5 with GPU + video + Codec) than the original 7-Series Zynq SOC; the RFSOC built 4Gbps ADC and DAC (Analog to Digital Convertor and Digital to Analog Convertor) [4]. Combined with MPSOC and RFSOC capability, they become perfect candidate of today’s 5G wireless front-haul applications.

Figure 4 is an illustration of a 16 TRX MIMO (Multi-Input Multi-Output) antenna design in a 3.5Gbps 5G NR (New Radio), by using ZU-29DR RFSOC. Because of the integration of ADC and DAC, and the massive capability of MPSOC, it serves beam-forming, DFE (Digital Front End) and ADC/DAC functions. It reduces power, cost and footprint drastically, and allows system change by its programmability, to suit today’s 5G initial deployment which still faces many uncertainties. It is a very successful example of how adding right functionality will expand capability of FPGA and benefit the end user ultimately.

Figure 4.

An illustration of using RFSOC in a 5G NR 16 TRX MIMMO 3.5Gbps band design

Similar to design and integration of SERDES in FPGA during a not-so-mature technology node, bring up ADC and DAC also requires strong technical capability of predicting and modeling the analog and RF behavior of a new technology.

2.3

HBM integration

Logic and DRAM memory technology development have long been parted. Each optimizes for better technology capability, market needs and cost. Thus integrating DRAM and logic in system in past was mostly through DDR interface. For wide bandwidth DRAM connections, large amount of DDR IOs are needed. Even so the bandwidth is still limited, power and latency still high.

HBM (High Bandwidth Memory) is a stacked DRAM cube using 3D-IC with uBump (micro-bump) and TSV (Through Silicon Via). Because its wide (1024 channel in HBM-2) and high speed (2~3 Gbps in HBM-2), its bandwidth, power and latency are un-surpassable. Integrating HBM to a logic IC also needs to employ passive 3D-IC technologies, such as CoWoS (Chip on Wafer on Substrate) and others.

In the 16nm Ultrascale-Plus FPGA family, HBM integration becomes available, which largely expands on-chip data processing capability because of ultra-wide bandwidth with low power and low latency. Figure 5 showed an illustration of FPGA integrated with 2 HBMs [5].

Figure 5.

An illustration of an Ultrascale-Plus FPGA integrated with 2 HBMs

The key to succeed in HBM integration relies on Xilinx’ long and successful experiences of 3D-IC SSIT (Stacked Silicon Integration Technology) since 2011, as well as industry’s volume production learning.

3.1

EUV readiness in 7nm and possible application

In TSMC’s 7nm technology, critical layers are all using immersion multi-patterning with uni-directional design. TSMC’s 7-Plus platform, will adopt several EUV lithography.

Potential use of EUV for better uniformity thus better power-performance (for example in MEOL (Mid-End of Line) to reduce resistance), will be assessed.