Process related yield risk mitigation with in-design pattern replacement for system ICs manufactured at advanced technology nodes

Jaehwan Kim; Jin Kim; Byungchul Shin; Sangah Lee; Jae-Hyun Kang; Joong-Won Jeon; Piyush Pathak; Jac Condella; Frank E. Gennari; Philippe Hurat; Ya-Chieh Lai

doi:10.1117/12.2551970

23 March 2020 Process related yield risk mitigation with in-design pattern replacement for system ICs manufactured at advanced technology nodes

Jaehwan Kim, Jin Kim, Byungchul Shin, Sangah Lee, Jae-Hyun Kang, Joong-Won Jeon, Piyush Pathak, Jac Condella, Frank E. Gennari, Philippe Hurat, Ya-Chieh Lai

Author Affiliations +

Proceedings Volume 11328, Design-Process-Technology Co-optimization for Manufacturability XIV; 113280I (2020) https://doi.org/10.1117/12.2551970
Event: SPIE Advanced Lithography, 2020, San Jose, California, United States

Abstract

Process and reliability risks have become critically important during mass production at advanced technology nodes even with Extreme Ultraviolet Lithography (EUV) illumination. In this work, we propose a design-for-manufacturability solution using a set of new rules to detect high risk design layout patterns. The proposed methods improve design margins while avoiding area overhead and complex design restrictions. In addition, the proposed method introduces an in-design pattern replacement with automatically generated fixing hints to improve all matched locations with identified patterns.

Conference Presentation

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Jaehwan Kim, Jin Kim, Byungchul Shin, Sangah Lee, Jae-Hyun Kang, Joong-Won Jeon, Piyush Pathak, Jac Condella, Frank E. Gennari, Philippe Hurat, and Ya-Chieh Lai "Process related yield risk mitigation with in-design pattern replacement for system ICs manufactured at advanced technology nodes", Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280I (23 March 2020); https://doi.org/10.1117/12.2551970

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