Presentation + Paper
24 February 2021 EUV single exposure via patterning at aggressive pitch
Author Affiliations +
Abstract
As the semiconductor industry continues pushing Moore’s law to the next node, interconnect structures scaling will be a key element to performance improvement of functional devices. However, the requirements for low LCDU and defectivity of these interconnect structures have become more stringent with continuous scaling. In this paper, a fundamental study is conducted to understand the impact of various factors on the patterning of EUV single exposure vias, and to find effective strategies to shrink CD while improving LCDU and defectivity. The work is based on a 40 nm pitch orthogonal via array baseline, and probes different patterning factors including illumination, resist materials, stack, scanner, and develop methods for LCDU improvement and defectivity reduction. The patterns are transferred to bottom dielectrics to study the evolution of LCDU and defectivity during etching.
Conference Presentation
© (2021) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jing Guo, Jennifer Church, Luciana Meli, Anuja de Silva, Martin Burkhardt, Karen Petrillo, Mary Breton, Cody Murray, Lijuan Zou, Allen Gabor, and Nelson Felix "EUV single exposure via patterning at aggressive pitch", Proc. SPIE 11609, Extreme Ultraviolet (EUV) Lithography XII, 116090U (24 February 2021); https://doi.org/10.1117/12.2582563
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KEYWORDS
Optical lithography

Etching

Semiconducting wafers

Stochastic processes

Resolution enhancement technologies

Extreme ultraviolet lithography

Scanners

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