e-Beam detection of over-etch in semiconductor processing and how over-etch level is related to defect detection parameters

Kwame Owusu-Boahen; Chang (Carl) Han; Ching Hsueh; Chulwoo (Jake) Kim; Arun Vijayakumar; Fnu Devender; David J. Moreau

doi:10.1117/12.2584652

22 February 2021 e-Beam detection of over-etch in semiconductor processing and how over-etch level is related to defect detection parameters

Kwame Owusu-Boahen, Chang (Carl) Han, Ching Hsueh, Chulwoo (Jake) Kim, Arun Vijayakumar, Fnu Devender, David J. Moreau

Author Affiliations +

Proceedings Volume 11611, Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV; 116110N (2021) https://doi.org/10.1117/12.2584652
Event: SPIE Advanced Lithography, 2021, Online Only

Abstract

Some over-etch (OE) related defects in semiconductor device processing are only obvious after vias or trenches are already filled. Such defects are usually buried and often discovered after failure analysis from failed devices. Inline detection by physical means using optical inspection tools is not possible. e-Beam inspection has the ability to detect this type of defect electrically. OE related defects create shorts or leakage paths and their ability to cause device failure depends on the level or extent of this leakage. Hard OE fail impacts yield while marginal OE is relatively harmless. e-Beam inspection detects both hard OE fail and marginal OE as bright voltage contrast (BVC) and it has always been a challenge to discern yield impacting hard OE fail from the relatively harmless OE based only on the defect images. TEM analysis is often necessary to distinguish between the two. In this paper attempt is made to relate the extent of OE to e-Beam defect detection parameters, Threshold (TH) and Grey Level (GLV). Correlation between the amount of OE and each of the two parameters is established. Also a correlation is found among the two parameters themselves. With these relationships established, the e-Beam defect detection parameters alone can be used to predict OE’s potential impact on yield without TEM analysis.

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Kwame Owusu-Boahen, Chang (Carl) Han, Ching Hsueh, Chulwoo (Jake) Kim, Arun Vijayakumar, Fnu Devender, and David J. Moreau "e-Beam detection of over-etch in semiconductor processing and how over-etch level is related to defect detection parameters", Proc. SPIE 11611, Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV, 116110N (22 February 2021); https://doi.org/10.1117/12.2584652

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