Semiconductor metrology for the 3D era

Janusz Bogdanowicz; Anne-Laure Charley; Philippe Leray

doi:10.1117/12.2666926

30 April 2023 Semiconductor metrology for the 3D era

Janusz Bogdanowicz, Anne-Laure Charley, Philippe Leray

Author Affiliations +

Proceedings Volume 12496, Metrology, Inspection, and Process Control XXXVII; 1249617 (2023) https://doi.org/10.1117/12.2666926
Event: SPIE Advanced Lithography + Patterning, 2023, San Jose, California, United States

Abstract

To enable the “endless progression of Moore’s law” [1], traditional scaling has moved from sufficient to a mere necessary condition. In other words, the concrete implementation of high-NA EUV lithography remains among the top R&D priorities of the semiconductor industry for the coming years. However, the roadmap predicts that other scaling boosters, all putting a strong emphasis on the third – vertical - dimension, will also play a critical role in allowing increased functionality from a fixed surface area of Si. In this presentation, we first review the challenges imposed on metrology and inspection by 3D devices in the context of GAA, 3DIC and 3D memories. We then discuss our work extracting buried information of various nature, i.e. dimensional, overlay and defectivity, using less conventional metrology. Finally, we recommend stronger focus on 3D see-through metrology to ensure the readiness of metrology as devices move deeper into the 3D era. [1]L. van den Hove, SPIE ALP (2022)

Conference Presentation

Citation Download Citation

Janusz Bogdanowicz, Anne-Laure Charley, and Philippe Leray "Semiconductor metrology for the 3D era", Proc. SPIE 12496, Metrology, Inspection, and Process Control XXXVII, 1249617 (30 April 2023); https://doi.org/10.1117/12.2666926

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