Scaling of parasitics in mm-wave MODFETs

Brian Hughes; Paul J. Tasker

doi:10.1117/12.20922

1 August 1990 Scaling of parasitics in mm-wave MODFETs

Brian Hughes, Paul J. Tasker

Proceedings Volume 1288, High-Speed Electronics and Device Scaling; (1990) https://doi.org/10.1117/12.20922
Event: Advances in Semiconductors and Superconductors: Physics Toward Devices Applications, 1990, San Diego, CA, United States

Abstract

Parasitics must be reduced for mm-wave MODFETs to realize their high potential. The parasitic resistances must be reduced so that (1) parasitic charging time is negligible, (2) to maintain the fj/fmax ratio, and (3) noise figure and power performance are not degraded significantly. The parasitic resistance must be scaled as l/fj. The problem of backside via inductance dominating the effective input resistance of wide MODFETs is shown. The design compromises are discussed, and rules-of-thumb are presented for scaling parasitics, (e.g., T-gate size).

Citation Download Citation

Brian Hughes and Paul J. Tasker "Scaling of parasitics in mm-wave MODFETs", Proc. SPIE 1288, High-Speed Electronics and Device Scaling, (1 August 1990); https://doi.org/10.1117/12.20922

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